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    ECNG 3016 Advanced Digital Electronics: Eneral Nformation

    Uploaded by

    Marlon Boucaud
    This document provides information about a lab assignment on digital system development using VHDL. The lab aims to help students understand the digital system development process and use of VHDL. It involves implementing an up-down counter in VHDL, simulating it in Modelsim, and testing it on a Spartan 3 FPGA development board. The key steps covered are system design, implementation and unit testing of modules, integration, further simulation testing, and on-board testing by mapping ports to FPGA pins. Results obtained from testing the up-down counter design match its expected behavior.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    ECNG 3016 Advanced Digital Electronics: Eneral Nformation

    Uploaded by

    Marlon Boucaud
    60 views11 pages
    This document provides information about a lab assignment on digital system development using VHDL. The lab aims to help students understand the digital system development process and use of VHDL. It involves implementing an up-down counter in VHDL, simulating it in Modelsim, and testing it on a Spartan 3 FPGA development board. The key steps covered are system design, implementation and unit testing of modules, integration, further simulation testing, and on-board testing by mapping ports to FPGA pins. Results obtained from testing the up-down counter design match its expected behavior.

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    Digital Electronics

    Original Title

    ecng3016_lab1a

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    This document provides information about a lab assignment on digital system development using VHDL. The lab aims to help students understand the digital system development process and use of VHDL. It involves implementing an up-down counter in VHDL, simulating it in Modelsim, and testing it on a Spartan 3 FPGA development board. The key steps covered are system design, implementation and unit testing of modules, integration, further simulation testing, and on-board testing by mapping ports to FPGA pins. Results obtained from testing the up-down counter design match its expected behavior.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    60 views11 pages

    ECNG 3016 Advanced Digital Electronics: Eneral Nformation

    Uploaded by

    Marlon Boucaud
    This document provides information about a lab assignment on digital system development using VHDL. The lab aims to help students understand the digital system development process and use of VHDL. It involves implementing an up-down counter in VHDL, simulating it in Modelsim, and testing it on a Spartan 3 FPGA development board. The key steps covered are system design, implementation and unit testing of modules, integration, further simulation testing, and on-board testing by mapping ports to FPGA pins. Results obtained from testing the up-down counter design match its expected behavior.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 11

    THE UNIVERSITY OF THE WEST INDIES

    ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES


    FACULTY OF ENGINEERING
    Department of Electrical & Computer Engineering

    ECNG 3016
    ADVANCED DIGITAL ELECTRONICS
    http://myelearning.sta.uwi.edu/course/view.php?id=686
    Semester II 2009
    1.

    GENERAL INFORMATION
    Lab #:
    Name of the Lab:

    1 Part A
    Introduction to Digital System Development using VHDL

    Lab Weighting:

    0%

    Delivery mode:

     Lecture
     Online
     Lab
     Other

    Venue for the Lab:

    Microprocessor Laboratory

    Lab Dependencies2

    The theoretical background to this lab is provided in ECNG 3016


    Theoretical content link: given at top of page
    Pre-Requisites ECNG 2004
    To undertake this lab, students should be able to:
    1. Use of Xilinx ISE and Modelsim in the implementation of digital
    system
    2. VHDL programming

    Recommended
    prior knowledge
    and skills3:

    Course Staff
    Lucien Ngalamou
    Marcus George

    Position/Role
    Lecturer
    Instructor

    Estimated total
    study hours1:

    E-mail
    
    lucien.ngalamou@sta.uwi.tt
    marcus.george@sta.uwi.tt

    Phone
    

    Office

    Office
    Hours

    room 202
    room 203

    THE UNIVERSITY OF THE WEST INDIES


    ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
    FACULTY OF ENGINEERING
    Department of Electrical & Computer Engineering

    2.

    LAB LEARNING OUTCOMES

    Upon successful completion of the lab assignment, students will be able to:
    1. Understand the process of digital system development
    2. Understand how VHDL can be used in digital system development
    3. Effectively use the Spartan 3 development board in on-board testing

    Cognitive
    Level
    C
    C, An
    Ap

    3. PRE-LAB
    Due Date:
    Submission
    Procedure:
    Estimated time to
    completion:
    3.1. Required Reading Resources
    3.2. Recommended Reading Resources
    3.3. Other Resources
    3.4. Pre-Lab Exercise

    THE UNIVERSITY OF THE WEST INDIES


    ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
    FACULTY OF ENGINEERING
    Department of Electrical & Computer Engineering

    4.

    IN-LAB

    Allotted Completion 3 hours


    Time:
    1 Computer
    Required lab
    1 Spartan 3 Toolkit
    Equipment:
    4.1. In-Lab Procedure

    4.1.1 Sample Procedure for digital system development


    Digital system development process consists of several steps. These are as follows:
    

    Step #1: Elicitation


    Awareness of problem at hand. Understanding the requirements/ design specification

    Step #2: Research


    Awareness of previous approaches used to solve the problem. Selection of a suitable
    approach to solving the problem at hand and getting aware of the principles involved in
    solving the problem using the chosen approach.

    Step #3: System design


    

    documentation of required system operation

    construction of datapath block diagrams, state diagrams, flow charts, truth tables, etc.

    algorithms

    documentation of system specification(done in parallel with construction of datapth


    block diagrams)

    Step #4: System Implementation + Unit Testing


    This is the translation of design specification into VHDL code. In this step modules
    are individually implemented and simulated using Modelsim 6.0XE before being
    integrated.

    Step #5: System Integration


    Implemented modules which have succeeded in unit testing must be port mapped

    together in a main file(VHDL module). A package(VHDL package) must also be created and
    components for all design entities must be include in package.
    1

    THE UNIVERSITY OF THE WEST INDIES


    ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
    FACULTY OF ENGINEERING
    Department of Electrical & Computer Engineering

    Step #6: Integration Testing


    After all functional VHDL modules are integrated then a overall system Modelsim
    simulation must be performed on main module.

    Step #7: On-board Testing


    After integration testing then an implementation constraint file must be created to map
    design ports to FPGA package pins. The bit file is then created and downloaded to the
    development board. The system is then thoroughly tested on the FPGA development board.

    Lab 1a: Introduction to Digital System Development using VHDL

    4.1.2 VHDL Implementation of an Up-Down Counter


    The up-down counter consists of five basic ports: clk, reset, ce, add, minus and
    dataout. When reset is set HIGH, the value inside each counter is set to zero. Once count enable
    ce is set HIGH, then the counter is enabled and hence the value inside the counter changes
    depending on the nature of the ports add and minus. When add is set HIGH the value inside the
    counter is incremented by one, while on the other hand if minus is set HIGH then value inside the
    counter is decremented by one. It is to be noted also that the value currently inside the counters is
    always assigned to the external port dataout. Figure 1 below shows the block diagram of the updown counter, while figure 2 gives its Modelsim simulation.

    Step #2.2: Draw datapath block diagram

    Figure 1: Block diagram of Up-Down Counter

    Lab 1a: Introduction to Digital System Development using VHDL

    Step #2.2: Algorithm


    Up_Down_Counter(clk, reset, ce, add, minus)
    begin
    create internal counter cnt
    if there is a rising edge of the clock pulse
    if reset = 1
    cnt <-- 00000000
    else if ce = 1 and add = 1
    cnt <-- cnt + 1
    else if ce = 1 and minus = 1
    cnt <-- cnt - 1
    else
    cnt <-- cnt
    end if
    endif
    dataout <-- cnt
    end

    Step #4: System Implementation + Unit Testing

    Lab 1a: Introduction to Digital System Development using VHDL

    Figure 2: Modelsim simulation of the Up-Down Counter

    Step #5: System Integration


    Since the up-down counter is the only module existing in this design then no integration is
    possible.
    Step #6: Integration Testing
    After all functional VHDL modules are integrated then an overall system Modelsim simulation
    must be performed on main module. In this case the up-down counter is the only module so
    therefore no additional simulation tests needs to be done here.
    Step #7: On-board Testing
    Create a new implementation constraint file, attach it to the up-down counter VHDL module
    and fill in the data given in table 1 below. The results obtained from testing the design on the FPGA
    development board using the pin configuration data from table 1 is given in the table 2 below.

    Lab 1a: Introduction to Digital System Development using VHDL

    Design Port

    FPGA Pin to be mapped to

    clk
    reset
    ce
    add
    minus
    dataout(0)
    dataout(1)
    dataout(2)
    dataout(3)
    dataout(4)
    dataout(5)
    dataout(6)
    dataout(7)

    T9
    any available pushbutton
    any available switch
    any available pushbutton
    any available pushbutton
    K12 - LED
    P14 - LED
    L12 - LED
    N14 - LED
    P13 - LED
    N12 - LED
    P12 - LED
    P11 - LED

    Table 1: Pin Configuration for the Up-Down Counter

    reset

    ce

    add

    dataout(7 to 0)

    minus

    LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

    1
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0

    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0

    0
    1
    1
    0
    0
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0
    0

    0
    0
    0
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    ON
    ON
    ON
    ON
    ON
    ON
    ON
    OFF
    OFF
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    OFF
    ON
    ON
    OFF
    OFF
    ON
    ON
    ON
    OFF
    OFF
    ON
    ON
    OFF
    OFF

    OFF
    OFF
    OFF
    OFF
    OFF
    ON
    OFF
    ON
    OFF
    ON
    OFF
    ON
    OFF
    ON
    OFF
    ON
    OFF
    ON
    OFF

    Table 2: Results obtained from testing design on FPGA Development board

    Lab 1a: Introduction to Digital System Development using VHDL

    Proceed to post-lab exercise.

    Lab 1a: Introduction to Digital System Development using VHDL

    5.

    POST-LAB

    A signed plagiarism declaration form must be submitted with your assignment.

    Due Date:
    Submission
    Procedure:
    Deliverables:

    End of Lab 1a: Introduction to Digital System Development using VHDL

    Lab 1a: Introduction to Digital System Development using VHDL

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