Digital Communication Lab Manual
Digital Communication Lab Manual
Digital Communication Lab Manual
IT 6313 DIGITAL
COMMUNICATION
LABORATORY MANUAL
II YEAR / III SEMESTER
REGULATION 2013
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
LABORATORY MANUAL
SYLLABUS
Digital Communication Lab (EC 591)
Contact: 3P
Credit: 2
(Students are required to perform at least ten experiments taking 3 from Group
A, 3 from Group B, 3 from Group C and 1 from Group D)
1.
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
LABORATORY MANUAL
Experiment No. 1
The names pseudo noise comes from the correlation properties of sequence of
N, is very large and Tb is very small, then the pn signal acts essentially like white
noise with a small DC component and hence is called Pseudo Noise Sequence.
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1
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SHIFT O/P
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0
RESULTS:
The output sequence is .. 111100010011010
Auto Correlation: Zoth = 2.44V
Z1th = 1.74 V
Z2nd = 1.72V
Z3rd = 2.44V
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
LABORATORY MANUAL
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
LABORATORY MANUAL
APPARATUS USED:
SL.
NO.
1
2
3
4
ITEM
Bread Board
CRO
Connecting Wires
IC 7495, IC 7486
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LABORATORY MANUAL
Experiment No: 2
Experiment Title: Studies of the properties of A/D and D/A converter
(AD7820/ADC0820 and ICL 8018A/8019A/8020A).(Properties like
transfer characteristics, code central line method of nonlinearity
study, differential nonlinearity, integral nonlinearity, resolution etc).
OBJECTIVE: This experiment will enable one to sense that to every input
digital word a single output analog value corresponds.
THEORY:
The digital to analog converters compose the devices transforming a digital
word binary encoded and generated for example by a computer, into a
discrete analog signal, in the sense that to every input digital word a single
output analog value corresponds.
The ideal characteristic of a 3 bit DAC is shown in Fig.1 and it is represented
by the straight line that connects the output discrete values corresponding to
the single input digital data
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FS
7.5
Analog
Output
Q
5
2.5
Let's consider now the possibility where only the most significant bit
(MSB) 7
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S3 is at level in the R resistance the current 13 = V REF / R will flow and therefore at
the operational amplifier output we will have the
voltage V 03 = -13 (R / 2) = -V REF /2
Analogously the contribution to output voltage provided by the immediately
less significant digit will result
V 02 = -12 (R / 2) = -(VREF / 2R) (R /2) = VREF/ 4 and so on
Vo1=-II(R/2) -(VREF 14R) (R 12) = -VREFI 8
V 00 = 10 (R / 2) = -(VREF / 8R) (R / 2) = -VREF / 16
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REF, will divide in node A into two identical currents but equal to the half of
the incoming one, as it is shown in Fig.4
Being
I3 = VREF/2R+(2R//2R) = VREF/3R
the potential of node A against ground is equal to
VA3 =2R. 13/2 = (1/3).VREF
and therefore at the operational amplifier output the voltage results
V03 = -3 R/ 2R. (1/3) .VREF = -V REF/2
Analogously the contribution to the output voltage of the immediately less
significant digit is determined by noticing that the current delivered from the
reference voltage V REF is equal to
12 = VREF/2R+(2R//2R) = VREF/3R = I3
and it divides itself in node B into two identical currents of value 12/2: this
now current will split equally at node A so the potential of node A against
ground is now equal to
VA2 = 2R. (12/4) = (1 16) .VREF
and therefore at the operational amplifier output the voltage
results V02 = -3R 12R. 1/6 VREF = -VREF /4
with analog reasoning we obtain .
I1= VREF /3R
VAl = 2R .(I1/8) = (1/12)
VREF V01 = -V REF / 8
and at the end
I0= VREF/3R
VAO = 2R(Io / 16) = (1 /24) VREF 9
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V00 = -V REF / 16
By applying the principle of effect superposition the output voltage results at the end
Vo = -V REF (8.S3 + 4. S2 + 2.S1 + I.So) /16
When all the bits are at logic level 1 the output voltage assumes the maximum
full scale value
VOFS = -0.9375 VREF
While the quantum that represents the increase of the output voltage in
correspondence of the least significant bit (LSB), results
Q = -0.0625 V REF
Analog to digital
THEORY:
The digital systems have been spreading considerably since they allow realizing
Complex functions accurately, low cost and in a way comparatively simple to implement.
Analog/digital converters are the natural interface between the world of physical
quantities that vary analogically i.e. in a continuous way and that of the digital control
systems which vary with finite increases. AID converters have numerous applications and
consequently have a high diffusion. Just think for example of the digital multi- meters.
Each one of this contains an AID converter for converting the analog quantity that has to
be measured to corresponding numerical value.
The analog/digital conversion is a logical process that requires conceptually twosteps: the quantizing and the coding. Quantization is the process that performs the
transformation of a continuous analog signal in a set of discrete levels. Soon
afterwards we combine through the coding each discrete levels with a digital word.
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111
110
101
100
011
010
001
000
The straight line is the continuous analog signal, while the staircase line is the quantized
corresponding signal. If we assume a binary code, the 8 quantized states are coded
through a 3 bits digital word and this corresponds to the output of a 3 bits AID converter.
The sequences of binary numbers starting from "000" and reaching "111" are assigned to
the 8 output states. Let us anal# in detail a few aspects of the quantized Signal. The first
aspect is the ution'" defined as the number of output states that can be coded through a
binary word of n bits; with n bits we can code 2 n output states. In this case we have a 3
bits quantizer; therefore we code 8 output states whereas with 12 bits we code 4096 of
them.. The diagram showed in figure 1 point out that in the quantized signal there are 2n
-1 = 7 threshold levels. These points are at 0.625-1.875
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-3.125 -4.375 -5.625 -6.875 -8.125 V. The threshold points have to be set accurately
to divide the range of the signal to quantize in correct quantized signals. The
voltages 1.25 -2.5 -3.75 -5 -6.25- 7.5 -8.75 V are the center points of each output
code word. The staircase quantization is the best possible approximation for a
straight line starting from the origin and reaching full scale. The range of the input
voltage for which the same output code is used is called "quantum". In figure 1, the
quantum is 1.25 V. In general the quantum is expressed by the relation:
V(t)
V
ta
a
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CLK
Reset
CTR
&
MSB
LSB
DAC
Vi
Let us apply a reset control. The counter goes to "0000" and the converter gives zero
voltage at the output. The comparator results at high level at the output, the first
pulse that leads the counter to "0001" and the converter output to 0.625 is let go. The
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converter remains in the starting state. When the new clock pulse passes the
counter goes to "0010" and the DAC output to 1.25 V. The process continues
until the counter receives the ninth pulse, its state then becomes "1001" and the
converter output goes to 5 .625 V and thus is larger than the voltage to converter.
The comparator output changes its state and so the clock pulses are not
transmitted to the counter any more. The word "1001" is then the digital
conversion of 5.0 V. The used converter allows the conversion of positive signals
included in the range from 0 to 5 V and has a maximum resolution of 0.625 V.
The counter converter is conceptually simple and its realization is of little difficulty
and cheap. On the other hand it is rather slow in the conversion. Moreover the
conversion time is not constant but depends upon the value to convert.
We start by setting the bit 3, thus "1000". The corresponding voltage is worth 5 V and
being lower than the voltage to convert we leave it at "1 ". We set to "1" the bit 2 too.
The word turns into "1100" corresponding to 7.5 V which is larger than the voltage to
convert. We put therefore at zero the bit 2 and we proceed to the bit 1 and set it to
"1". The corresponding word "1010" is worth 6.25 V still larger than 5.0 V, we put
than at zero the bit 1 and set to "1" the bit O. The word turns into "1001" and is worth
5.625 V. This value is still larger than 5.0 V and so the reading jams at "1000" which
is the digital conversion of the voltage 5.0 V. We can see as in this case we have
done only four comparisons to perform the conversion. In the case of an
n bits converter are required n comparisons instead of the 2n foreseen, in the worst
case, 'by the previous converter. We have to make a precise statement: while the
counter had convened 5.0 V into the word "1001 ", the successive approximation one
converts into "1000". This is because whereas the counter converter blocks the clock
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when the digital word goes over the value to convert and so approaches in
excess with the last significant bit, the successive approximation converter
approaches in deficiency.
APPARATUS USED :
SL.
NO.
1
2
5
ITEM
Trainer Kit
multimeter
Connecting Wires
Experiment No: 3
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Figure 6-2 also shows several clock signals and sample pulses that will be
explained in later sections of this chapter. An integrated circuit that performs
the PCM encoding and decoding functions is called a codec (coder/decoder),
which is also described in a later section of this chapter.
PCM SAMPLING
The function of a sampling circuit in a PCM transmitter is to periodically sample
the continually changing analog input voltage and convert those samples to a
series of constant-amplitude pulses that can more easily be converted to binary
PCM code. For the ADC to accurately convert a voltage to a binary code, the
voltage must be relatively constant so that the ADC can complete the conversion
before the voltage level changes. If not, the ADC would be continually attempting
to follow the changes and may never stabilize on any PCM code.
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Essentially, there are two basic techniques used to perform the natural sampling and
flat-top sampling. Natural sampling is shown is when tops of the sample pulses retain
their natural shape during the interval, making it difficult for an ADC to convert the
sample to a PCM , the frequency spectrum of the sampled output is different . The
amplitude of the frequency components produced from sample pulses decreases for
the higher harmonics in a (sin x)/x manner Pi information frequency spectrum
requiring the use of frequency equalizer) before recovery by a low-pass filter.
The most common method used for sampling voice signals in top sampling,
which is accomplished in sample-and-hold circuit. The sample and-hold circuit
is to sample the continually changing. Convert those samples to a series of
constant-amplitude PAM volt, the input voltage is sampled with a narrow pulse
and then hold until the next sample is taken. Figure 6-4 shows flat-top sampling,
4 shows, the sampling process alters the frequency spectrum and introduced
aperture error, which is when the amplitude of the sampled signal pulse time.
This prevents the recovery circuit in the PCM receive) Inducing the original
analog signal voltage. The magnitude of error of the analog signal voltage
changes while the sample is being taken and the width ' of the sample pulse.
Flat-top sampling, however, introduces fewer apertures natural sampling and
operates with a slower analog-to-digital converter.
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Chapter 6
APPARATUS USED:
SL.
NO.
1
2
3
4
5
ITEM
Trainer Kit
multimeter
Connecting Wires
CRO
Function Generator
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Experiment No: 4
Experiment Title: Studies of PSK modulator and demodulator,
connected by physical channel.
Objective:
Study of Carrier Modulation Techniques by Phase Shift Keying method.
THEORY
Phase-shift keying (PSK) is a digital modulation scheme that conveys data by
changing, or modulating, the phase of a reference signal (the carrier wave).
Any digital modulation scheme uses a finite number of distinct signals to
represent digital data. In the case of PSK, a finite number of phases are used.
Each of these phases is assigned a unique pattern of binary bits. Usually, each
phase encodes an equal number of bits. Each pattern of bits forms the symbol
that is represented by the particular phase. The demodulator, which is designed
specifically for the symbol-set used by the modulator, determines the phase of
the received signal and maps it back to the symbol it represents, thus recovering
the original data. This requires the receiver to be able to compare the phase of
the received signal to a reference signal such a system is termed coherent.
In Phase Shift Keying (PSK) modulation techniques, the modulated output
switches between in-phase and out-of phase component of the carrier
frequency for all 'one' to 'zero' transitions. The carrier frequency chosen for
PSK modulation are 1 MHz (o Degree) and 1 MHz (180 Degree)
CARRIER GENERA TOR block on DCL-05 generates the carrier waves 1 MHz (0
Degree) and 1 MHz (180 Degree), which are available at SIN 2 and SIN 3 post.
The PSK modulator is also built around the 2 to 1 Ana log Multiplexer which
switches between the 1 MHz (0 Degree) and 1 MHz (180 Degree) signals for all
'one' to 'zero" transitions occurring in the transmitted data stream.
The phase detector works in the principle of squaring loops. First step in PSK
detection is the sine to square wave conversion using an Schmitt trigger. This
enables the PSK detector to be built around digital IC's. The Biphase splitter basically
doubles the frequency component of the modulated data and also ensures that the
out of phase component of the modulation signal does not reach the PLL. The PLL
recovers the carrier frequency from the output of the phase splitter, but the frequency
of the recovered carrier is twice that of the transmitted carrier. So a Divide by 2
counter is used to divide the frequency of the PLL output by 2, thus recovering the
reference carrier. The delay flip-flop is used to compare the phase of the incoming
data and the reference carrier thereby recovering the data.
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Procedure:
1. Refer to the block diagram and carry out the following connections and
switch settings.
2. Connect power supply in proper polarity to the kits DCL-O5 and DCLO6 and switch it on.
3. Connect CLOCK and DATA generated on DCL-O5 to CODING CLOCK IN
and DATA INPUT respectively by means of the patch-chords provided.
4. Note: 8th switch of SW1 from data pattern generator is not used to generate
data pattern, output remains at low level irrespective of this switch position.
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier
Modulator logic.
6. Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of
the Carrier Modulator Logic.
7. Connect PSK modulated signal MODULATOR OUTPUT on DCL-O5 to
the PSK IN of the PSK DEMODULA TOR on DCL-O6.
8. Observe various waveforms as mentioned below.
.Observation:
Observe the following waveforms on oscilloscope and plot it on the paper.
On Kit DCL-O5
1. Input NRZ-L Data at CONTROL INPUT.
2. Carrier frequency SIN 2 and SIN 3.
3. PSK modulated signal at MODULATOR OUTPUT.
On Kit DCL-O6
1. PSK Modulated signal at PSK IN.
2. PSK Demodulated signal at PSK OUT.
3. Observe output of SINE TO SQUEARE CONVERTOR,
SQUARING LOOP, DIVIDE BY 2 on test points provided.
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Waveforms:
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5.
Experimental Kits Data Conditioning and Carrier Modulation (DCL05) & Data Reconditioning and Carrier Demodulation (DCL-06).
Power Supply
20 MHZ Dual Trace Oscilloscope
Multimeter
Patch Chords
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Experiment No: 5
Experiment Title: FREQUENCY SHIFT KEYING TECHNIQUES
Objective:
Study of Carrier Modulation Techniques by Frequency Shift Keying method:
Theory:
In Frequency Shift Keying modulation techniques, the modulated output
shifts between two frequencies for all 'one' (mark) to 'zero' (space)
transitions. The carrier frequency chosen for FSK modulation is 500 KHz
and 1 MHz. Note that the above frequencies are greater than twice the
modulating frequency. Note that the FSK may be thought of as an FM
system in which the carrier frequency is midway between the mark and
space frequencies, and modulation is by a square wave.
CARRIER GENERATOR block on DCL-O5 generates the carrier waves
500KHz and1 MHz, which are available at SIN1 and SIN2 post.
The FSK modulator is also built around the 2 to 1 Analog Multiplexer which
switches between the 500KHz and 1 MHz signals for all 'one' to 'zero" transitions.
FSK describes the modulation of a carrier (or two carriers) by using a different
frequency for a 1 or 0. The resultant modulated signal may be regarded as
the sum of two amplitude modulated signals of different carrier frequency
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier
Modulator logic.
6. Connect carrier component SIN 1 to INPUT1 and SIN 2 to INPuT2 of
the Carrier Modulator Logic.
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Observation:
Observe the following waveforms on oscilloscope and plot it on the paper.
On Kit DCL-O5
1. Input NRZ-L Data at CONTROL INPUT.
2. Carrier frequency SIN 1 and SIN 2.
3. FSK modulated signal at MODULATOR OUTPUT.
On Kit DCL-O6
1. FSK Modulated signal at FSK IN.
2. FSK Demodulated signal at FSK OUT.
3. Observe output of PHASE DETECTOR, LPF, VCO on test points provided.
Experimental Data:
NOTE: In FSK demodulator PLL circuit used is very sensitive to input voltage
level, because of which you may get blurred output signal if input power varies
slightly. To get clear signal at the output tune pot P3 in FSK Demodulator section.
To get better results set the following bit pattern for INPUT DATA:
10101010
10101110
11101010
00111010
11001100
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Waveforms:
Analysis:
A small phase lag exist between the modulating data and the recovered data
because of the limitation of tracking ability and the time response of PLL
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Switch Faults:
Note: Keep the connections as per the procedure. Now switch
corresponding fault switch button in ON condition & observe the different
effect on the output. The faults are normally used one at a time.
1. Put switch 1 of SF1 (DCL-O5) in Switch Fault section to ON position.
This will open capacitor for filtering of SIN 1 signal. Sine wave SIN 1
will be distorted and its amplitude gets reduced.
2. Put switch 2 of SF1 (DCL-O5) in Switch Fault section to ON position.
This VI/ill disable channel selection signal going to Modulator IC.
Modulator output contains only single channel (INPUT 1) data.
3. Put switch 2 of SF1 (DCL-O6) in Switch Fault section to ON position. This
will remove resistor connected to PLL in FSK demodulator. Center
frequency of PLL changes and output of FSK demodulator gets distorted.
Precautionary Measure to be taken:
10.
11.
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EXPERIMENT NO: 6
EXPERIMENT TITLE: AMPLITUDE SHIFT KEYING MODULATION
TECHNIQUES
Objective:
Study of Carrier Modulation Techniques by Amplitude Shift Keying method.
Theory:
Carrier modulation is a technique by which digital data is made to modulate a
continuous wave (sine wave) carrier. For all types of carrier modulation, the
carrier frequency should be at least 2 times that of modulating frequency. In
Amplitude shift keying, the carrier is transmitted when the modulating data is
'one' and the carrier is rejected from transmission when the data is 'zero'. In
DCL-O5 the ASK Modulators employs an Analog Multiplexer as a modulating
switch, which can switch between carrier and ground, for every 'one' to 'zero'
transitions. The carrier frequency chosen for ASK modulation is 1 MHz.
ASK DEMODULA TOR block on DCL-O6 employs an envelope detector to recover
the data from the modulated carrier. The ASK modulated input is fed to the half wave
rectifier. The rectified input is fed to the filter, where the original data is recovered.
The threshold detector is used to recover the original amplitude levels of the data.
So whenever the sinewave is transmitted, the detector identifies it as a 'one' and
whenever the carrier is absent, the detector identifies it as a 'zero'.
ASK describes the technique the carrier wave is multiplied by the digital signal f
(t). Mathematically, the modulated carrier signal s
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Apparatus Required:
Experimental Kits Data Conditioning and Carrier Modulation (DCL05) & Data Reconditioning and Carrier Demodulation (DCL-06).
Power Supply
20 MHZ Dual Trace Oscilloscope
Multimeter
Patch Chords
5. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier
Modulator logic.
6. Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2
of the Carrier Modulator Logic.
7. Connect ASK modulated signal MODULATOR OUTPUT on DCL-OS to
the ASK IN of the ASK DEMODULATOR on DCL-O6.
8. Observe various waveforms as mentioned below.
Observation:
Observe the following waveforms on oscilloscope and plot it on the paper.
On Kit DCL- O5
1. Input NRZ-L Data at CONTROL INPUT.
2. Carrier frequency SIN 2.
3. ASK modulated signal at MODULATOR OUTPUT.
On Kit DCL-O6
1. ASK Modulated signal at ASK IN.
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Waveforms:
Analysis:
It has been observed that a very small time lag between the modulating
data and the recovered data
Switch Faults:
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16.
12. Ensure that equipment or training kit switch is kept off While
connect it to main power supply.
13. For connecting any signal from one equipment to equipment or from
one section to other section of the same kit, ensure that signal is
grounded properly and subsequently connect the signal-to-signal line.
14. Handle gently all the necessary button or knob in the equipment
avoiding all other button or knobs which are not required to be adjusted
for the equipment.
15. For unusual spark of burning smell, immediately switch off the main
supply to the kit.
Ensure that, a signal is connected to an appropriate junction destined for it.
6. Always cover the equipment for dust protection after the experiment.
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
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Experiment No. 7
Experiment Title: Studies on Delta modulator & Demodulator using trainer kits.
If the signal amplitude has decreased, the modulator output is at logic level
0. Thus the output from the modulator is a series of zeros and ones to
indicate rise and fall of the waveform since the previous value.
One way in which Delta modulator and demodulator is assembled is as show in Fig.
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As it has been seen in case of modulator when the output from unipolar to
bipolar converter is applied to integrator, its output tries to follow the analog
signal in ramp fashion and hence is a good approximation of the signal itself.
The integrator's output contains sharp edges which are 'smoothened out' by
the Low - Pass Filter, whose cut-off frequency is just above the audio band.
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
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APPARATUS USED:
SL.
NO.
1
2
5
ITEM
Trainer Kit
CRO
Connecting Wire
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
LABORATORY MANUAL
Experiment No. 8
Experiment Title: Studies on Adaptive Delta modulation using trainer kits.
OBJECTIVE: This experiment will enable one to understand how an Adaptive Delta
Modulator Circuit can work to have a good result w.r.t delta modulator. This
experiment will also help to understand the operation of Digital modulation technique.
THEORY
As it has been seen, delta modulation system is unable to chase the rapidly
changing information of the analog signal which gives rise to distortion & hence
poor quality reception. This is known as slope overloading phenomenon. The
problem can be overcomed by increasing the integrator gain (i.e. step-size).
But using high step-size integrator would lead to a high quantization noise.
QUANTISATION NOISE:
It is defined as error introduced between the original signal & the quantized
signal due to the fixed step size in which the signal (quantized) is
incremented. As the error is random in nature & hence unpredictable, it can
be treated as noise. High quantization noise may play havoc on small
amplitude signals. The solution to this problem is to increase the integrator
gain for fast-changing input & to use normal gain for small amplitude signals.
The basic idea is to increase the integrator the integrator gain (it is doubled
on this trainer) when slope overload occurs. If still it is unable to catch up with
the signal, the integrator gain is doubled again. The integrator on board has
four available gains standard, standard X2, standard X4, and standard X8.
The integrator thus adopts itself to the gain where its lowest value can just
overcome the slope overloading effect. See fig. 6A.
the control circuit its output goes low. The counter now advance to 01 doubling the
integrator gain. This increases the ramping rate of the integrator & it is able to
catch the analog signal faster. In the next clock cycle if the same situation
continues the counter advances to '10' thus forcing the integrator gain to quadruple
its standard value. This situation continues till the counter advances to ' 11' where
it remains locked until the control logic does not detect a change in the bit level at
its input As soon as the control circuit detects a change in the bit level, its output
goes high, thus resetting the counter & thus normalizing the integrator gain.
In Adaptive Delta Demodulator the control circuit receives the same bit stream as
the transmitted one except for the fact that it is received after a half clock cycle
delay. The functioning of the Receiver's control circuit & counter is same as that of
the transmitter's block. Therefore, the demodulators output which itself is a good
approximation of the analog input signal accepts for the inherent spikes. The output
from integrator is passed to a Low Pass Filter to 'smooth out 'the waveform. Thus,
Adaptive Delta Modulation system is thus able to reduce slope-over load error at an
expense of small increase in quantization error. It turns out that in matter of speech
transmission the reduced slope error provides a net advantage in spite of slight
increase in quantization error & that the adaptive delta.
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FIG A
Control Word
00
01
10
11
Table 1
Integrator Gain
Standard
Standard X2
Standard X4
Standard X8
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FIG B
THE CONTROL CIRCUIT WORKS AS FOLLOWS: The control circuit compares the
preset data bit from D flip-flop with the previous two data bits. Its output to the
counter is high when the three bits are identical, the control circuits output goes low,
thus letting the counter advance with every clock cycle. This advancement continues
till the output from the control circuit does not go 'high'. Each time the counter is
incremented from 00 integrator gain is doubled till the counter reached '11' where it
remains in that state until it is reset by the counter. Similarly, the Adaptive Delta
Demodulator is alike Delta Demodulator except for two blocks
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namely, the control circuit & the counter. They function in the same way as in
modulator part, except for the fact that they are clocked by the receiver clock.
APPARATUS USED:
SL.
NO.
1
2
5
ITEM
Trainer Kit
CRO
Connecting Wire
PROCEDURES:
1.
2.
3.
4.
5.
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DIGITAL COMMUNICATION LAB (CODE:IT6313)
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Experiment No. 9
Experiment Title: Studies on Delta Signal Modulation using trainer kits.
OBJECTIVE: This experiment will enable one to understand how an Delta
Sigma Modulator Circuit can work to have a good result(to pass DC level
signal which is a must in video system w.r.t delta modulator).This experiment
will also help to understand the operation of Digital modulation technique.
THEORY
The Delta Modulation & Adaptive Delta Modulation suffers from two
serious limitations, namely,
(1) They are not able to pass DC. level information which is a must in video systems.
(2) The signal - to - noise ratio decreases as the signal frequency increases.
Both these serious limitations can be overcomed by Delta Sigma modulation.
The Delta Modulator on-board can pass DC level information if the integrators
are zeroed before hand (by level adjust presets) & the gains of integrator at two
ends (TX & RX) are exactly equal. This is possible on ST2105 board but not in
real life operation where TX & RX. are separated by hundreds of kms. & they are
expected to work over a long period without additional setting up.
The inherent short coming of the Delta Modulator to pass DC level
information is due to the fact that it passes the information about the change
in the voltage level & not the actual voltage level itself. It encodes the change
from -2V to -IV same as it would encode a change from +2V to +3V. J
In Delta Sigma Modulation the integrator is added hi front of the Delta sigma
modulator. This simple arrangement makes a big change in the circuit behaviors. It
now responds to actual voltage levels rather than the change in the voltage level. The
effect of the addition of integrator before the delta modulator can be done away by
adding a differentiator at the end of the receiver. The System looks as shown in
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The system shown in the Figures can be simplified further. Since the voltage
comparator is highly non-linear device cannot transfer the two integrations at
its input to one integration at its output.
The voltage comparator functionally can be thought of as a unity gain
differential amplifier followed by a zero-crossing detector.
If the voltage comparator is replaced by this circuit, the no. of integrators can
be reduced to one (at the output of unit-gain differential amplifier).Similarly,
since the low pass filter is a linear circuit element the effect of integrator at the
input of L.P.f...is nullified by the differentiator present at its output. Therefore
these two blocks are redundant in the receiver.
The resulting circuit looks as in Fig. 9A & 9B.
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To see how the circuit functions, suppose that initially the TX.DATA is at
logic * 1' & that input remains constant at+2V.
Since logic 1 is present at the input of Unipolar-to-Bipolar converter, its output is-4V,
which appear at- VE terminal of unity gain differential amplifier. Its output soon switches
to+6V. This +6V appears at the input of integrator which ramps down at a fast rate. As
soon as it crosses zero level, the zero-crossing detectors output goes zero
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which is latched in the coming clock cycle. Thus the D-Flip-Flops output goes
low & a zero is transmitted.
The zero's appearance at input of unipolar to bipolar converter makes it switch
its output to +4V. With +4V input to the unity gain differential amplifier, its output
goes to -2V level. Since -2V signal is present at input of integrator; it ramps up
slowly, as the rate of ramping depends on the input applied to it. The ramp will
not be able to cross-up zero at this slow rate, so again a zero is latched at the
next clock cycle. Thus the inference which can be drawn is that smaller the
signal at integrator input, slower it will ramp up or down thus latching the same
data bits for more clock periods. Thus the mark to space ratio conveys the
information about the mean level of the signal & the signal & the modulator's
output depends on the actual signal amplitude itself & not only on its change.
The received data is latched into D-Flip-Flop by the Receiver clock which has been
before being latched. The level changer provides the +VE & -VE voltages needed to
reconstruct the input analog signal. It also inverts the signal & compensate for the
inversion at transmitter automatically. The work of the low pass filter is to remove the
spikes introduced by switching action of unipolar to bipolar converter.
APPARATUS USED:
SL.
NO.
1
2
5
ITEM
Trainer Kit
CRO
Connecting Wires
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