Hi 7190
Hi 7190
Hi 7190
Data Sheet
FN3612.10
Features
22-Bit Resolution with No Missing Code
0.0007% Integral Non-Linearity (Typ)
20mV to 2.5V Full Scale Input Ranges
Internal PGIA with Gains of 1 to 128
Serial Data I/O Interface, SPI Compatible
Differential Analog and Reference Inputs
Internal or System Calibration
120dB Rejection of 60/50Hz Line Noise
Settling Time of 4 Conversions (Max) for a Step Input
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Process Control and Measurement
Industrial Weight Scales
Part Counting Scales
Laboratory Instrumentation
Seismic Monitoring
Magnetic Field Monitoring
Pinout
HI7190
20 LD SOIC, PDIP
TOP VIEW
SCLK
20 MODE
SDO
19 SYNC
SDIO
18 RESET
CS
17 OSC1
DRDY
16 OSC2
DGND
15 DVDD
AVSS
14 AGND
VRLO
13 AVDD
VRHI
12 VINHI
VCM 10
11 VINLO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HI7190
Ordering Information
PART
MARKING
TEMP.
RANGE
(C)
HI7190IP
HI7190IP
-40 to 85
20 Ld PDIP
E20.3
HI7190IPZ
HI7190IPZ
-40 to 85
20 Ld PDIP*
(Pb-free)
E20.3
HI7190IB
HI7190IB
-40 to 85
20 Ld SOIC
M20.3
HI7190IBZ
(Note)
HI7190IBZ
-40 to 85
20 Ld SOIC
(Pb-free)
M20.3
HI7190IBZ-T
(Note)
HI7190IBZ
-40 to 85
20 Ld SOIC
Tape and Reel
(Pb-free)
M20.3
HI7190EVAL
Evaluation Kit
PART
NUMBER
PACKAGE
PKG.
DWG. #
VRLO
REFERENCE
INPUTS
TRANSDUCER
BURN-OUT
CURRENT
MODULATOR
PGIA
VINHI
VINLO
DIGITAL FILTER
1
1-BIT
D/A
VCM
SERIAL INTERFACE
UNIT
CLOCK
GENERATOR
OSC1
OSC2
CONTROL REGISTER
CS
MODE
SCLK SDIO
SDO
FN3612.10
June 27, 2006
HI7190
Typical Application Schematic
10MHz
17
13
+5V
16
15
OSC1 OSC2
DVDD
AVDD
4.7F
4.7F
0.1F
1
0.1F
INPUT
INPUT
+5V
12
11
10
R1
SCLK
VINHI
VINLO
SDIO
VCM
SDO
3
DATA I/O
2
DATA OUT
19
SYNC
+2.5V
REFERENCE
9
8
7
-5V
+
0.1F
CS
VRLO
CS
5
DRDY
DRDY
18
AVSS
RESET
4.7F
AGND
14
SYNC
4
VRHI
MODE
DGND
RESET
20
FN3612.10
June 27, 2006
HI7190
Absolute Maximum Ratings
Thermal Information
Supply Voltage
AVDD to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS to AVDD
Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DVDD
ESD Tolerance (No Damage)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V
JA (C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND = 0V, VCM = AGND,
PGIA Gain = 1, OSCIN = 10MHz, Bipolar Input Range Selected, fN = 10Hz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.0007
0.0015
%FS
SYSTEM PERFORMANCE
Integral Non-Linearity, INL
Differential Non-Linearity
(Note 2)
LSB
See Table 1
V/C
Noise, eN
See Table 1
70
dB
120
dB
120
dB
Conversions
VREF
- VREF
VREF
AVSS
AVDD
1.0
nA
5.0
pF
2.5
200
nA
(Note 2)
1.2(VREF/Gain)
1.2(VREF/Gain)
1.2(VREF/Gain)
0.2(VREF/Gain)
2.4(VREF/Gain)
2.0
0.8
1.0
10
DIGITAL INPUTS
(Note 11)
FN3612.10
June 27, 2006
HI7190
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND = 0V, VCM = AGND,
PGIA Gain = 1, OSCIN = 10MHz, Bipolar Input Range Selected, fN = 10Hz (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5.0
pF
2.4
0.4
-10
10
10
pF
200
ns
50
ns
VIN = 0V
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
50
ns
500
ns
50
ns
ns
(Notes 2, 7)
(Note 7)
40
ns
(Note 7)
40
ns
(Note 7)
35
ns
(Note 2)
100
ns
(Note 2)
100
ns
(Note 2)
0.1
10
MHz
(Note 2)
30
ns
(Note 2)
IAVDD
1.5
mA
IAVSS
2.0
mA
IDVDD
SCLK = 4MHz
3.0
mA
SB = 0
15
32.5
mW
SB = 1
mW
PSRR
(Note 3)
-70
dB
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. Applies to both bipolar and unipolar input ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 4, R1 = 10k, CL = 50pF.
8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.
9. VREF = VRHI - VRLO.
10. These errors are on the order of the output noise shown in Table 1.
11. All inputs except OSC1. The OSC1 input VIH is 3.5V minimum.
FN3612.10
June 27, 2006
HI7190
Timing Diagrams
tSCLK
tPRE
CS
tDSU
tSCLKPW
tSCLKPW
SCLK
tDHLD
1ST BIT
SDIO
2ND BIT
CS
SCLK
SDIO
1ST BIT
2ND BIT
SDO
tACC
tDV
tDRDY
DRDY
CS
SCLK
SDIO
1
FN3612.10
June 27, 2006
HI7190
Pin Descriptions
20 LEAD
DIP, SOIC
PIN NAME
SCLK
Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the
falling edge.
SDO
Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
CS
DESCRIPTION
Chip Select Input. Used to select the HI7190 for a serial data transfer cycle. This line can be tied to DGND.
DRDY
An Active Low Interrupt indicating that a new data word is available for reading.
DGND
AVSS
VRLO
VRHI
10
VCM
Common Mode Input. Should be set to halfway between AVDD and AVSS .
11
VINLO
12
VINHI
Analog Input HI. Positive input of the PGIA. The VINHI input is connected to a current source that can be used to check
the condition of an external transducer. This current source is controlled via the Control Register.
13
AVDD
14
AGND
15
DVDD
16
OSC2
Used to connect a crystal source between OSC1 and OSC2 . Leave open otherwise.
17
OSC1
Oscillator Clock Input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the device,
or an external oscillator can drive OSC1 . The oscillator frequency should be 10MHz (Typ).
18
RESET
Active Low Reset Pin. Used to initialize the HI7190 registers, filter and state machines.
19
SYNC
Active Low Sync Input. Used to control the synchronization of a number of HI7190s. A logic 0 initializes the converter.
20
MODE
Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking
(Mode = 0) for the Serial Port.
R1
DUT
CL (INCLUDES STRAY
CAPACITANCE)
FIGURE 4.
R2
CESD
HUMAN BODY
CESD = 100pF
R1 = 10M
R2 = 1.5k
DUT
MACHINE MODEL
V
CESD = 200pF
R1 = 10M
R2 = 0
FIGURE 5A.
R1
R2
R1 = 1G
R2 = 1
DIELECTRIC
FIGURE 5B.
FN3612.10
June 27, 2006
HI7190
TABLE 1. NOISE PERFORMANCE WITH INPUTS CONNECTED TO ANALOG GROUND
HERTZ
SNR
ENOB
P-P NOISE
(V)
RMS NOISE
(V)
HERTZ
SNR
ENOB
P-P NOISE
(V)
RMS NOISE
(V)
6.0
GAIN = 16
GAIN = 1
10
132.3
21.7
9.8
1.5
10
120.1
19.7
39.8
25
129.5
21.2
13.6
2.1
25
114.8
18.8
73.4
11.1
113.5
18.6
85.1
12.9
30
127.7
20.9
16.6
2.5
30
50
126.3
20.7
19.5
3.0
50
111.0
18.1
114.4
17.3
109.6
17.9
134.0
20.3
60
125.6
20.6
21.2
3.2
60
100
122.4
20.0
30.7
4.6
100
105.5
17.2
214.8
32.5
250
95.2
15.5
699.1
105.9
250
107.7
17.6
166.7
25.3
500
98.1
16.0
505.3
76.6
500
89.1
14.5
1417.7
214.8
1000
83.5
13.6
2686.0
407.0
2000
62.6
10.1
30110.0
4562.1
1000
85.7
13.9
2101.8
318.5
2000
68.8
11.1
14661.6
2221.4
GAIN = 32
GAIN = 2
10
129.2
21.2
14.0
2.1
10
113.2
18.5
88.8
13.5
109.0
17.8
142.7
21.6
25
125.7
20.6
20.9
3.2
25
30
124.5
20.4
24.1
3.7
30
108.2
17.7
157.4
23.8
50
104.7
17.1
235.8
35.7
50
123.4
20.2
27.3
4.1
60
122.5
20.1
30.3
4.6
60
105.0
17.1
227.8
34.5
102.3
16.7
310.5
47.0
100
118.1
19.3
50.0
7.6
100
250
106.1
17.3
199.5
30.2
250
93.4
15.2
861.1
130.5
87.1
14.2
1782.7
270.1
500
96.9
15.8
580.1
87.9
500
1000
84.4
13.7
2435.6
369.0
1000
78.2
12.7
4990.4
756.1
2495.4
2000
57.0
9.2
57311.1
8683.5
2000
67.8
11.0
16469.7
GAIN = 64
GAIN = 4
10
125.9
20.6
20.5
3.1
10
106.7
17.4
186.2
28.2
25
123.1
20.1
28.4
4.3
25
102.9
16.8
288.4
43.7
101.9
16.6
325.8
49.4
30
121.8
19.9
32.8
5.0
30
50
119.9
19.6
40.9
6.2
50
98.5
16.1
479.8
72.7
98.9
16.1
459.8
69.7
60
119.9
19.6
40.9
6.2
60
100
116.1
19.0
63.2
9.6
100
96.3
15.7
620.2
94.0
250
85.5
13.9
2133.5
323.3
250
105.7
17.3
209.7
31.8
500
96.6
15.8
597.8
90.6
500
78.1
12.7
5025.0
761.4
1000
66.7
10.8
18693.5
2832.3
2000
50.5
8.1
120163.0
18206.5
1000
84.3
13.7
2469.5
374.2
2000
68.2
11.0
15656.1
2372.1
GAIN = 128
GAIN = 8
10
124.7
20.4
23.4
3.5
10
101.1
16.5
356.5
54.0
96.0
15.7
638.3
96.7
25
120.6
19.7
37.8
5.7
25
30
119.2
19.5
44.3
6.7
30
95.2
15.5
704.8
106.8
50
93.2
15.2
882.2
133.7
50
117.5
19.2
53.8
8.2
60
116.8
19.1
58.6
8.9
60
92.2
15.0
996.7
151.0
91.4
14.9
1086.6
164.6
100
112.1
18.3
100.0
15.2
100
250
101.4
16.5
345.2
52.3
250
79.4
12.9
4346.4
658.5
71.8
11.6
10439.2
1581.7
500
95.3
15.5
691.1
104.7
500
1000
83.1
13.5
2838.6
430.1
1000
60.1
9.7
39923.0
6048.9
2347.7
2000
44.8
7.1
233238.2
35339.1
2000
68.3
11.1
15494.7
FN3612.10
June 27, 2006
HI7190
Definitions
Integral Non-Linearity, INL, is the maximum deviation of
any digital code from a straight line passing through the
endpoints of the transfer function. The endpoints of the
transfer function are zero scale (a point 0.5 LSB below the
first code transition 000...000 and 000...001) and full scale (a
point 0.5 LSB above the last code transition 111...110 to
111...111).
Differential Non-Linearity, DNL, is the deviation from the
actual difference between midpoints and the ideal difference
between midpoints (1 LSB) for adjacent codes. If this
difference is equal to or more negative than 1 LSB, a code
will be missed.
Offset Error, VOS , is the deviation of the first code transition
from the ideal input voltage (VIN - 0.5 LSB). This error can
be calibrated to the order of the noise level shown in Table 1.
Full Scale Error, FSE, is the deviation of the last code
transition from the ideal input full scale voltage
(VIN- + VREF/Gain - 1.5 LSB). This error can be calibrated
to the order of the noise level shown in Table 1.
Input Span, defines the minimum and maximum input
voltages the device can handle while still calibrating properly
for gain.
Noise, eN , Table 1 shows the peak-to-peak and RMS noise
for typical notch and -3dB frequencies. The device
programming was for bipolar input with a VREF of +2.5V. This
implies the input range is 5V. The analysis was performed on
100 conversions with the peak-to-peak output noise being
the difference between the maximum and minimum readings
over a rolling 10 conversion window. The equation to convert
the peak-to-peak noise data to ENOB is:
ENOB = Log2 (VFS/VNRMS)
where: VFS = 5V, VNRMS = VNP-P/CF and
CF = 6.6 (Empirical Crest Factor)
The noise from the part comes from two sources, the
quantization noise from the analog-to-digital conversion
process and device noise. Device noise (or Wideband
Noise) is independent of gain and essentially flat across the
frequency spectrum. Quantization noise is ratiometric to
input full scale (and hence gain) and its frequency response
is shaped by the modulator.
Looking at Table 1, as the cutoff frequency increases the
output noise increases. This is due to more of the
quantization noise of the part coming through to the output
and, hence, the output noise increases with increasing -3dB
frequencies. For the lower notch settings, the output noise is
dominated by the device noise and, hence, altering the gain
has little effect on the output noise. At higher notch
frequencies, the quantization noise dominates the output
Circuit Description
The HI7190 is a monolithic, sigma delta A/D converter which
operates from 5V supplies and is intended for
measurement of wide dynamic range, low frequency signals.
It contains a Programmable Gain Instrumentation Amplifier
(PGIA), sigma delta ADC, digital filter, bidirectional serial port
(compatible with many industry standard protocols), clock
oscillator, and an on-chip controller.
The signal and reference inputs are fully differential for
maximum flexibility and performance. Normally VRHI and
VRLO are tied to +2.5V and AGND respectively. This allows
for input ranges of 2.5V and 5V when operating in the
unipolar and bipolar modes respectively (assuming the PGIA
is configured for a gain of 1). The internal PGIA provides
input gains from 1 to 128 and eliminates the need for
external pre-amplifiers. This means the device will convert
signals ranging from 0V to +20mV and 0V to +2.5V when
operating in the unipolar mode or signals in the range of
20mV to 2.5V when operating in the bipolar mode.
The input signal is continuously sampled at the input to the
HI7190 at a clock rate set by the oscillator frequency and the
selected gain. This signal then passes through the sigma
delta modulator (which includes the PGIA) and emerges as a
pulse train whose code density contains the analog signal
information. The output of the modulator is fed into the sinc3
digital low pass filter. The filter output passes into the
calibration block where offset and gain errors are removed.
The calibrated data is then coded (2s complement, offset
binary or binary) before being stored in the Data Output
Register. The Data Output Register update rate is
determined by the first notch frequency of the digital filter.
This first notch frequency is programmed into HI7190 via the
Control Register and has a range of 10Hz to 1.953kHz which
corresponds to -3dB frequencies of 2.62Hz and 512Hz
respectively.
Output data coding on the HI7190 is programmable via the
Control Register. When operating in bipolar mode, data
output can be either 2s complement or offset binary. In
unipolar mode output is binary.
The DRDY signal is used to alert the user that new output
data is available. Converted data is read via the HI7190
serial I/O port which is compatible with most synchronous
transfer formats including both the Motorola 6805/11 series
FN3612.10
June 27, 2006
HI7190
SPI and Intel 8051 series SSR protocols. Data Integrity is
always maintained at the HI7190 output port. This means
that if a data read of conversion N is begun but not finished
before the next conversion (conversion N + 1) is complete,
the DRDY line remains active (low) and the data being read
is not overwritten.
The HI7190 provides many calibration modes that can be
initiated at any time by writing to the Control Register. The
device can perform system calibration where external
components are included with the HI7190 in the calibration
loop or self-calibration where only the HI7190 itself is in the
calibration loop. The On-chip Calibration Registers are
read/write registers which allow the user to read calibration
coefficients as well as write previously determined
calibration coefficients.
Circuit Operation
The analog and digital supplies and grounds are separate
on the HI7190 to minimize digital noise coupling into the
analog circuitry. Nominal supply voltages are AVDD = +5V,
DVDD = +5V, and AVSS = -5V. If the same supply is used
for AVDD and DVDD it is imperative that the supply is
separately decoupled to the AVDD and DVDD pins on the
HI7190. Separate analog and digital ground planes should
be maintained on the system board and the grounds should
be tied together back at the power supply.
When the HI7190 is powered up it needs to be reset by
pulling the RESET line low. The reset sets the internal
registers of the HI7190 as shown in Table 2 and puts the part
in the bipolar mode with a gain of 1 and offset binary coding.
The filter notch of the digital filter is set at 30Hz while the I/O
is set up for bidirectional I/O (data is read and written on the
SDIO line and SDO is three-stated), descending byte order,
and MSB first data format. A self calibration is performed
before the device begins converting. DRDY goes low when
valid data is available at the output.
TABLE 2. REGISTER RESET VALUES
REGISTER
VALUE (HEX)
XXXX (Undefined)
Control Register
28B300
10
FN3612.10
June 27, 2006
HI7190
junction. The feedback loop forces the average of the fed
back signal to be equal to the input signal VIN .
PGIA
+
VIN
INTEGRATOR
COMPARATOR
DAC
VRHI
VRLO
Analog Inputs
GAIN
SAMPLING RATE
(kHz)
INPUT IMPEDANCE
(M)
78.125
1.6
156.25
0.8
312.5
0.4
VCM Input
625
0.2
The voltage at the VCM input is the voltage that the internal
analog circuitry is referenced to and should always be tied to
the midpoint of the AVDD and AVSS supplies. This point
provides a common mode input voltage for the internal
operational amplifiers and must be driven from a low noise,
low impedance source if it is not tied to analog ground.
Failure to do so will result in degraded HI7190 performance.
It is recommended that VCM be tied to analog ground when
operating off of AVDD = +5V and AVSS = -5V supplies.
FN3612.10
June 27, 2006
HI7190
the conversion. It can not, however, remove noise present
on the analog signal prior to the ADC (which an analog filter
can).
HI7190
AVDD
RATIOMETRIC
CONFIGURATION
CURRENT
SOURCE
LOAD CELL
VRHI
VRLO
VINHI
fMODULATOR = fOSC/128
VINLO
AVSS
The filter then converts the serial modulator data into 40-bit
words for processing by the Hogenauer filter. The data is
decimated in the filter at a rate determined by the CODE
word FP10-FP0 (programed by the user into the Control
Register) and the external clock rate. The equation is:
MODULATOR OUTPUT
MODULATOR
CLOCK
DIGITAL
FILTER
CLOCK
GENERATOR
CALIBRATION
AND CONTROL
SYNC
SERIAL I/O
OSC2
OSC1
SDO
SDIO
SCLK
CS
DRDY
RESET
Digital Filtering
One advantage of digital filtering is that it occurs after the
conversion process and can remove noise introduced during
12
The Control Register has 11 bits that select the filter cutoff
frequency and the first notch of the filter. The output data
update rate is equal to the notch frequency. The notch
frequency sets the Nyquist sampling rate of the device while
the -3dB point of the filter determines the frequency
spectrum of interest (fS). The FP bits have a usable range of
10 through 2047 where 10 yields a 1.953kHz Nyquist rate.
The Hogenauer filter contains alias components that reflect
around the notch frequency. If the spectrum of the frequency
of interest reaches the alias component, the data has been
aliased and therefore undersampled.
Filter Characteristics
Please note: We have recently discovered a
performance anomaly with the HI7190. The problem
occurs when the digital code for the notch filter is
programmed within certain frequencies. We believe the
error is caused by the calibration logic and the digital
notch code NOT the absolute frequency. The error is
seen when the user applies mid-scale (0V input, Bipolar
mode). With this input, the expected digital output
FN3612.10
June 27, 2006
HI7190
should be mid-scale (800000h). Instead, there is a small
probability, of an erroneous negative full scale (000000h)
output. Refer to Technical Brief TB348 for complete
details.
The FP10 to FP0 bits programmed into the Control Register
determine the cutoff (or notch) frequency of the digital filter.
The allowable code range is 00AH . This corresponds to a
maximum and minimum cutoff frequency of 1.953kHz and
10Hz, respectively when operating at a clock frequency of
10MHz. If a 1MHz clock is used then the maximum and
minimum cutoff frequencies become 195.3kHz and 1Hz,
respectively. A plot of the (sinx/x)3 digital filter characteristics
is shown in Figure 9. This filter provides greater than 120dB
of 50Hz or 60Hz rejection. Changing the clock frequency or
the programming of the FP bits does not change the shape
of the filter characteristics, it merely shifts the notch
frequency. This low pass digital filter at the output of the
converter has an accompanying settling time for step inputs
just as a low pass analog filter does. New data takes
between 3 and 4 conversion periods to settle and update on
the serial port with a conversion period tCONV being equal to
1/fN .
clock frequency and gain, determines the allotted time for the
input capacitor to charge. The addition of external components
may cause the charge time of the capacitor to increase beyond
the allotted time. The result of the input not settling to the proper
value is a system gain error which can be eliminated by system
calibration of the HI7190.
Clocking/Oscillators
The master clock into the HI7190 can be supplied by either a
crystal connected between the OSC1 and OSC2 pins as
shown in Figure 10A or a CMOS compatible clock signal
connected to the OSC1 pin as shown in Figure 10B. The
input sampling frequency, modulator sampling frequency,
filter -3dB frequency, output update rate, and calibration time
are all directly related to the master clock frequency, fOSC .
For example, if a 1MHz clock is used instead of a 10MHz
clock, what is normally a 10Hz conversion rate becomes a
1Hz conversion rate. Lowering the clock frequency will also
lower the amount of current drawn from the power supplies.
Please note that the HI7190 specifications are written for a
10MHz clock only.
10MHz
0
ALIAS BAND
fN fC
17
16
OSC1
OSC2
HI7190
AMPLITUDE (dB)
-20
-40
FIGURE 10A.
-60
10MHz
NO
CONNECTION
-80
-100
17
-120
OSC1
fC
fN
2fN
3fN
16
HI7190
OSC2
4fN
FREQUENCY (Hz)
FIGURE 10B.
Input Filtering
The digital filter does not provide rejection at integer
multiples of the modulator sampling frequency. This implies
that there are frequency bands where noise passes to the
output without attenuation. For most cases this is not a
problem because the high oversampling rate and noise
shaping characteristics of the modulator cause this noise to
become a small portion of the broadband noise which is
filtered. However, if an anti-alias filter is necessary a single
pole RC filter is usually sufficient.
If an input filter is used the user must be careful that the source
impedance of the filter is low enough not to cause gain errors in
the system. The DC input impedance at the inputs is > 1G but
it is a dynamic load that changes with clock frequency and
selected gain. The input sample rate, also dependent upon
13
Operational Modes
The HI7190 contains several operational modes including
calibration modes for cancelling offset and gain errors of
both internal and external circuitry. A calibration routine
should be initiated whenever there is a change in the
ambient operating temperature or supply voltage. Calibration
should also be initiated if there is a change in the gain, filter
notch, bipolar, or unipolar input range. Non-calibrated data
can be obtained from the device by writing 000000 to the
Offset Calibration Register, 800000 (h) to the Positive Full
Scale Calibration Register, and 800000 (h) to the Negative
Full Scale Calibration Register. This sets the offset
correction factor to 0 and both the positive and negative gain
slope factors to 1.
FN3612.10
June 27, 2006
HI7190
The HI7190 offers several different modes of Self-Calibration
and System Calibration. For calibration to occur, the on-chip
microcontroller must convert the modulator output for three
different input conditions - zero-scale, positive full scale,
and negative full scale. With these readings, the HI7190
can null any offset errors and calculate the gain slope factor
for the transfer function of the converter. It is imperative that
the zero-scale calibration be performed before either of the
gain calibrations. However, the order of the gain calibrations
is not important.
The calibration modes are user selectable in the Control
Register by using the MD bits (MD2-MD0) as shown in
Table 4. DRDY will go low indicating that the calibration is
complete and there is valid data at the output.
TABLE 4. HI7190 OPERATIONAL MODES
MD2
MD1
MD0
OPERATIONAL MODE
Conversion
Reserved
Conversion Mode
For Conversion Mode operation the HI7190 converts the
differential voltage between VINHI and VINLO . From
switching into this mode it takes 3 conversion periods (3 x
1/fN) for DRDY to go low and new data to be valid. No
calibration coefficients are generated when operating in
Conversion Mode as data is calibrated using the existing
calibration coefficients.
Self-Calibration Mode
Please note: Self-calibration is only valid when operating in a
gain of one. In addition, the offset and gain errors are not
reduced as with the full system calibration.
The Self-Calibration Mode is a three step process that
updates the Offset Calibration Register, the Positive Full
Scale Calibration Register, and the Negative Full Scale
Calibration Register. In this mode an internal offset
calibration is done by disconnecting the external inputs and
shorting the inputs of the PGIA together. After 3 conversion
periods the Offset Calibration Register is updated with the
value that corrects any internal offset errors.
14
FN3612.10
June 27, 2006
HI7190
System Offset/Internal Gain Calibration Mode
Please note: System Offset/Internal Gain is only valid when
operating in a gain of one. In addition, the offset and gain errors
are not reduced as with the full system calibration.
The System Offset/Internal Gain Calibration Mode is a single
step process that updates the Offset Calibration Register,
the Positive Full Scale Calibration Register, and the
Negative Full Scale Calibration Register. First the external
differential signal applied to the VIN inputs is converted and
that value is stored in the Offset Calibration Register. The
user must apply the zero point or offset voltage to the
HI7190 analog inputs and allow the signal to settle before
selecting this mode.
After this is completed the Positive and Negative Full Scale
Calibration Registers are updated. The inputs VINHI and VINLO
are disconnected and the external reference is switched in. The
HI7190 then takes 3 conversion cycles to sample the data and
update the Positive Full Scale Calibration Register. Next the
polarity of the reference voltage across the VINHI and VINLO
terminals is reversed and after 3 conversion cycles the
Negative Full Calibration Register is updated. The values
stored in the Positive and Negative Full Scale Calibration
Registers correct for any internal gain errors in the A/D transfer
function. After 3 more conversion cycles, the DRDY line will
activate signaling that the calibration is complete and valid data
is present in the Data Output Register.
Serial Interface
The HI7190 has a flexible, synchronous serial communication
port to allow easy interfacing to many industry standard
microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including
both the Motorola 6805/11 SPI and Intel 8051 SSR protocols.
The Serial Interface is a flexible 2-wire or 3-wire hardware
interface where the HI7190 can be configured to read and
write on a single bidirectional line (SDIO) or configured for
writing on SDIO and reading on the SDO line.
The interface is byte organized with each register byte
having a specific address and single or multiple byte
transfers are supported. In addition, the interface allows
flexibility as to the byte and bit access order. That is, the user
can specify MSB/LSB first bit positioning and can access
bytes in ascending/descending order from any byte position.
The serial interface allows the user to communicate with 5
registers that control the operation of the device.
Data Output Register - a 24-bit, read only register
containing the conversion results.
Control Register - a 24-bit, read/write register containing
the setup and operating modes of the device.
Offset Calibration Register - a 24-bit, read/write register
used for calibrating the zero point of the converter or system.
Positive Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Positive Full Scale
point of the converter or system.
Negative Full Scale Calibration Register - a 24-bit,
read/write register used for calibrating the Negative Full
Scale point of the converter or system.
There are limits to the amount of offset and gain which can
be adjusted out for the HI7190. For both bipolar and unipolar
modes the minimum and maximum input spans are
0.2 x VREF /GAIN and 1.2 x VREF /GAIN respectively.
Two clock modes are supported. The HI7190 can accept the
serial interface clock (SCLK) as an input from the system or
generate the SCLK signal as an output. If the MODE pin is
logic low the HI7190 is in external clocking mode and the
SCLK pin is configured as an input. In this mode the user
supplies the serial interface clock and all interface timing
specifications are synchronous to this input. If the MODE pin
is logic high the HI7190 is in self-clocking mode and the
SCLK pin is configured as an output. In self-clocking mode,
SCLK runs at FSCLK = OSC1 /8 and stalls high at byte
boundaries. SCLK does NOT have the capability to stall low
in this mode. All interface timing specifications are
synchronous to the SCLK output.
In the unipolar mode the offset plus the span cannot exceed
the 1.2 x VREF /GAIN limit. So, if the span is at its minimum
Reserved
This mode is not used in the HI7190 and should not be
selected. There is no internal detection logic to keep this
condition from being selected and care should be taken not
to assert this bit combination.
15
FN3612.10
June 27, 2006
HI7190
case of CS inactive during the clock stall time it takes 1 OSC1
cycle plus prop delay (Max) for the outputs to be disabled.
DATA OUT
BIDIRECTIONAL DATA
PORT CLOCK
CHIP SELECT
DEVICE STATUS
CLOCK MODE
SDO - Serial Data out. Data is read from this line using those
protocols with separate lines for transmitting and receiving
data. An example of such a standard is the Motorola Serial
Peripheral Interface (SPI) using the 68HC05 and 68HC11
family of microcontrollers, or other similar processors. In the
case of using bidirectional data transfer on SDIO, SDO does
not output data and is set in a high impedance state.
SDIO - Serial Data in or out. Data is always written to the
device on this line. However, this line can be used as a
bidirectional data line. This is done by properly setting up the
Control Register. Bidirectional data transfer on this line can
be used with Intel standard serial interfaces (SSR, Mode 0)
in MCS51 and MCS96 family of microcontrollers, or other
similar processors.
SCLK - Serial clock. The serial clock pin is used to
synchronize data to and from the HI7190 and to run the port
state machines. In Synchronous External Clock Mode, SCLK
is configured as an input, is supplied by the user, and can
run up to a 5MHz rate. In Synchronous Self Clocking Mode,
SCLK is configured as an output and runs at OSC1/8.
37
SDIO
SCLK
HI7190
CS
DRDY
MODE
29
SDO
41
45
89
121
125
OSC1
CS
SCLK
16
FN3612.10
June 27, 2006
HI7190
DRDY - Data Ready. This is an output status flag from the
device to signal that the Data Output Register has been
updated with the new conversion result. DRDY is useful as an
edge or level sensitive interrupt signal to a microprocessor or
microcontroller. DRDY low indicates that new data is available
at the Data Output Register. DRDY will return high upon
completion of a complete Data Output Register read cycle.
MODE - Mode. This input is used to select between
Synchronous Self Clocking Mode (1) or the Synchronous
External Clocking Mode (0). When this pin is tied to VDD the
serial port is configured in the Synchronous Self Clocking
mode where the synchronous shift clock (SCLK) for the serial
port is generated by the HI7190 and has a frequency of
OSC1/8. When the pin is tied to DGND the serial port is
configured for the Synchronous External Clocking Mode
where the synchronous shift clock for the serial port is
generated by an external device up to a maximum frequency
of 5MHz.
CS
INSTRUCTION
BYTE
17
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
SDIO
INSTRUCTION
CYCLE
DATA TRANSFER
CS
INSTRUCTION
BYTE
SDIO
INSTRUCTION
CYCLE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
SDO
DATA TRANSFER
FN3612.10
June 27, 2006
HI7190
Instruction Register
The Instruction Register is an 8-bit register which is used
during a communications cycle for setting up read/write
operations.
INSTRUCTION REGISTER
MSB
LSB
R/W
MB1
MB0
FSC
A3
A2
A1
A0
DESCRIPTION
Write Operation
R/W - Bit 7 of the Instruction Register determines whether a
read or write operation will be done following the instruction
byte load. 0 = READ, 1 = WRITE.
MB1, MB0 - Bits 6 and 5 of the Instruction Register
determine the number of bytes that will be accessed
following the instruction byte load. See Table 5 for the
number of bytes to transfer in the transfer cycle.
TABLE 5. MULTIPLE BYTE ACCESS BITS
MB1
MB0
DESCRIPTION
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
DESCRIPTION
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
18
FN3612.10
June 27, 2006
HI7190
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
BYTE 2
MSB
22
21
20
19
18
17
16
D23
D22
D21
D20
D19
D18
D17
D16
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
BYTE 1
15
14
13
12
11
10
D15
D14
D13
D12
D11
D10
D9
D8
IR WRITE PHASE
CS
LSB
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
I0
SDIO
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
THREE-STATE
SDO
B6
B7
B8
B9
B10
THREE-STATE
IR WRITE PHASE
CS
SCLK
B15
SDIO
I0
I1
I2
SDO
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
THREE-STATE
THREE-STATE
IR WRITE PHASE
CS
SCLK
SDIO
I0
I1
I2
I3
I4
I5
I6
I7
B15
B0
SDO
B1
B2
B3
B4
B5
B6
B7
B8
B9
FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW
19
FN3612.10
June 27, 2006
HI7190
IR WRITE PHASE
CS
SCLK
I0
SDIO
I1
I2
I3
I4
I5
I6
I7
B15
B0
SDO
B1
B2
B3
B4
B5
B6
B7
B8
B9
FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH
IR WRITE PHASE
CS
SCLK
B15
SDIO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
THREE-STATE
SDO
B8
B9
B10
THREE-STATE
FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW
IR WRITE PHASE
CS
SCLK
B15
I0
SDIO
I1
SDO
I2
I3
I4
I5
I6
I7
B0
B1
THREE-STATE
B2
B3
B4
B5
B6
B7
B8
B9
THREE-STATE
FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH
Control Register
The Control Register contains 24-bits to control the various
sections of the HI7190. This register is a read/write
register.
BYTE 2
MSB
22
21
20
19
18
17
16
DC
FP10
FP9
FP8
FP7
FP6
FP5
FP4
BYTE 1
15
14
13
12
11
10
FP3
FP2
FP1
FP0
MD2
MD1
MD0
B/U
BYTE 0
7
LSB
G2
G1
G0
BO
SB
BD
MSB
SDL
20
HI7190
Changing the filter notch frequency, as well as the selected
gain, impacts resolution. The output data rate (or effective
conversion time) for the device is equal to the frequency
selected for the first notch to the filter. For example, if the
first notch of the filter is selected at 50Hz then a new word is
available at a 50Hz rate or every 20ms. If the first notch is at
1kHz a new word is available every 1ms.
The settling-time of the converter to a full scale step input
change is between 3 and 4 times the data rate. For example,
with the first filter notch at 50Hz, the worst case settling time
to a full scale step input change is 80ms. If the first notch is
1kHz, the settling time to a full scale input step is 4ms
maximum.
The -3dB frequency is determined by the programmed first
notch frequency according to the relationship:
f -3dB = 0.262 x fNOTCH .
MD2 through MD0 - Bits 11 through 9 are the Operational
Modes of the converter. See Table 4 for the Operational
Modes description. After a RESET is applied to the part
these bits are set to the self calibration mode.
B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is
set the HI7190 is configured for bipolar operation. When this
bit is reset the part is in unipolar mode. This bit is set after a
RESET is applied to the part.
G2 through G0 - Bits 7 through 5 select the gain of the input
analog signal. The gain is accomplished through a
programmable gain instrumentation amplifier that gains up
incoming signals from 1 to 8. This is achieved by using a
switched capacitor voltage multiplier network preceding the
modulator. The higher gains (i.e., 16 to 128) are achieved
through a combination of a PGIA gain of 8 and a digital
multiply after the digital filter (see Table 7). The gain will
affect noise and Signal to Noise Ratio of the conversion.
These bits are cleared to a gain of 1 (G2, G1, G0 = 000) after
a RESET is applied to the part.
TABLE 7. GAIN SELECT BITS
G2
G1
G0
GAIN
GAIN ACHIEVED
16
32
64
128
21
FN3612.10
June 27, 2006
HI7190
result in conversion X + 1 data overwriting conversion X
results. For example, with fOSC = 10MHz, fN = 2kHz, the
read cycle must start within 1/2000 - 128(1/106) = 487s
after DRDY went low.
2) The Data Output Register read cycle for conversion X
must be completed within 2(1/fN)-1440(1/fOSC) after DRDY
initially goes active low. If the read cycle for conversion X is
not complete within this time the results of conversion X + 1
are lost and results from conversion X + 2 are now stored in
the data output word buffer.
Completing the Data Output Register read cycle inactivates
the DRDY interrupt. If the one word data output buffer is full
when this read is complete this data will be immediately
transferred to the Data Output Register and a new DRDY
interrupt will be issued after the minimum DRDY pulse high
time is met.
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
BYTE 1
15
14
13
12
11
10
P15
P14
P13
P12
P11
P10
P9
P8
BYTE 0
7
LSB
P7
P6
P5
P4
P3
P2
P1
P0
MSB
22
21
20
19
18
17
16
N23
N22
N21
N20
N19
N18
N17
N16
BYTE 1
BYTE 2
MSB
22
21
20
19
18
17
16
15
14
13
12
11
10
O23
O22
O21
O20
O19
O18
O17
O16
N15
N14
N13
N12
N11
N10
N9
N8
BYTE 0
BYTE 1
15
14
13
12
11
10
O15
O14
O13
O12
O11
O10
O9
O8
LSB
N7
N6
N5
N4
N3
N2
N1
N0
BYTE 0
7
LSB
O7
O6
O5
O4
O3
O2
O1
O0
22
FN3612.10
June 27, 2006
HI7190
Die Characteristics
DIE DIMENSIONS
PASSIVATION
3550m x 6340m
Type: Sandwich
Thickness:Nitride 8k
USG 1k
METALLIZATION
Type: AlSiCu
Thickness:Metal 2, 16k
Metal 1, 6k
SYNC
MODE
SCLK
SDO
SDIO
HI7190
OSC1
CS
DRDY
OSC2
DGND
DVDD
AVSS
23
AVDD
VINHI
VINLO
VCM
VRHI
VRLO
AGND
FN3612.10
June 27, 2006
HI7190
Dual-In-Line Plastic Packages (PDIP)
N
E1
INDEX
AREA
1 2 3
N/2
INCHES
-B-
SYMBOL
-AD
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the MO Series Symbol List in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
0.210
5.33
A1
0.015
0.39
A2
0.115
0.195
2.93
4.95
0.014
0.022
0.356
0.558
B1
0.045
0.070
1.55
1.77
0.008
0.014
0.204
0.355
0.980
1.060
24.89
26.9
D1
0.005
0.13
0.300
0.325
7.62
8.25
E1
0.240
0.280
6.10
7.11
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.430
10.92
0.115
0.150
2.93
3.81
20
20
9
Rev. 0 12/93
24
FN3612.10
June 27, 2006
HI7190
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010) M
B M
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
0.014
0.019
0.35
0.49
0.0091
0.0125
0.23
0.32
0.4961
0.5118
12.60
13.00
0.2914
0.2992
7.40
7.60
-B1
L
SEATING PLANE
-A-
h x 45
-C-
A1
C
0.10(0.004)
0.25(0.010) M
C A M
B S
0.050 BSC
1.27 BSC
0.394
0.419
10.00
10.65
0.010
0.029
0.25
0.75
0.016
0.050
0.40
1.27
20
0
20
8
7
8
NOTES:
Rev. 2 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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25
FN3612.10
June 27, 2006