Ov2640 Camera Hardware Guide
Ov2640 Camera Hardware Guide
Ov2640 Camera Hardware Guide
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OmniVision Technologies, Inc. reserves the right to make changes without further notice to
any product herein to improve reliability, function or design. OmniVision does not assume
any liability arising out of the application or use of any project, circuit described herein;
neither does it convey any license under its patent nor the right of others.
This document contains information of a proprietary nature. None of this information shall
be divulged to persons other than OmniVision Technologies, Inc. employee authorized by
the nature of their duties to receive such information, or individuals or organizations
authorized by OmniVision Technologies, Inc.
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Table of Contents
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Company Confidential
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NOTE:
Connector PWDN should be connected to ground if unused.
Sensor reset pin RESETB is active low.
AVDD is 2.8V sensor analog power.
DVDD is 1.3V sensor digital power.
DOVDD is 1.8V to 3.0V sensor digital IO power.
Sensor AGND and DGND should be separated and connect to a
single point at outside PCB (Don't connect inside module).
C2 should close to sensor DVDD and DGND.
C3 should close to sensor SVDD, AVDD and AGND.
C4 should close to sensor VHRFH and AGND.
C5 should close to sensor VREFN and AGND.
C6 should close to sensor DOVDD and DGND.
C1 should close to sensor EVDD and DGND.
D9:D2 is module YUV and RGB 8bits output (D9:MSB, D2:LSB).
D9:D0 is module raw RGB 10 bits output (D9:MSB, D0:LSB
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If DOVDD uses different power supply than AVDD, then 3 regulators should be used.
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If DOVDD uses the same voltage as AVDD, then only 2 regulators are required. R/C filter is used
to separate AVDD from DOVDD.
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Power off mode means that in power saving mode, all the power supplies to the camera module
are cut.
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Step 6:
Pull XCLK low.
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After battery on, OV2640 cameras should be set to power down mode to minimize power
consumption. The cameras should be initialized first, then set to power down mode.
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PWDN
SIO_C
XCLK
Step 1:
Apply XCLK
Step 2:
after 10ms, Pull Low PWDN
Step 3:
Optional Step 4:
Initialization.
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SIO_D
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Step 1:
DOVDD, DVDD and AVDD powers are applied. The 3 powers could be applied simultaneously.
If applied separately, the power on sequence should be DOVDD first, DVDD second and AVDD
last.
Step 2:
after 3ms of last power applied, reset OV2640 camera module by SCCB write.
Step 3:
After 2ms, initialize OV2640 by SCCB initialization. Please find initialization setting from
OV2640 Camera Module Software Application Notes or contact with OmniVision local FAE.
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Step 1.
Pull low XCLK,
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Step 2.
Turn off AVDD, DVDD and DOVDD. The 3 powers could be turned off simultaneously. If
turned off separately, AVDD should be turned off first, DVDD second and DOVDD third.
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Step 3.
Pull Low PWDN and RESET
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The SCCB bus of OV2640 could be shared with other devices in both power down mode and
power off mode. When OV2640 camera module is power down or power off, the SCCB Bus is
leave free. The SCCB of OV2640 doesn't affect the read/write of other SCCB device.
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PCB Delay
PCLK
D[7:0]
PCB Delay
Data
Internal Delay
PLL
PCLK
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PCLK
XCLK
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XCLK
PCB Delay
XCLK
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D[7:0]
Camera Module
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Backend/Baseband
PCLK to Data
Delay
So the delay of video data to clock at backend/baseband side is very critical for timing design. If
the delay is over the spec. of backend/baseband chip, the backend/baseband chip can not get video
data correctly. The incorrect video data may have wrong color, fixed or moving horizontal lines.
Delay_XCLK = 0
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2. XCLK and PCLK should not share ESD/EMI device with other signals. Use dedicate
ESD/EMI device or R/C filters for XCLK and PCLK. So that the delay on XCLK and
PCLK could be adjusted later.
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3. For camera module, use single ESD/EMI device or single R/C filter for XCLK and PCLK to
minimize clock delay.
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4. Carefully layout PCB to keep XCLK wire as short as possible, PCLK wire the same length
as data lines.
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AVDD is supplied by separate regulator. DVDD and DOVDD could be supplied by separate
regulator or shared regulator with other circuits. The voltage of each power supplied are within
sensor specification.
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If there is a long flex cable to connect camera module to main board of phone, please make sure
the ground of camera module is not shared with other circuits. For flip type phone, share camera
ground with LCD module would cause very strong power/ground noise.
PCLK output
D[9:0] output
Check procedures
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f. If SCCB soft reset is used, please wait at least 2~5ms after SCCB soft rest.
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a. Check polarity of HREF(HSYCN), VSYNC, PCLK, make sure the polarity of camera
module matches with backend or baseband side.
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b. Check sample clock. Please pay attention to baseband/backend sample with MCLK. In
this case, the clock divider inside sensor could not be turned on. Please also pay attention to
possible timing issues listed in section 5.
If camera interface uses HREF, then the window position is defined by sensor.
If camera interface uses HSYNC, then the window position is defined by backend /
baseband.
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Sample Rate
too High
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Timing Issue
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Full Screen
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Camera module
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Place an object in front of camera module, check if the picture is on center of LCD. If not, the
output window of camera is not correct.
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