Robust Asynchronous Reset Architecture For Scan Coverage
Robust Asynchronous Reset Architecture For Scan Coverage
Robust Asynchronous Reset Architecture For Scan Coverage
scan coverage
Sandeep JainNikila Krishna, - April 15, 2015
Digital integrated circuits typically use asynchronous set/resets to set the value of memory elements
(flip-flops) without depending on any clock pulses. This logic, however, requires special handling
during scan based testing of the device. Also, the logic associated with asynchronous set/reset may
constitute 2-4% of the total faults in a design. With growing focus on high test-coverage and zero
DPPM, especially for critical applications like automotive and medical devices, it is important to
thoroughly test such faults to ensure overall system robustness.
This article presents various scenarios, and the test architecture to robustly detect scan coverage
including potential race conditions on asynchronous paths.
The salient features of this architecture are:
Mode
Mode-1
Mode-2
Details
ATPG without targetting reset faults
ATPG targetting reset faults
Mode-3
Configuration
TDR_bit=1, RESET=1
TDR_bit=1,
RESET=0(capture)
TDR_bit=0, RESET=X
As the mux is a single library cell, there will not be any glitch inside the mux logic. There should be
no special requirement to use any balanced or glitchless muxes for reset muxing.