Abstract: Ultra-Low Power Phase Locked Loops
Abstract: Ultra-Low Power Phase Locked Loops
Abstract: Ultra-Low Power Phase Locked Loops
INTRODUCTION
PLL ARCHITECTURE
(1)
D. Programmable divider:
The chosen RF application targets the 2.4
GHz ISM band. This requires the VCO and
divider to operate nominally at 4.8 GHz (to
generate I and Q components at 2.4 GHz).
The block diagram of the programmable
divider is shown in Fig. 6.
The synthesizer input frequency comes from
a 5 MHz crystal oscillator. The required
division factor (N) is nominally 480-496, so
the design requires eight divide-by-2/3 cells.
The design uses only True single phase
clocking (TSPC) flops rather than Sourcecoupled logic (SCL) flops. The internal
topological details of the 2/3 cell are shown
in fig. 7 and 8. The combinational logic,
except for an inverter, is absorbed inside the
SIMULATION RESULTS