DDS Assignment 1
DDS Assignment 1
DDS Assignment 1
In between source and destination data may be corrupted due to any type of
noise.
Extra bits that are generated and transferred along with data transfer to
ensure no bits were lost during data transfer.
We add these redundancy bits to the information data at the source end and
remove at destination end.
1. Encrypt information data according to even and odd parity method before
transmission of information at source end.
2. Decryption and Correction(in case of any errors) at the receivers end.
Calculate the
number of number of redundancy bit for 25 bit of input data string by above
formula we get 5 redundancy bit required.
The redundancy bits are placed at the position that corresponds to the power
of 2, i.e., 1, 2, 4, 8 and so on.
TRANSMITTER
The First block with data input represents the input, which we will give to the
encoder.
Next, the Encoder part will add the redundancy bits to the data and give out
the data to PiSo.
The PiSo is responsible for converting the given parallel input to serial output.
RECEIVER
Decoder part receives the parallel data from SiPo, responsible for detecting
error, and correcting the error. The decoder will give out the location of the
erroneous bit, with the actual data without any error and without any
redundancy bits.
In hamming code with even and odd parity check method by using Verilog
HDL, we transmit 25 bit information data with 5 redundancy bits from source
and receive this data at destination.
This received data may be corrupted due to noise. To remove this noise we
find the address of error bit then correct them.
For finding the location of error bit and correct them we use again even parity
check method and/or odd parity check method .
We have also written code for decrypting this 30 bit encrypted data into 25
bit information data.
Now we can use only one circuit for correction error bit and finding the actual
information data.
Procedure:
??0?100?1101
P1= ? 0 1 0 1 0 = 0
P2= ? 0 0 0 1 0 = 1
P3= ? 1 0 0 1
=0
P4= ? 1 1 0 1
=0
P1= ? 0 1 0 1 0 = 0
P2= ? 0 0 0 1 0 = 1
P3= ? 1 0 0 1
=0
P4= ? 1 1 0 1
=1
P1= 0 0 1 0 1 1
P2= 1 0 0 0 1 1
P4= 0 1 0 0 1
(correct)
P8= 1 1 1 1 1
Parity bits 1 , 2 and 8 are not correct. So to find erroneous bit position we add
1+2+8 = 11.
We have used Xilinx ISE 10.1 Simulator for simulating and synthesized
Verilog HDL Code.
Xilinx ISE 10.1 Simulator is a simulator which is used for simulating HDL
language and schematic circuit diagram.