EDN Design Ideas 1999
EDN Design Ideas 1999
EDN Design Ideas 1999
ideas
1
5
XTAL1
AT89C2051
RST
RxD
P1.7
TxD
XTI
PCM1710
26
27
IC1B
P3.2 6
P1.0 TO 6
LRCIN
28
MD
MC
ML
22k
5V
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2 mSEC/DIV
(b)
A simple mC-based circuit (a) continuously reprograms the PCM1710 audio DAC for a resolution of
20 bits. The mC sends 1 byte of code after each RST pulse (b).
January 7, 1999 | edn 107
design
ideas
web site, www.ednmag.com. At the registered-user area, go into the Software Center to download the file from DI-SIG,
#2312.) After each RST pulse, the mC sends
1 byte of code; the mC sends the same byte
every third RST pulse. The circuit uses register RO to temporarily save the value of the
next word to send because the mC reset
does not affect this register. The circuit also
uses one bit-addressable memory location,
designated FLAG (20H), to switch between
design
ideas
clockwise or counterclockwise.
venient and sometimes impossiP1 (1k)
You record these data for future
ble, such as when the trimmer is
MULTITURN
reference.
mounted on a panel, for example.
WIRE-WOUND
POTENTIOMETER
If you wish to restore the potenThe simple tool in Figure 1 comes
tiometers original position, you
in handy in such situations.
Figure 1
adjust P1 to the recorded value with
You construct the tool by
the
same position of S1 by turning
mechanically coupling the trimCW
the trim tool in the opposite direcming tools shaft to the shaft of a
MECHANICAL
S1
tion until the DMM reads zero rehigh-quality, multiturn, wireCOUPLING
sistance. This position is the origiwound potentiometer (P1). The
wiper and one of the end terminal setting of the potentiometer.
CCW
nals of this potentiometer connect
The resistance value of P1 is not
TRIM TOOL
DMM
critical. However, its better to seto a DMM operating in resistancelect low values to obtain higher resmeasurement mode. The toggle
(IN RESISTANCETIP FOR
MEASUREMENT MODE)
olution on the DMM. Also, a sinswitch, S1, selects one of the two
TURNING
TRIMMER
available end terminals. Before
gle range of the DMM should
SCREW
disturbing the setting of a multicover the value. This prototype
turn potentiometer in a circuit, This tool with a memory allows you to accurately restore the
uses 1 kV. You can improve the
you rotate the trim tool to the original setting of a multiturn potentiometer.
tool by replacing P1 with a miniature bidirectional optical shaft enendpoint of P1s rotation span in
the opposite direction to that in which you firmly holding P1 with one hand and turn coder and connecting its output to an
intend to adjust the trimming poten- the trimming potentiometer to the desired up/down counter. (DI #2308)
tiometer. Set the selector switch such that setting. The corresponding P1 resistance
the DMM reads zero (or near-zero) resis- value on the DMM, along with S1s posiTo Vote For This Design,
tance. Then, you rotate the trim tool by tion, tells you whether the tool rotates
Circle No. 428
Figure 1
R2
1M
IC1A
4069
IC1B
2
IC1C
4
IC1D
6
1N4148
C3
1 mF
1M
R3
1M
D2
1N4148
C1
IC1E
INPUT
C2
0.1 mF
R1
5M
D1
1N4148
1 nF
11
IC1F
10
13
12
RESET HIGH
RESET LOW
A charge pump comprising D1, D2, C1, and C2 inhibits a three-gate oscillator when input activity exists. After 40 msec without input activity, the oscillator starts running and produces a reset signal.
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ideas
square wave. The high time of the resethigh output resets the mP under control,
which must start the activity (and activate
the watchdog input) before the end of the
low time. R3 and C3 essentially control the
high and low times, which have almost the
same value.
Although this design monitors an RS232C line, you can use the circuit to monitor a digital level. When monitoring an RS-
240V, 50 OR 60 Hz
Figure 1
LOAD
1 TO 3 kW
FAN
REGULATOR
LAMP
10 TO 25W
NEUTRAL
SCR2
R1
PULSE
TRANSFORMER
100
1W
SCR1
D1
1N4007
R2
100
1W
D2
1N4007
A couple of thyristors, a pulse transformer, and two diodes transform a humble 100W fan regulator into a high-power ac controller.
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LAB SET
Figure 1
DIP HEADER
4.7M
11002
15V
0.1
132
30.1k
500
15V
0.1
20k
7
1
10k
TEMP
10k
2TEMP
2
+
8
IC1
OP-O7
VIRTUAL
GROUND
1k
4
1
2 IC2A
2
LM324AN
30.1k
100k
0.1
0
470k
13
2
14
IC2B
12 +
11
22k
500
1N4148A
0.1
0.1
215V
15V
215V
1k
100
15V
RED
+
6 5V
REF-O2A
SETIC3
POINT
4 10k
6
5
2
IC2C
+
1k
20k
Q1
2N3904
2
IC2D
10
+
"TOO-COLD"
THRESHOLD
0.1
50k
SETPOINT
MONITOR
10
25V
47k
100
215V
+
BLACK
YELLOW
10
25V
1N4148A
1 nF
4.7M
10k
215V
NOTE:
ALL CAPACITORS ARE IN MICROFARADS UNLESS OTHERWISE SPECIFIED.
A four-wire silicon diode helps to maintain an IR cameras temperature at approximately 88K. One pair of #38 AWG wires forward-biases the diode
with a fixed 10 mA of drive current. A second pair of wires provides for a Kelvin-connection measurement of the diodes forward voltage drop, which
is a nonlinear function of temperature.
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116 edn | January 7, 1999
design
ideas
ence. In addition to a low-offset error amplifier, this IC also contains an optocoupler driver for simplicity in designing isolated converters. An undervoltage-lockout
circuit provides a controlled start-up transient. The design in Figure 1 uses discontinuous-conduction mode (in which the
flyback transformer undergoes complete
demagnetization in every cycle), with
maximum duty cycle set to 50%. Continuous-mode flyback circuits (in which the
flyback transformer operates in continuous inductor-current mode) have a righthalf-plane zero that limits the control
bandwidth, as opposed to discontinuousmode flybacks that do not restrict bandwidth.
Both ICs operate in either mode; the
Figure 1
PC30EI19
choice of mode depends on the powersupply requirements. You can easily buffer
the primary-side oscillator with an emitter follower to provide slope compensation for designs requiring duty cycles beyond 50%. Note, however, that you have
the option of programming a duty-cycle
clamp to 50% or less, which can save cost
by eliminating several slope-compensation components. The maximum-dutycycle clamp in the UCC3809 is completely programmable by selecting the two
resistors connected to pins 3 and 4. (DI
#2288)
MBR1635
+
7:1
+
+
48V
1 mF
120 mF
100V
1 mF
1.74k
2200 mF
6.3V
15 mV
5V
1
98 mH
PRIMARY
IRF630
15V
1N4148
0.0022 mF 150k
22.6k
1 mF
10
UC3965
1
8
0.1 mF
0.2
UCC3809
100 pF
4.02k
3
220 pF
22.6k
0.1 mF
4
750
0.022 mF
EACH
7.15k
4.02k
14.3k
1000 pF
2N2222A
5
1.43k
1 nF
1k
MOC8102
2
1
A discontinuous-mode flyback regulator provides an isolated, regulated supply, and saves cost by cutting compensation components.
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Edited by Bill Travis and Anne Watson Swager
ideas
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ideas
W0 + W1 s + W2 s 2 U 0 + U 1 z11 + U 2 z12 .
H(s) =
H(z) =
C 0 + C 1z
11
1
M=
B 0 + B 1s + B 2 s 2
, and
+ C 2z
12
D 0 + D1z11 + D 2 z12
[U 0 U 1U 2 ] T = M [W0 W1 W2 ] T , and
[W 0 W1 W2 ] T = M11 [U 0 U1 U 2 ] T,
(1)
(2)
where
M =
1
1
2 M 1 = 1
1 ,
1
0
1
1
M 1 =
.
These equations assume that the prototype filter is normalized with respect to
the sampling frequency, fS. For example,
design a second-order Butterworth unity-gain, lowpass IIR filter with cutoff frequency, fC,=100 Hz, and sampling rate,
fS=1000 Hz. First, you use CW to frequency-scale the Butterworth prototype
(in normalized form, CW =1). The expression for CW is
CW
f f
= 2 tan C C =
fS fS
0.4223
0. 4223+ 0. 919s + s 2
1 0.4223 0.1056
0.25 0.5
0.5
0
2 0 = 0.2112 ;
1 0.4223 1.5651
D0 0.25 0.5
= 0.5
0
2 0.9190 = 1.7889 .
D
1
D2 0.25 0.5 1 1.0000 0.6461
design
ideas
neously; otherwise, a net voltage imbalance would appear at the input of Q1 and
Q2, resulting in alarm activation. Momentarily opening S3 resets Q4 by interrupting its anode current. C2 provides a
small time delay to allow the voltage at
the input of Q1 and Q2 to stabilize before
enabling Q3. C1, C3, and C4 prevent stray
ac pickup or transients from triggering
Q4. (DI #2286).
To Vote For This Design,
Circle No. 387
Figure 1
Normally closed sensor pairs form the detectors in a tamper-resistant and foolproof window/door security system.
most accurate way to give the information, but it requires time and expertise.
The following hint provides a quick way
to determine, using a DSO, how often
each of two waveforms occurs.
First, use a standard nonaveraging
mode to find the voltages of the two states
at a fixed point in time (V1 and V2). Now,
turn averaging on using a large number
of averages. After the trace settles, measure the average level(VA). The percentage of time the signal at V2 is:
VA1V1
100%.
V21V1
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transformer coupling is virtually universal, despite the problems inherent in inductively coupled circuits. These problems include relatively high interwinding
stray capacitance and a tendency to couple switching noise into the signal. In
contrast, the self-powered amplifier in
Figure 1 is different in that it incorporates optoisolators to effect communication of both signal and power around the
isolation barrier.
As in many isolation-amplifier designs,
the signal processing in Figure 1s circuit
uses PWM. The isolated-modulator
front-end circuitry derives from an earli-
Figure 1
5V
~20 mA
200
2
~20 mA
8
+
*1M
OI1
22
mF
PVI5100
*1M
1 nF
*1M
3
IC3
1
*1M
+
20M
20M
1 mSEC
27k
2.6
R3
5.1M
0.0047 mF
10
1
11 +
C2
0.0047 mF
C1
R1
10M
VIN
51V
1
7 +
8
C3
10 pF
0.6
IC4
20M 1.2V
V1
12
IC1
R4
13
OI2
100
VOUT
1M*
C5
0.022 mF
13
14
2
3
200
7 6
1
+ IC
5
3 4
240k
240k
0.022 mF
15V
12
15
1
LMC7101
2
S2
10
ZERO
5V
11
52.5V
2
S1
1M*
3k
V2
200k
2
200k
15
100 pF
C4
S3 0.022 mF
LT1009
14
IC2
1
+
10M
THERMALLY
MATCH
10M
R2
3
9
16
5V
IN4148
HCPL-2231
1M*
NOTES: IC1 TO IC4=1/4 LT1443.
S1 TO S3=1/3 HC4053.
*1% METAL FILM.
ISOLATED PWM MODULATOR
A virtual perpetual-motion machine (when theres light), this self-powered amplifier provides complete galvanic isolation for both power and signal.
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Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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lators provide galvanic isolation and generate the RxD received signals with RS232C logic levels. The circuit provides
galvanically isolated communication in
full-duplex mode at any standard transmission speed. The use of galvanic isolation allows transmission over nearly
twice the distance for nonisolated systems. If you use a four-wire cable and
split the separation circuits at the cable
ends, you can further increase the transmission distance. (DI #2315).
To Vote For This Design,
Circle No. 333
RxD1
IC1
TLP2200
Figure 1
IC2
MAX860
D1
1N581
1
2
3
2.2 mF
FC
VDD
C1
SHDN
D2
5.6V
GND
LV 6
4 C11
OUT
4.7 mF
VDD
A
6 1EN
D3
4.7 mF
GND2
5 VSS
5.6V
2.2k
D4
TxD1
OUT
1N581
D5
1N414
22k
IC3
TLP2200
2.2k
2
A
GND1
R1
VDD
OUT
D6
1EN
5.6V
VSS
C4
4.7 mF
D7
IC4
MAX860
8
VDD
FC
SHDN
C1
1N581
1
C5
4.7 mF
6 LV
GND
5 OUT
C11 4
D8
5.6V
TxD2
2
3
2.2 mF
D9
R2
22k
D10
1N581
1N414
RxD2
RS-232C-interface ICs and optoisolators provide a supplyless RS-232C transmission link with galvanic isolation for increased distance.
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X1
D0
X2
D1
RESET
Figure 1
EA/VP
serial interface, so it uses the negativevoltage generator in the MAX232 RS232C/TTL converter. Listing 1 is the subroutine for the 8051 mC. The program
VCC
1
D2
D3
D4
D5
IC1
8051
D6
VCC
INC
U/D
IC2
X9103
CS
VH
VL
VSS
VW
LCD
8
7
6
GND VCC
1
VO
RS
RW
5
E
6
DO
7
D1
8
D2
9
D3
10
D4
11
D5 D6 D7
12
13
14
D7
RS
VCC
RW
E
R1
10k
VCC
C2
10 mF
16
1
3
4
10 mF
C3
5
11
10
12
9
C1+
VCC
C12
V+ 2
V2 6
C2+
C22
T1I
IC3
MAX232
T1O
T2I
T2O
R1O
R1I
R2O
R2I
GND
C4
10 mF
C5
10 mF
14
7
13
8
15
A standard 8051 mC and a digitally controlled potentiometer provide a convenient way to vary the contrast of an LCD, using contrast-up and -down
buttons.
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high-voltage capability. If
12V is unavailable, you can
use charge-pump circuitry
to double the input voltage.
The driver shows excellent
performance, with 60-nsec
nonoverlap time, superior to
that of many available ICs.
Figure 3 shows the two gate
drivers outputs, with each
driver switching an IRL3103
n-channel MOSFET, a good
choice for a 10A converter.
The total cost of the driver
does not exceed 30 cents. (DI
#2306).
To Vote For This Design,
Circle No. 336
5 V(A)
D
5 V(A)
Q1
2N5458
G
R2
R4
R5
300k
7.5k
1k
S
R1
20k
LF398
AGND
2
74HC4066
1
PULSES
13
IC1A
R3
51k
C
C1
0.1 mF
C2
0.1 mF
IC2
NUL
IN
6 C OUT 5
8
L
7
LR
S/H_OUT
74HC4066
11
12
A
C
IC1B
B 10
5 V(D)
AGND
AGND
R6
100k
DGND
C3
0.01 mF
R8
4.3k
R7
5.6k
DGND
SAMPLE
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ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
Fax
Company
Address
Country
Design Idea Title
ZIP
Signed
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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Decimal
235
469
939
1877
3755
Binary
(maximum)
11101011
111010101
1110101011
11101010101
111010101011
Hex
00EB
01D5
03AB
0755
0EAB
G 22 = ( (Di (1 + 2 41i ) i =1
N -1
i =2
j=i +1
(Di (1 - 41i )
Its obvious that G11 has a constant value, the reciprocal of the base resistance,
R. G12 is a linear function of the input
code and base resistance R. The expression for G22, however, reveals complex,
nonlinear behavior as a function of the
digital input code. A Thevenin transform
in Figure 2s circuit produces the simplified equivalent circuit in Figure 3. The
output resistance, RO, in the most common case, when the MDAC connects to
G11 = 1/ R,
G12 =
VOFF
2.652*VOS
2.763*VOS
2.875*VOS
2.986*VOS
3.097*VOS
(Di - 21i )/ R,
i =1
Figure 1
REF
RFB
VREF
2R
2R
2R
2R
2R
SW1
SW2
SW(N21)
SW(N)
1
A
IOUT
RIN
1
+
IOUT
+
D1 (MSB)
D2
D(N21)
D(N) (LSB)
VOUT
VOS
The output impedance of a multiplying R-2R DAC is a complex, nonlinear function (third equation in the text) of the digital input code.
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design
ideas
VOFF = VOS (1 + R G 22 ).
References
RFB
RFB=R
IOUT
2
+
VOFF
VOS
RO
IOUT
+
2
A Thevenin transformation of the equivalent circuit in Figure 2 produces a greatly simplified circuit.
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ideas
Figure 3
7.5
MAX1683
7
6.5
1.9
6
ROUT (V)
1.8
5.5
MAX660
1.7
LOAD=50 mA
LOAD=5 mA
5
1.6
4.5
1.4
1.3
3.5
1.2
LOAD=150 mA
1.1
3
3
(a)
10
(b)
6
7
8
INPUT VOLTAGE (V)
10
Over the usable 3.6 to 10V input-voltage range, the small MAX1683 (a) exhibits higher output resistance than the more robust MAX660 (b).
1
MAX1683
Figure 4
0.98
1
MAX660
LOAD=5 mA
0.96
0.98
LOAD=50 mA
0.94
0.96
EFFICIENCY (%) 0.92
0.94
EFFICIENCY (%)
0.9
LOAD=150 mA
0.92
0.88
LOAD=50 mA
0.9
0.86
0.88
0.84
3
3
(a)
10
6
7
8
INPUT VOLTAGE (V)
10
(b)
Both the MAX1683 (a) and the MAX660 (b) offer better than 90% efficiency over a large portion of their usable operating range.
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ideas
R OUT =
1
+ 4(R 4 + R 2 R 1 R 3 ) + 2R ESR ,
f OSC C1
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ideas
1.25[1+(R3/R4)], with appropriate
changes to the value of R2, using the formula R2=(VIN(MIN)20.7V)/10 mA. Small
components allow the entire circuit to
occupy less than 0.24 in.2 of board area.
Y
0
1
0
1
XOR
0
1
1
0
mentation, the data shifts the most significant bit first, one data byte at a time.
Two temporary registers buffer the
data to prevent the shifting from corrupting the data. The shift register comprises two separate 8-bit registers,
CRC16_HI and CRC16_LO. The most
significant bit of CRC16_HI is the location of Stage 16 (Figure 1). From the figure and Table 1, you can see that the result of XORing the input data bit and the
contents of Stage 16 of the shift register
determines the effect that new data has
on the shift register. If the result is a one,
then you must complement the contents
of stages 2 and 15 before rotating the new
data into the shift register. If the result is
a zero, then the new data can rotate immediately into the shift register. Some
housekeeping tips can be helpful here.
The data transmitter should generate its
CRC-16 in the same manner as the data
receiver. Also, its advisable to clean the
CRC-16 shift register before rotating the
first data bit of the data string into it.
Figure 1
(a) POLYNOMIAL REPRESENTATION OF CRC-16: X16+X15+X2+1
(b) HARDWARE REPRESENTATION OF CRC-16
STAGE
1
X0
STAGE
2
STAGE
3
X1
STAGE
9
X2
STAGE
10
X9
STAGE
11
X10
X11
STAGE
12
X12
STAGE
4
STAGE
5
STAGE
6
X3
X4
X5
STAGE
13
STAGE
14
STAGE
15
X13
X14
STAGE
7
X6
STAGE
8
X7
X8
STAGE
16
X15
X16
You can represent the CRC-16 algorithm as both a polynomial (a) and a hardware-based shift register (b).
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ideas
How does the CRC-16 identify data errors? The simplest method is to attach the
shift register to the end of the data string.
In this implementation, the CRC16_HI
register should follow the last byte of data
sent. The CRC16_LO register follows the
CRC16_HI register. If the receiving system computes a CRC-16 value from all
the data bytes and the attached shift register (CRC16_HI and CRC16_LO), then
the resulting CRC-16 code is 0000h. Any
nonzero result indicates an error in the
data. In some systems, an error may occur that results in all zeros being sent as
the data and attached CRC-16. This type
of error poses as error-free data. In these
systems, you can overcome the false indication by complementing the CRC-16
before attaching it to the data string. The
CRC-16 shift register generated by attaching the complement is always 800Dh.
The code fragment in Listing 1 generates a CRC-16 shift register on a byte-bybyte basis. You could embed this code
within serial-receive and serial-send routines to provide a powerful error-detection tool. You can easily generate the
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Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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R2 22k
PIC16C63
DS1820
2
D1
Q3
R3 22k
OUTPUT
PSOTO5LC
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A simple three-transistor circuit provide both latch-up protection and signal conditioning in this
mC interface.
one-wire sensor/m
March 4, 1999 | edn 107
design
ideas
VCC
16
R2
2 RxCx(1)
14
VDD
1TR1
RxCx(2)
Q1
Cx(1)
Q1
5
7
OUT1
C2
1
3
13
4
IN
11
R1
OUT1
4098
R2
Q2
+TR1
Q2
1TR2
+TR2
9
10
OUT2
OUT2
12
VSS
8
0V
A dual monostable multivibrator provides a convenient means of detecting a signals rising and
falling edges.
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design
ideas
Figure 2
R1
10M
C1
100k
100k
R6
+
100 pF
R4
10M
9V
C2
220 nF
100k
2.87M
IC1
10M
10M
IN+
R2
IN1
R3
ICL7611
1
3 +
SENSORCLAMP
INPUTS
5
Q2
BC857C
6
4
8
Q1
BC847C
61
8
7
VOUT
4 IC2
TLC393
R8
511k
1N4004
100k
R5 100 nF
R7
100k
C3
1 mF
R9
5.11M
A CMOS integrator and comparator condition the signal from Figure 1s sensor for interpretation by a DMM or an oscilloscope.
www.ednmag.com
design
ideas
to a -51 mC.
Listing 1 is available for downloading
from EDNs Web site, www.ednmag.com.
At the registered-user area, go into the
Software Center to download the file
from DI-SIG, #2329. (DI #2329).
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design
ideas
5V
5V
IC1
CA339
R8
18k
R7
10k
5V
5V
IC2A
CD4082
5V
Q6
10
CK
Q7
R3
180
IC5
ICM7555
C1
0.01 mF
IC2B
CD4082
R10
10k
Q4
SDP8406
IC4A
CD4093
C4
1 mF
8
R11
10k
SMALL
BOX
Q3
2N3904
R5
100k
C3
0.1 mF
C5
0.01 mF
R9
620k
R6
5.1k
R4
100k
5V
5V
Figure 1
Q1
SEP8706
6
IC4B
CD4093
IC3
CD4020
Q8
3
1
R1
C2 18k
0.01 mF
R2
4.3k
Q2
2N3906
LARGE
BOX
13
11
IC4C
CD4093
C6
1000 pF
RESET
R12
10k
5V
An oscillator circuit allows a photodetector to both count and sort objects according to size.
www.ednmag.com
design
ideas
Figure 1
LONG
CODE
ENTER
PULSEWIDTH
SEPARATOR
DEBOUNCE
SHORT
LONG/
SHORT
SELECT
CLOCK
LONG/SHORT
ADDRESS
ENTRY
WINDOW, T1
(8 SEC)
CLOCK
R-1
DECODER
COUNTER
FIRST
TRIGGER
RESET
R-1
R-2
TRIGGER
LOCKOUT, T2
(10 SEC MINIMUM)
TRIGGER
TRIGGER
CODEENTRY
WINDOW
TIMER
(T1)
1
2
3
4
DECODED
COUNTER
RESET
R-2
UNLOCK
COMMAND
10
SEC
OR
GATE
5
6
7
8
COMBINATION
SET
(SEE TEXT)
RETRIGGERLOCKOUT
TIMER
(T2)
A handful of timers and counters configures a highly secure, single-button combination lock.
www.ednmag.com
design
ideas
quence would also be secure; you can implement a shorter code by simply
Figure 3
taking the unlock pulse from a
lower count on IC6. IC6s output returns
low after 10 sec when T2 resets. If desired,
you can generate a lock command, which
need not be secure, by adding the simple
circuit in Figure 3. (DI #2327).
1/4 CD4093
+
~600 mSEC
1M
"SHORT" PULSES
FROM IC1, PIN 10
R2
24k
14
1 mF
~7 mSEC
LOCK
COMMAND
You can generate a lock command with this additional circuit by rapidly entering four or more
short pulses.
IC1
CD4093
Figure 2
"LONG"
(>0.3 SEC)
+
A
240k
14
12
2
1 mF
NO
0.082 mF
5
6
CODEENTRY
BUTTON
22k
43Ok
100k
"SHORT"
10 (<0.3 SEC)
14
D
0
9
14
UNLOCK
COMMAND
8
15
100k
16
0
13
100k
IC6
CD4011
16
13
100k
IC5
CD4019
11
13
15
~7 mSEC
1 mF
+
LONG/SHORT
ADDRESS
LINES
10 mF +
20V
TANTALUM
POWER
(5 TO 15V)
20-mSEC CLOCK
DELAY
1000 pF
22k
TRIGGER
DUAL TIMER
(T1 AND T2)
COMBINATION SET
(LLSSLSSL SHOWN)
+
0
22k
3
12
10
11
10M
8.2M
13
16
2
1 mF
220k
7
8
16
2
4
7
IC3
CD4017 10
1
5
15
R-1
6
9
8
13
IC2
CD4538 5
14
1 mF
+
14
15
1M
2
3
5
6
7
8
14
9
10
11 B
3 A
4
12
22 mF
20V
TANTALUM
13
POWER-ON
RESET
IC4
CD4072
R-2
NOTE: ALL DIODES=1N4148.
You program your combination by hard-wiring the IC3-IC4 output-to-input connections, LLSSLSSL, where L and S are long and short inputs, respectively, in this example.
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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ideas
VREF / 255
5/255
= 3.0001
= 2.990V.
2
design
ideas
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design
ideas
VOUTB = I2 R F +
(R + R F )
RF
+ VOSB S
1VOSA
.
R
RS
S
VOUTA = I1 R F +
(R + R F )
RF
+ VOSA S
1VOSB
.
R
RS
S
Figure 2
Figure 1
VOUTB=I1 RF+VOSB
VOSB
V+
VOUTB=I2RF+[1VOSA(RF/RS)+VOSB((RS+RF)/RS)]
VOUTB
VOUTB
VOSB
100k
V1
RF
PSD
V+
RF
PSD
I2
_
I2
V1
V1
RS
+
RF
I1
V+
RS
V+
RF
I1
100k
A
_
A
+
VOUTA
VOSA
_
VOUTA
VOUTA=I1 RF+VOSB+VOSC
V+
VOUTA=I1RF+[1VOSB(RF/RS)+VOSA((RS+RF)/RS)]
VOSA
_
V+
design
ideas
5V
Figure 1
0.1
mF
0.1
mF
COP8SGR728M8
mC
5V
1 mF
0.1
mF
SPEAKER
4V
RIGHT SPEAKER
LM4835
BOOMER AMPLIFIER
+
1
SHUTDOWN
GAIN SELECT
MODE
MUTE
DC VOL
RIGHT DOC
RIGHT IN
BEEP IN
LEFT IN
LEFT DOC
VCC
5V
1k
10
mF
PB1
20k
+
U5 RIGHT IN
GND
PB2
0.33
mF
20k
RIGHT OUT
RIGHT OUT
RIGHT GAIN2
RIGHT GAIN1
BYPASS
HP SENSE
LEFT GAIN1
LEFT GAIN2
LEFT OUT+
LEFT OUT1
20k
0.068
mF
20k
1 mF
20k
20k
SPEAKER
4V
20k
20k
+
LEFT IN
U6
20k
200k
220 mF +
0.068
mF
R13
20k
1
LEFT
SPEAKER
220
mF
0.33 mF
5V
HP+
3
1k
HEADPHONE SWITCH
SW1
1k
HP1
HEADPHONE
OUTPUT
Instead of tweaking potentiometers, you can use pushbuttons and a mC to control Nationals Boomer amplifier IC.
www.ednmag.com
design
ideas
V
10 VF + VR
10
,
= REF >
N VF1VR VPIN5 N +1
9V
100k
Figure 1
9
VF INPUT
100k
2 _
8
10
1
100k
+
IC1C
3 +
100k
VF-VR
10k
IC1A
11 OP491
10 mF
100k
SWR
11
1 LO
2
1V
3
+V
4 R
200k
13
VR INPUT
_
14
12
18
17
16
15
LO
100k
IC1D
14
5 SIG
IC2
LM3914 13
6 R
6 _
7
100k
HI
100k
7
IC1B
100k
820
8
9
100k
REF
ADJ
MODE
K
13 K
14
K
15
K
16
K
LED1
17
K
12
18
11
19
HI 10
12
A
A
A
A
A
A
A
20 K
10
9
8
7
6
5
4
3
2
1
6.4-TO-1
3.9-TO-1
2.7-TO-1
2.2-TO-1
1.8-TO-1
1.5-TO-1
1.3-TO-1
1.2-TO-1
1.1-TO-1
1-TO-1
NOTE: 50 mV<VF+VR<7.5V.
You can use an LED-driver IC to produce a thermometer-type indicator for the standing-wave ratio in RF systems.
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ideas
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
Fax
Company
Address
Country
Design Idea Title
ZIP
Signed
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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ideas
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ideas
Figure 2
F
D
B
G
E
C
G
E
C
A
F
D
DO
RE
MI
FA
SOL
LA
TI
DO1
RE1
MI1
FA1
SOL1
f, Hz
264
297
330
352
396
440
495
528
594
660
704
792
T, mSEC
3.78
3.36
3.04
2.84
2.51
2.3
2.0
1.9
1.68
1.5
1.4
1.26
1/2T, mSEC
1.89
1.68
1.52
1.42
1.26
1.14
1.01
0.94
0.84
0.76
0.71
0.63
NUMBER TO
PUT INTO NR
189
168
152
142
126
114
101
94
84
76
71
63
NOTE
(a)
NOTE SHAPE
DURATION
PUT INTO DR
WHOLE
HALF
QUARTER
EIGHTH
16TH
16
(b)
A musical passage consists of pitches (a) and durations of the notes (b); you enter these values into the mCs pitch and duration registers.
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design
ideas
the registered-user area, go into the Software Center to download the files from
DI-SIG, #2336. (DI #2336).
indicator allows you to devote full attention to making the connection without
having to observe an LED. The circuit
also consumes less power than Dijkstras
design
ideas
S1
Figure 1
3V
R2
3.3k
R4
56k
+
221.5V
1
RX
R1
100
F
3
IC1
OP150
1
4
R5
100k
R6
10k
G
Q1
2N3904
PANASONIC
P9912 OR
PROJECTS UNLIMITED
AT-138
R3
220
R7
1.5k
NOTES:
RX=LESS THAN 12V=BUZZ.
IC1=AD 0P150, MAXIM MAX495, BURR-BROWN OPA340,
NATIONAL LMC272 (1/2 OF DUAL), TI TLC272C (1/2 OF DUAL),
TI TLV2221 (SEE DATA SHEET FOR PINOUT), PHILIPS NE5230.
This audible-signal continuity tester consumes little power and allows you to detect opens and shorts without observing an LED.
service as an spst switch. A simple wireless transceiver illustrates how you can
use stereo jacks for switching with
monaural plugs, stereo plugs, or both
(Figures 1 and 2). Using the design in
Figure 1, you can connect the battery return to the ring of stereo jacks serving
one or more I/O devices. The circuit in
Figure 2 connects the returns of individual circuits to the ring.
With this scheme, power control be-
design
ideas
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design
ideas
Figure 2
At a 100k-sample/sec sampling rate, the circuit in Figure 1 provides excellent hold accuracy.
Figure 3
The S/H circuit in Figure 1 exhibits low ringing and overshoot characteristics when sampling at 400k samples/sec.
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design
ideas
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fIN
18
Input fIN, which connects to the ACK pin of LPT1, produces an IRQ7 hardware interrupt on every
rising edge. The software counts the number of rising edges that occur during the timebase, T,
which IRQ0 helps to generate.
interrupt-based, which allows for resident operation in an MS-DOS environment and for multitasking mode under
Windows. For a timebase of 1 sec and using a 100-MHz Pentium PC, the frequency meter gives good results in the
range of 10 Hz to 10 kHz with errors less
than 0.26% for DOS and 0.94% for Windows (Figure 3). This design uses a Tektronix (www.tek.com) CFG280 function
generator for reference. A faster PC
should produce even better results.
Listing 1 is written in Borland C++
compiler, and you can use the same proApril 29, 1999 | edn 89
design
ideas
WINDOWS 95
MS-DOS
20
0
10
2000
4000
6000
FREQUENCY (Hz)
8000
10,000
12,000
For a timebase of 1 sec and using a 100-MHz Pentium PC, the frequency meter gives good results that
range from 10 Hz to 10 kHz with errors less than 0.26% for DOS and 0.94% for Windows.
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design
ideas
IDISCHARGE =
510
3.3M
RD
R3
C1
10 nF
LED
7
V+
R1
3.3M
+
3 IN+
4 IN1
OUT 8
6V R2
1M
Q1
5 HYST
IC1
MAX921
6 REF
V1
GND
2
VBATTERY
RD
A NiCd or nickel-metal-hydride
(NiMH) battery has a nominal cell voltage of approximately 1.2V at midcharge
and approximately 1V at end of charge.
Do not discharge past the end-of-charge
voltage, because you may damage the
battery. The values in Figure 1a are for a
four-cell battery. R1 and R2 determine the
end-of-voltage limit referenced to the
built-in 1.182V bandgap reference.
When battery voltage is high, comparator IC1 turns on Q1, a power n-channel
MOSFET, which discharges the battery
through RD.
When the battery reaches the end-ofcharge voltage, the circuits behavior gets
interesting. R3 and C1 provide positive ac
feedback to ensure that the comparator
fully switches and prevents the circuit
from becoming a linear regulator. However, the intrinsic internal resistance of
the battery also causes negative dc feedback. As the MOSFET turns off the battery terminal voltage, the comparator
turns the MOSFET back on. The positive
ac feedback overwhelms the negative
feedback, thus ensuring switching, but
only for a short time, and the circuit oscillates. The frequency is roughly
PATTY 09d2348a
GND
(b)
When the battery reaches the end of charge, this deep-discharge circuit (a) oscillates until the battery voltage stays below the hysteresis threshold (b).
f=
1
.
2 p (R 3 + R1 R 2 ) C1
design
ideas
X1Y(n)K
KY(n)K11
FOR n = 0, 1, 2, 3K AND
K = 2, 3, 4, 5K
This recursion monotonically converges toward the Kth root of the num-
TABLE 1CUBE-ROOT
MAXIMUM ERRORS
X
0.001
0.01
0.1
10
100
1000
% Error
0.001
0.0005
0.0002
0.00005
0.00002
0.00001
X
0.001
0.01
0.1
10
100
1000
Number
of iterations
1998 Design Idea
10
12
14
19
23
22
Number
this
Design Idea
10
Eight
Six
Seven
11
14
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design
ideas
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ideas
VIN
Figure 1
VIN
PHASE 2
PHASE 1
1
3
2
COUT
COUT
VOUT
(a)
VOUT
(b)
Adding a few diodes to a switched-capacitor inverter doubles the current from input to output.
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award for
the winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
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ZIP
design
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Figure 2
Switching regulator drives
robot motor . . . . . . . . . . . . . . . . . . . . . . . .99
Simple fix adds door-chime
repeater . . . . . . . . . . . . . . . . . . . . . . . . . . .100
OBJECT
LAMPS
PHOTODETECTOR
MOTOR
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R2D2 has lamps in his eyes to provide a light source and a photodetector in his nose to detect light
reflected from an oncoming object.
May 13, 1999 | edn 99
design
ideas
1+R2/R3, amplifies this voltage. The amplified voltage is a control voltage, VC,
which routes to the ISRs Adjust pin via
R1. A decrease in VC, relating to a decrease
in light level, causes the ISRs output voltage and the corresponding speed of the
dc motor to increase. An increase in VC,
relating to an increase in light level, causes VOUT and the corresponding motor
speed to decrease. A further increase in
light level causes VC to increase to a point
Figure 1
astable multivibrator. The timing components, R1, R2, R3, and C3, provide the required pulse widths.
The maximum duty cycle of a typical
chime is 25%. The energized time is
0.76(R3+R4)C3, which you can adjust
from 7.6 msec to 0.4 sec. The de-energized time is 0.693(R1+R2)C3, which you
can adjust from 0.3 to 1 sec. IC2 drives the
12V relay, K1, via resistor R5 and transistor Q1. D5 is a flyback diode that protects
K1. You must select K1 to fit the specific
chime. The coil current can be as high as
200 mA. The circuit normally uses closed
BR1
4-1N4001
D3
1N4001
IN
D1
1N4001
D2
1N4001
LM7812C
2
IC1 OUT
GND
3
C1
0.1 mF
C2
0.1 mF
R1
470k
R2
1M
K1
FRONT
NC1
16V
AC
VCC
IC2
LM555
7
DISCHARGE
2
TRIGGER
FRONT
CHIME
NO1
REAR
1N4148
RESET
COM1
NC2
3
THRESHOLD
OUTPUT
R5
1k
COM2
NO2
B
RELAY_DPDT_b
CONTROL 5
VOLTAGE
D5
1N4001
D4
POT
R3
500
R4
10k
C3
0.1 mF
GND
12V
REAR
CHIME
C4
0.1 mF
Q1
2N2222A
You can both protect your door chime and obtain pleasing chime repetition with this circuit.
www.ednmag.com
design
ideas
Figure 1
1
IN1
5V
DS1010-400
VCC
14
10%
CLK=1.0416 MHz
CLK22
TAP1
10%
TAP2
CLK23
10%
10%
4 TAP4
10%
TAP3
12
TAP5
10%
5 TAP6
10%
TAP7
CLK24
10%
6 TAP8
10%
GND
7
TAP9
10%
TAP10
(a)
(b)
Using a delay line and a phase-comparison scheme with XOR gates (a), this circuit multiplies the input clock by 2, 3, and 4 without a PLL (b).
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design
ideas
Figure 2
(a)
(b)
(c)
3 (a), 33
3 (b), and 43
3 (c).
Internally delayed clock signals produce the desired clock-multiplication factors of 23
(tpdHLtpdLH) presents a problem. A standard delay line with fixed and known delay taps is preferable.
The circuit in Figure 1a uses a Dallas
Semiconductor (www.dalsemi.com) DS1010-400 delay line, which has 10 builtin fixed delays of 40 nsec, to implement
a 23, 33, and 43 clock multiplier that
operates from an external 1.0416-MHz
clock. This design requires XOR gates
with short propagation delays, such as
advanced-bipolar or fast CMOS gates
with propagation delays of less than 10
denominator and then multiply the result by the numerator, but the circuit
would become relatively complex and require analog components.
However, if your application can
tolerate some clock jitter, there is another answer: the binary-rate-multiplier
(BRM) circuit. This well-known circuit
works by multiplexing two dividers into
and out of the divide path. Unfortunately, it is sometimes difficult to find the set
of design parameters that gives the least
design
ideas
f IN
,
fOUT
(2)
and
DIV2 = DIV1 + 1.
(3)
fIN
fOUT
(REP1 + REP2 )
11 .
(REP1 DIV1) + (REP2 DIV2 )
(4)
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design
ideas
brightness has been economically unfeasible in most scanners because it is costly to implement a high-current voltage
source that is also software-programmable. However, you can use a simple, lowcost circuit to implement full-range
lamp-brightness control (Figure 1).
The fluorescent lamps in most low-
Figure 1
SENSOR OUTPUTS
LIGHT
SENSOR
PC
PC
PARALLEL
PORT
IC1
LM9830
12V IN
LAMP-BRIGHTNESS
CONTROL SIGNAL
OBJECT TO
BE SCANNED
0 TO 12V OUT
LAMP
ASSEMBLY
LAMPBRIGHTNESS
CONTROL
REGULATOR
STEPPER
MOTOR
A
12V
A
B
B
SENSEA
SENSEB
A lamp-brightness control regulator provides full-range brightness control depending on the duty cycle of the control signal from IC1.
12V IN
Figure 2
10k
Q1
NDP6020P
8
5.1k
7
C2
0.01
+
CONTROL
SIGNAL
C1
22 mF/25V
VOUT
0 TO 12V AT 0.5A
VOUT=122
(DUTY CYCLE)
D
G
2.8k
1%
1/4W
R1
2k
1%
1/4W
R2
IC1B
R5
51k
R3
100k
1 6
R4
100k
R6
51k
+
C5
47 mF/16V
5V
0
F=10 TO 50 kHz
1
IC1A
LM358
+
GND
C3
0.1
C4
0.1
GND
NOTES:
ALL RESISTORS ARE 5% TOLERANCE, 1/8W, UNLESS OTHERWISE INDICATED.
C1 AND C5 ARE SOLID TANTALUM. ALL OTHER CAPACITORS ARE CERAMIC.
SOLDER Q1 TO PC BOARD WITH COPPER AREA 1 IN.2 FOR HEAT SINKING.
This control regulator averages the control signal to provide an adjustable reference input to IC1B that ultimately determines the level of VOUT.
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design
ideas
VC 4 = 5V DUTY CYCLE.
R1 + R 2
= VPK
R2
DUTY CYCLE
R1 + R 2
,
R2
VCC
R1
1
LM393
+
R3
R2
(a)
VCC
R1
10k
1
LM393
+
1k
R2
10k
ZVN3306
(b)
The classical Schmitt-trigger circuit (a) requires an iterative adjustment and the op amps sink current affects the ability to adjust the circuit. The adjustable levels of an improved circuit (b) are completely independent.
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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design
ideas
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design
ideas
Figure 2
SIX CELLS 12V
+
1 mF
FOUR CELLS 8V
4.5V
THREE
AA CELLS
28.0k
A THREE CELLS 6V
14.0k
BATTERY
+
ONE CELL 2V
R4
499k
28.0k
2
100k
RANGE SWITCH
R1
16.3k
R2
60.9k
3
R3
5k
IC2
LTC1096
R5
16.9k
8
R6
2k
1
+
VCC
50-mA
PANEL
METER
~
(~60
mV)
IC1
LT1541
TO PIN 6
TO PIN 1
2
3
VREF
CS/SD
+IN
CLK
1IN
DOUT
1
7
TO
mP
GND
4
1.2V
METER FACE
0 TO 100%
To measure a sealed lead-acid batterys open-circuit voltage, an expanded-scale voltmeter circuit uses an op amp and reference to provide the necessary gain and offset to drive an analog or digital-panel meter, or optionally an ADC.
www.ednmag.com
design
ideas
put drives a standard 50-mA analog panel meter with a scale from 0 to 100%. You
can also use a 1V full-scale digital panel
meter or an ADC (Figure 2). The 8-bit
ADC, IC2, uses the 1.2V reference voltage
of IC1 for the ADC reference, giving a
full-scale output (8 bits) for a 1.2V input.
If you use the ADC, the op amps gain
must increase from 5 to 6 to provide an
output of 1.2V from the op amp for a
200-mV change at the input. To make
this change, you simply increase the value of R4 to 600 kV. You can also use analog meters ranging from 100 mA to 1 mA,
if you reduce the values of R5 and R6.
Calibrating the circuit requires an adjustable voltage source, preferably with
coarse and fine voltage adjustment and
a digital voltmeter. With three AA cells
for power and the range switch in the
one-cell position, apply a precise
12.130V to the input at point A. Connect a DVM to the op amp output (Pin
1) and adjust R3 for a 1.000V reading on
the DVM. Next, adjust R6 for a full-scale
reading, 100%, on the analog meter. Decreasing the voltage source by 100 mV to
12.030V should drop the DVM reading
0%
1.93
5.79
7.72
11.58
50%
2.03
6.09
8.12
12.18
100%
2.13
6.39
8.52
12.78
design
ideas
40
30
POWER
20
10
0
210
DERIVATIVE
220
230
240
1
1.11 1.23 1.34 1.45 1.57 1.68 1.8 1.91 2.02 2.14 2.25
FREQUENCY (GHz)
40
30
POWER
20
10
0
21
DERIVATIVE
210
DERIVATIVE
22
220
23
230
24
25
240
1
(b)
DERIVATIVE
1.11 1.23 1.34 1.45 1.57 1.68 1.8 1.91 2.02 2.14 2.25
FREQUENCY (GHz)
In a well-behaved system (a), both the power data and its derivative are above the 12-dBm level.
Tests of the same system with a loose connector (b) show that the power curve still doesnt dip
below 12 dBm, but the derivative data indicates the existence of a power hole.
eliminate any chance of shipping an improperly functioning system to a customer. (DI #2360)
Reference
1. Application Note AN64-1, Fundamentals of RF and Microwave Power
Measurements, Hewlett-Packard Co,
Palo Alto, CA.
design
ideas
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design
ideas
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design
ideas
TIME (SEC)
An excited voltage source in the RLC circuit ensures oscillation startup and then quickly fades
away.
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design
ideas
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input of IC8. R1, R2, and the 215V power supply shift the 0 to 5V output level to
approximately 22 to +2V. C1 filters any
high-speed transients that arise from the
switching action of IC6s output.
Op amp IC9 attenuates the integrators
output by 100 and sums the result with
the output of the pedestal DAC. For the
component values of IC8s integrator
stage, the maximum ramp rate at the input of the ADC is approximately 2
mV/msec, which is equivalent to 0.067
LSB per conversion. Feedback of the servo-loop circuit maintains the dc level of
the integrators output by continuously
adjusting the input voltage of the
ADS7805 to the level required for the
Codei-to-Codei+1 output transition.
Thus, the servo-loop circuit locks in the
input voltage to the ADC to maintain the
Codei-to-Codei+1 output transition.
The P=Q16 signal that the circuit clocks
into flip-flop IC7 indicates whether the
programmed Codei exists for the ADC
under test. The output of IC7 connects to
an input control line, CNTL6, on the controlling PCs I/O card. After the control
program sends each new Codei to the
tester, the PC reads the state of CNTL6.
A high level on CNTL6 indicates that
Codei exists and is not missing.
ALIGN PEDESTAL DAC WITH ADC UNDER TEST
Before starting the missing-codes test,
the procedure requires alignment of the
pedestal DACs endpoints with those of
the ADC under test. This alignment ensures that the pedestal DACs output
closely matches the corresponding ADC
input voltage for all codes programmed
to the tester. Under this condition, the
voltage needed to sum with the pedestal
DAC output should be only a few LSBs
(referred to the ADC input), thus keeping
the dc output level of the integrating op
June 10, 1999 | edn 113
design
ideas
Figure 1
5V
CC
CC
19
2
+V
DC
AC
OM
O
BP
22 20
OM
18
23
28
VOUT1
RE
FI
BP
FI
RE
24
1
25
SE
FO
RE
26
1
21
RE
215V
15V
13
1M
14 16 15 17
27
VOUT2
SB
CB
0.0022 mF
0L
100k
DB
DB
DB
DB
DB
DB
DB
7
DB
DB
DB
10
R
EN
1
EN
2
LD
AC
DB
11
M
DB SB
IC11
DAC2813
1 2 3 4 5 6 7 8
9 10 11 12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15V 215V
CC
CC
21
SJ
22
10
10
10 11 12 13 14 15 16
24
IC1
DAC729
VOUT
25
KF
26
KF
IO
IN
F
AG
RE
OU
F
RE
29
30
31
N
32
T
GN
AD
IN
RE
GA
B1MSB
1
33
D
34
B18 LSB
17
VDD
18
DGND
20
19
Y0 Y1 Y2 Y3
IC12
74HC139
G
A
B
23
5V
PC0
PC1
PC2
8255 PORT C
D8
D7
D6
D5
D4 D3
D2
D1
Q8
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D0
8255 PORT B
8255 PORT A
11
19
C
OE
1
18
17
16 15
14 13 12
1Q 2Q 3Q 4Q 5Q 6Q 7Q
IC13
74HC573
8Q
1D 2D 3D 4D 5D 6D 7D 8D
2 3 4 5 6 7 8 9
D15 D14 D13 D12 D11 D10 D9 D8
11
19
C
OE
1
18
17
16 15
14 13 12
1Q 2Q 3Q 4Q 5Q 6Q 7Q
IC14
74HC573
8Q
1D 2D 3D 4D 5D 6D 7D 8D
2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
An analog servo loop tests for no missing codes by finding the ADCs input voltage that corresponds to the Codei-to-Codei+1 output transition.
www.ednmag.com
the line occur only once per analog-todigital conversion or, in the case of the
ADS7805, approximately every 10 msec.
For the variable MinCount set to 3 and
MaxTry set to 30, the missing-codes
tester can test the 10-msec ADS7805 for
all 21621 codes in less than 7 sec. (DI
#2334)
Reference
1. Shill, Mark A, Servo loop speeds
tests of 16-bit ADCs, Electronic Design,
Feb 6, 1995, pg 93.
To Vote For This Design,
Circle No. 415
0.1 mF
15V
7
IC8
4
OPA602
5V
15V
5V
100k
C1
R1
5k
R2
30k
10 pF
215V
14.9k
15V
3
100
100
5
14.9k
1M 215V
215V
10k
+
CL
10k
D
CNTL5
IC10B
215V
CL
IC7
Q
CLK
CNTL6
IC5C
330 pF
1k
15V
10k
2 2 7
6
+
3
4 IC9
OPA627
74HC74
PR
DUT POWER
IC5B
10k
CLK
5V
LM293
7
IC6
CNTL4
IC10A
74HC74
PR
270 pF
222.2 mF
33.2k
2
200
215V
23
AGND2
BYTE
25
CS
24
R/C
26
BUSY
14
27
DGND
PC4
PC5
PC6
8255 PORT C
28
VANA
VDIG
ADS7805
DUT
VIN
D15 D14 D13 D12 D11 D10 D9
6
10
11 12
D8
13
D7
10 mF
P>Q16
D6
D5
D4
D3
15 16 17 18 19
D2
D1
D0
IC4A
74HCOO
20 21 22
P=Q16
IC4C
IC4D
IC4B
IC5A
74HC04
17 15 13 11
P7
P6
P5
P4
8
P3
6
P2
P1
P0
Q6
18 16 14
Q5
Q4
12
Q3
9
Q2
7
Q1
5
P=Q
Q0
3
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P7
P>Q 1
IC2
74HC682
Q7
17 15 13 11
P6
P>QH
P5
P4
P3
P1
P0
P2
P>Q 1
IC3
74HC682
19 P=QH
Q7
Q6
18 16 14
Q7
Q6
Q5
Q4
12
Q5
Q3
9
Q4
IC5D
Q2
7
Q3
Q1
5
Q2
P=Q
Q0
P>QL
19 P=QL
IC5E
3
Q1 Q0
design
ideas
Figure 1
R18
2.5M
C11
470 mF
R19
2.5M
421N4007
+ C12
100 mF
7.4V
2.3W
D4
1N4148
Q1
MMG05N60D
Q2
MGSF1P02
4.7 mF/
350V
C13
L2
10 mH
R17
270
R21
1M
IC2
MOC8103
R1
100k
85 TO 260V AC
R20
1M
C14
47 mF
R22
33k
Q4
BC559C
C10
10 mF
R4
560
C8
470 pF
IC1
MC34063
D6
6.8V
R15
1k
7
6
Q3
MMBT2222
5
R14
10k
C9
470 pF
R8
560
R16
3.3
*AVAILABLE FROM
THOMSON OREGA.
A hysteretic architecture in an offline switch-mode power supply makes it possible to achieve less-than-100-mW standby power.
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design
ideas
Figure 2
(a)
(b)
The turn-off characteristic of a lateral MOSFET (a) results in significant wasted power in a no-load condition; lower parasitic capacitance in an IGBT
leads to lower dissipation during the turn-off period.
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design
ideas
IOUT =
load-grounding possibility;
simple control of IOUT/VIN ratio;
high precision, linearity, stability,
and bandwidth;
wide IOUT range, approximately 1
mA to IC(max) of Q1 and Q2; and
high output resistance of approximately 50 MV. (DI #2365).
To Vote For This Design,
Circle No. 418
V21VOUT
=
R6
Figure 1
15V
R2
IC3
OP-77
100k 1%
R5
R3
115V
100k 1%
15V
100k 1%
15V
15V
Q1
2N3019
VIN
R1
R4
100k 1%
+
IC1
OP-77
R7
33k
115V
V1
R6
VOUT
100k 1%
R8
47k
V2 1k 0.1%
IC2
OP-77
IOUT
Q2
2N4033
115V
115V
A versatile voltage-to-current converter provides a handy current source in many analog applications.
www.ednmag.com
design
ideas
ing amplifier that uses a digitally con1
R
R
Ck
(
1
k
)
VO
y
1 1
trolled potentiometer and a fixed capac.
= 1 21 A = 1
1
V
y
S
1
2
B
itor as an input Tee network. The magj +
R1Ck(11k)
nitude of the gain for this inverting cirIn this equation, k is a number that
cuit is also R2/R1. However, in this case,
R1, C, and the location of the wiper along varies from 0 to 1 and reflects the prothe resistor array of the potentiometer es- portionate position of the wiper from
tablish the cutoff frequency. The upper one end of the potentiometer (0) to the
cutoff frequency is programmable be- other end (1).
cause the wiper of the potentiometer is
The circuits gain expression is
under digital or computer control.
VO
A
= o C .
Several analysis approaches help deVS j + C
termine the circuit gain as a function of
frequency. One approach is to use y, or
This equation has the same form as an
admittance, parameters. If you treat net- equation for an amplifier or lowpass filworks A and B as two ports (Figure 2b), ter with a gain of 2R2/R1 and a cutoff frethe ratio of the short-circuit admittance quency of
coefficient for the input port, y21 A, to y12B
1
fC =
.
2R1Ck(11k)
4
.
2R1C
For the XDCP family of digitally controlled potentiometers (Xicor Inc, www.
xicor.com), k can vary from 0 to 1. The
number of taps or programmable wiper
positions determines the resolution. R1
represents the RTOTAL of the potentiometer. The number of taps varies from 32 to
256, and RTOTAL varies from 1 kV to 1
MV, depending on the potentiometer.
The potentiometer can store a wiper or
cutoff-frequency setting in nonvolatile
memory, which permits the circuits cutoff frequency to return to a predetermined value on power-up.
For the circuit in Figure 2a, gain is 4.7,
and the cutoff frequency varies from 6.4
kHz to a theoretically infinite hertz. The
circuit uses a 10-kV potentiometer, the
X9C103, which has 100 taps and a threewire interface. The circuit is useful for
audio, control, and signal-processing applications. (DI #2367)
To Vote For This Design,
Circle No. 419
X9C103
CS
Figure 2
NETWORK B
5V
INC
UID
2
VS
1 7
CONTROL
AND
MEMORY
R1
R2
R2
47k
3
C
0.01 mF
(a)
kR1 (11k)R1
5V
1
+
VS
7
+
VO
VO
4 LT1097
15V
NETWORK A
(b)
An inverting amplifier that uses a digitally controlled potentiometer and a fixed capacitor provides for a programmable cutoff frequency (a). You can
analyze the circuit as a two-port network (b).
www.ednmag.com
design
ideas
250
0
VOUT=25V
22
200
24
26
VOUT=22.5V
28
210
150
B
C
100
D
212
50
214
216
(a)
10
100
OUTPUT CURRENT (mA)
1000
(b)
10
30
40
50
60
70
80
90
100
Figure 2
20
For a S 5V output, the dropout voltage is less than 2 mV at 90 mA of output current (a). For a 25V output, quiescent current ranges from 127 to 140
mA.
This method eliminates lengthy computations and substitutions. Using this resistor ratio, you select two resistors, assign convenient values, and then
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design
ideas
VNGN
,
GN
where Gt1/R.
Using Millmans Theorem, with
VCC at the top of R1 and RF (FigFigure 2
ure 2), set up the numerator with
a Millman equation. Set up the denominator with another Millman equation
when the output voltage is zero (with only
one voltage source in the denominator).
l F and therefore negAssume that RC is lR
ligible in the calculations. The resultant
equation for the voltage ratio is:
VIN(HIGH)
Figure 1
VIN(LOW )
VNG N
GN
VNG N
GN
R F + R1
= VOLTAGE RATIO.
RF
VX
R1
R2
RN
VN
12 12
+
R
RF
= 1
12
R1
VCC
12V
VCC
RC
R1
R2
RF
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design
ideas
Every month readers pick one Design Idea from the issue as the winner. Congratulations to all the winners, and
keep the innovative ideas coming.
Jan 1, 1998,Fax saver cuts wear, tear, and power, Hugh Adams, Fort
Walton Beach, FL.
Jan 15, 1998, LED flasher and triac pulser work off ac line, Dennis
Eichenberg, Parma Heights, OH.
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design
ideas
To use the circuit, you apply the reference level and adjust the gain at Pin 7 of
IC2B to bring the display to an all-lite
condition. This adjustment artificially
sets the reference to half of the internal
ADCs span. The absolute value of the
deviation about this reference setting is
scaled into eight equal steps above and
below this fixed reference to the limits of
the converter. For a 5V application, this
results in approximately 0.31V indexes
((5/2)/8). The circuit passes the resulting
index to a rate table, which sets the display update period. A second index
pointer increments each time the displays update period times out. Positive
deviations from the reference increment
this mask pointer, and negative deviations decrement the pointer. This second
pointer then indexes through a mask
10.0k
Figure 1
IC2A
MAX475
VCC
30.1k
S2
30.1k
S+
SENSOR+12
GND
2
3
2
+
1
11
POWER GND
POWER+12
4.7k
IC3
LM4040-2.5
6
2
4.7k 5 IC2B
+
VCC
20k
7
560
VREF
4
4.7k
10
IC1
12C671
4.7k
10.0k
VCC
560
560
+
2
10.0k
10.0k
560
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The controllers program for this differential monitoring display provides a dynamic display to the
four LEDs based on the deviation from an initially set sensor or monitored value.
June 2 4, 1999 | edn 113
design
ideas
Figure 1
INIT
1
2
T1
0.2 mF
200:8
mC
IC2
COP8SGR740Q3
5V
TRANSMITTER
IC1
74HCT04
TRANSMIT
MA40B8S
C1
C2
40
C0
39
G3/T1A
38
TXPOS
6
TXNEG
TXNEG
TXPOS
CMPOUT
G7/CK0
32 pF
10 MHz
CKI
8 VCC
6
5V
RESET 34
5
REF
10 F1/CMP1IN2
ECHO 11
F2/CMP1IN+
CMPOUT 12
F3/CMP1OUT
32 pF
8
10
11
12
13
TENA
18
TDATA
19
RDATA 20
(a)
(b)
GND
L1/CKX
33
L2/TDX
L3/RDX
J1
RJ11 6P4C
RECEIVER
1k
1M
0.01 mF
5V
RECEIVE
MA40B8R
0.01 mF
1
3
5V
3.9k
100k
100k
100k
RDATA
5
IC4
D2
C7
4 0.001 mF 1N60
LMV821
D1
1N60
TENA
DIRECT-RECEIVE INHIBIT
5V
ECHO
TDATA
RS-485 INTERFACE
VCC
IC3
1
8
RO
VCC
2
7 TXD2
RE
DO
3
6 TXD+
DE
DO
5
4 DI
GND
(e)
C2
0.001 mF
D3
1N4148
INIT
R1
47k
+
10 mF
R2
1M
1 2 3 4
DS36F95
5V DECOUPLING CAPACITORS
REF
C1
0.015 mF
+
100 mF
0.1 mF
0.1 mF
0.1 mF
(f)
(c)
(d)
The range-finder module consists of five main subcircuits: a transmitter (a), a mC (b), a receiver (c), a direct-receive inhibit circuit (d), and an RS-485
interface (e), in addition to the requisite decoupling capacitors (f).
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design
ideas
VOLTAGE (V)
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design
ideas
VIN
Figure 1
48V
DC
0.068
12V
SUPPLIED
SEPARATELY
+ 1.5 mF
470 mF
63V
6.3V
MURS120
100
100
1 mF
1 mF
Q1
S2 12V IN BOOST
S+
301k
TG
RUN/SD
LT1693-2
IC1A
12V
CT
VREF
SS
IAVG
VC
10k
C1
1.8
nF
0.1
mF
Q3
Q2
LT1693-2
COLL
V+
IC2A
IC2B
MBR0530
0.1 mF
Q4
IC1B
100
12V
13:2
VIN
SGND BG
VFB
PGND
R1
2.49k
LT1431
IC4 REF
GND-F
GND-S
BAS16
S1
ERROR
AMP
VOUT
1.5V
15A
5.1
MURS12022
1 mF
5V
REF
1.5 mH
4.7 nF
MBR0530
TS
IC3
LT1339
C2
680 pF
R2
33.2k
GAIN=3
1.56k
30.1k
100
0.1 F
FOLDBACK 12V
ILIM
MMBT3906
C3
100 pF
470
mF
6.3V
28
IC5A
LT1431
30.1k
10k
+SENSE
10k
1.96k
2SENSE
100
NOTES:
Q1 AND Q3=MTD20N06.
Q2 AND Q4=SI4420.
A two-transistor forward converter, Q1 and Q3, with synchronous rectifiers Q2 and Q4 converts 48V dc to 1.5V at 15A.
www.ednmag.com
design
ideas
TRANSIENT
RESPONSE
WITH S1 CLOSED
(40 mV/DIV)
66.4 mV
TRANSIENT
RESPONSE
WITH S1 OPEN
(40 mV/DIV)
96.8 mV
LOAD STEP
(10A/DIV)
20 mSEC/DIV
OUTPUT-VOLTAGE TRANSIENT RESPONSE
The peak-to-peak deviation with S1 open is 96.8 mV (center trace). Closing S1 to short C2 decreases
this deviation to 66.4 mV (top trace.)
www.ednmag.com
design
ideas
Figure 1
5V REF
UC3842/3/4/5BASED
SWITCHER
8
1
R1A
4.7k
IC1
R8
1.5M
5V REF
8
1
R1
10k
IC1
Q1
2N3906
UC3842/3/4/5BASED
SWITCHER
R2
47k
Q1
2N3906
R2
47k
(a)
C1
1 mF
LATCHING
1.5M
8
2
IC2A
LM393
3
+
R3
390
C1
1 mF
R5
33k
R1B
4.7k
1k
R7
1.5M
+
IC2B
390
C2
1 mF
R6
100k
1.5M
CYCLING
R4
(b)
Manipulating Pin 1 of a UC384x switcher allows you to add more overcurrent protection (a). A dual-comparator circuit allows for cycling or latching off
when the switcher is in current-limit mode (b).
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design
ideas
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Address
Country
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A11
A12
A13
A17
A18
A01
A02
A03
A07
A08
C2,1 C2,0
C3,1 C3,0
C1,1 C1,0
C7,1 C7,0
C8,1 C8,0
C7,11 C8,11
C7,10 C8,10
C7,1 C8,0
C7,0 C8,0
A series of eight quad-output voltage DACs provide 32 channels that you can individually program.
All of the DACs simultaneously update.
design
ideas
0PA4277
5V
3 +
2
Figure 1
4
10
100
11
11
12
25V
13
0.01
14
15
5 +
6
5V
16
SDI
5V
+
1
REFH
REFL GND
1
VDD
VOUTB
CHANNEL 1
VOUTC
CHANNEL 2
CHANNEL 3
LOADREG
RESET
VOUTD
CHANNEL 4
100
11
12
13
14
15
5V
16
SDI
5V
REFH
REFL GND
VDD
11
12
100
13
0.01
14
15
5V
CS
VOUTB
LOADDACS
VOUTC
16
RESET
VOUTD
SDI
REFH
REFL GND
+
1
8
VDD
CHANNEL 8
25V
VSS
7
VOUTA
CLK
CHANNEL 9
6
CS
VOUTB
DAC7615
LOADDACS
CHANNEL 10
3
VOUTC
CHANNEL 11
LOADREG
2
RESET
+
0.01
12
CHANNEL 7
5V
VOUTD
11
CHANNEL 6
CHANNEL 12
RESETSEL
10
CHANNEL 5
LOADREG
100
5V
25V
VOUTA
DAC7615
14
VSS
RESETSEL
10
8
+
1
8
CLK
10 +
SDI
1
5V
REFH
REFL GND
1
VDD
+
1
8
25V
VSS
VOUTA
CLK
7
CHANNEL 13
6
CS
VOUTB
DAC7615
13 LOADDACS
14
LOADREG
15
RESET
16
RESETSEL
CHANNEL 14
3
VOUTC
CHANNEL 15
2
VOUTD
CHANNEL 16
22.5V
SYSTEM
REF LOW
19 18 17 16 15
14
13 12
11
G2 Y1 Y2 Y3 Y4 Y5 Y6
74HC541
G1 A1 A2 A3 A4 A5 A6
Y7
A7
A8
13 25 12 24 11 23 10 22
RESETSEL
10
2.5V
SYSTEM
REF HIGH
25V
VOUTA
DAC7615
LOADDACS
13
VSS
CS
12
+
1
8
CLK
0.01
+
1
9 21
8 20
7 19
Y8
6 18 5 17
74HC04
4 16
3 15
2 14
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0PA4277
5V
3 +
2
4
1
10
100
11
12
25V
13
0.01
14
15
5 +
6
5V
16
SDI
REFH
REFL GND
1
VDD
11
12
13
14
15
5V
VOUTC
RESET
VOUTD
RESETSEL
16
SDI
CHANNEL 17
CHANNEL 18
CHANNEL 19
CHANNEL 20
10
11
12
100
0.01
5V
5V
REFL GND
1
VDD
DAC7615
LOADDACS
VOUTC
RESET
SDI
VOUTD
5V
16
CHANNEL 21
CHANNEL 22
CHANNEL 23
REFH
REFL GND
+
1
8
VDD
25V
VSS
VOUTA
7
CHANNEL 25
6
CS
SDI
CHANNEL 24
5V
+
1
CLK
0.01
15
RESETSEL
VOUTB
14
LOADREG
DAC7615
VOUTC
CHANNEL 27
2
VOUTD
CHANNEL 28
1
5V
REFH
REFL GND
1
VDD
+
1
8
25V
VSS
VOUTA
CLK
CS
LOADDACS
CHANNEL 26
3
13
VOUTA
VOUTB
100
12
25V
VSS
CS
14
11
+
1
8
CLK
13 LOADDACS
14
LOADREG
15
RESET
16
RESETSEL
10
REFH
VOUTB
LOADREG
100
10
13
VOUTA
DAC7615
LOADDACS
12
25V
VSS
CS
+
1
8
CLK
0.01
10 +
1
5V
+
1
VOUTB
DAC7615
7
CHANNEL 29
6
CHANNEL 30
3
VOUTC
CHANNEL 31
LOADREG
RESET
RESETSEL
2
VOUTD
CHANNEL 32
The controlling software transposes eight 16-bit words into a vector of 16 8-bit words.
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design
ideas
Figure 1
12 17
VDD 21
DB0
DB11
DAC-8222
REF08
15V
(210.24V)
VREFA 4
22
5 DGND
AGND
23
IOUTA
RFBA
20k
0.1%
215V
2
+
2
+
OP400
11
10
5k
1%
15V 215V
VX
14
5
15V
100k
18
VY
2AIN2
AIN1
2BIN2
2AIN4
11
7
OSC
16
BIN1
13
12
VIN
9
6
2
+
215V
20k, 0.1%
10
GND
10k, 0.1%
6
VIN
SELECT
18 DAC2A/DAC2B
LDAC
19
WR
20
IOUTB
RFBB
24
VOUT
1 mF
VREFB
10 nF
LTC1040
AOUT
2BIN4
BOUT
AIN3
A+B
4
15
3
OUT 1
OUT 2
OUT 3
BIN3
GND
9
STROBE
1
A precision comparator uses a D/A converter to provide precise, noninteractive control of the upper and lower thresholds.
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Figure 1
12V
Figure 2
51.1k
10k
51.1k
51.1k
Q2
BC857
DC
VCC
12V
100k
300
5V
VOUT
R1
51.1k
51.1k
V
DC IN
5V
VIN
Q3
BC847B
300
VOUT
IC1
300
Q4
BC857B
Q1
BC846
Q3
BC846
Q2
BC807-25
100k
3k
100k
300
Q1
BC817-25
100k
R1
2.87k
R2
R2
51.1k
+
DC
VEE
12V
212V
A simple logic gate cuts power drain and provides high-speed operation
with symmetrical rise and fall times.
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design
ideas
differ in turning Q1 and Q2 on; the output rise time can be 50% longer than the
fall time. To obtain high speed and avoid
transmission errors stemming from
wrong bit length, you must lower all the
resistor values, thereby raising power
consumption.
The circuit in Figure 2 draws current
only when turning Q1 or Q2 on. When the
output of IC1 is low, Q3 is on, and the reverse-biased Q4 is off; no current flows
in R1 and R2. When the output of IC1 goes
high, Q3 turns off while Q4 turns on. Because the two branches are symmetrical,
the time constants are similar, and the
output exhibits similar rise and fall times
(Figure 3). With one-tenth the power
consumption of the circuit in Figure 1,
the circuit achieves the same transmission speed without risk of bit-length error from asymmetrical rise and fall times.
(DI #2378)
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design
ideas
Figure 2
Figure 3
RDEN
(OPTIONAL)
RESET
ALE
You can exploit otherwise unused control signals in Figure 1s configuration to generate a
Reset signal.
ware time budget. The serially connected 100V resistors degrade the slew rate
of the signals routed to the PC to prevent
transmission-line effects on the parallel
ports cable. The 1-kV pullup resistors
connect to the open-collector signals on
the Control Port. The 10-kV pullup resistors eliminate floating conditions on
the AD(7:0) bus. This application needs
no Reset signal. If your design needs one,
you can generate it by using a memorymapped port or an unused combination
of the control signals (Figures 2c and 3).
In this case, you need a larger CPLD. (DI
#2374)
(a)
(b)
(c)
A PC takes over a mCs job in controlling the write (a) and read (b) cycles in an application; an
optional Reset generator (c) requires a somewhat larger CPLD.
5 monolithic-microwave IC (MMIC)
from Mini-Circuits (Brooklyn, NY,
www.minicircuits.com) as the RF amplifier. Its easier to use such an off-the-shelf
part than to configure your own gigahertz-region amplifier.
You can consider the approach in Figure 1 as a sort of transimpedance amplifier with addition of a feedforward compensation path. The circuit processes
signals from 0 Hz to the high-frequency
cutoff of the MMIC (approximately 4
GHz for the ERA 5). Current from the reverse-biased photodiode, DP, an InGaAs
design
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ideas
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the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
Fax
Company
Address
Country
Design Idea Title
ZIP
Signed
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
design
Edited by Bill Travis and Anne Watson Swager
ideas
AC LOAD LINE
IB
IC
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DC LOAD LINE
(b)
V=5V
A single-stage synchronous oscillator converts audio or video to FM (a). The load line is a combination of a straight line and an ellipse (b).
July 22, 1999 | edn 125
design
ideas
10 TO
15V
INPUT
+
D1
100 mF P6KE36A
50V
MUR120
MUR120
T1
100 mH
24V/200-mA
3.6k
OUTPUT
(6.7 mA
MINIMUM LOAD)
L1
+ 100 mF
50V
100 mF
50V
Figure 1
VIN
1N4148
200
SW
LT1172
18k
FB
GND
VC
1k
10 nF
C1
100 nF
The second coil of this unusual flyback converter is not a coil but rather an off-the-shelf gatedrive transformer. This component offers 3750V rms isolation and full VDE approval.
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VCC
VCC
Figure 2
Figure 1
VIN, so VOUT goes low. VOUT stays low until VIN drops below V2. When VIN drops
below V2, VOUT goes high again; V2tVCC;
and R1, R2, and R3 set V1.
You can easily set either trip voltage
without affecting the other. However, V1
must be greater than V2 or both trip voltages will be equal to V1. A disadvantage
of this circuit is that it requires two comparators, but comparators usually come
in dual packages. (DI #2383)
VCC
R1
RA
RL
RL
R2
2
VIN
1
+
8
1
VOUT
4
LM393NE
R3
5
VIN
+
A
1
VOUT
RF
RB
VCC
(a)
V2
V1
VOUT
VCC
2
R4
V2
1 8
B
+
4
R5
0
(b)
VIN
design
ideas
share the same line. The design also overcomes the shortcomings of modem interference protectors. The design elimi-
MODEM MODE
HUNT
NO HUNT
OFF
Figure 1
HUNT ORDER
L1>L2
L2>L1
VCC
S2
VCC
470
VCC
470
VCC
470
470
S1
PHONE
L2
L1
SN75447
VCC
10k
10k
VCC
4.7k
10k
14
VCC
16
PIC16F84
RA3
IC1
OSC1
RA2
RA0
L2_CNTL
L1_CNTL
RB7
RB6
RB2
RESET
MCLR
RB1
GND
RB0
1Y
2A
2Y
17 MODEM_CNTL
3
L1_OH
12 L2_OH
8
HUNT_SW
L2>L1_SW
MODEM_OH
CLMP
MODEM
L2
L1
L2_CNTL
VCC
1A
1Y
2A
2Y
1 S
CLMP
3
5
M_CNTL
VCC
L1_ON_HOOK
L2_ON_HOOK
M_ON_HOOK
VCC
10k
(a)
L1_CNTL
SN75447
2
100 pF
1A
R1, 1M
K4
R2, 1M
GREEN
P1
L2 TIP
TO
TELEPHONE
LINE
13
L1 RING
RED
L1 TIP
4
VCC
L2 RING
6
8
13
YELLOW
16
J1
PH L2 TIP
RED
K5
5
6
4
3
11
9
K2
M_CNTL
L1_ON_HOOK
L2_ON_HOOK
13
1
16
RJ14
BLACK
6
4
3
GREEN
J2
M_ON_HOOK
TO
PHONES
K6
K3
11
2
PH L1 RING
3
PH L1 TIP
4
PH L2 RING
5
YELLOW
6
8
L2_CNTL
GREEN
R3, 1M
R4, 1M
BLACK
L1_CNTL
6
4
3
K1
16
RJ14
11
9
RED
VCC
MODEM RING
MODEM TIP
TO
MODEM
3
4
RJ14
100
100 mF
25V
10V POWER
TL780-05
1
+
100 mF
25V
IN
OUT
COMMON
GND
320.1 mF
VCC
(b)
A low-cost mC with flash memory controls the connection of phone lines L1 and L2 to the modem (a). Electromechanical relays switch the phone lines
while providing an isolated data path (b).
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ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
ZIP
design
Edited by Bill Travis and Anne Watson Swager
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Now the emitter of Q1 is at ground level, and the high level on the Rx interface
output supplies base current to Q1 via R3.
Q1 conducts, and the RS-232C Tx driver
input goes low. The MAX232 driver
transmits a high-level mark signal. In this
way, Q1 and D1 simply provide a route
from Rx to the I/O pin when the circuit
receives characters without echoing
Figure 1
T Q
C0
C1
D Q
T Q
C2
T Q
C3
T Q
C3
T Q
C4
T Q
C4
C0
T Q
C1
T Q
C2
T Q
C3
T Q
C4
C1
T Q
D Q
C0
C2
T Q
Figure 3
Figure 2
D Q
Mbps plesiochronous-digital-hierarchy
test set. You can extend the technique (to
more than 15 bits or so) to propagate the
LSBs in parallel; this extension would
give the ripple path four clock cycles to
settle. The downside of this method is
that next-state errors would occur if you
needed a resettable counter, though you
can usually design out the requirement
for such a counter at the system level. (DI
#2388)
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design
ideas
Figure 1
VIN1-2
RINPUT1-2
VIN1
VIN2
RINPUT1
RINPUT2
VIN2-2
RINPUT2-2
AVDD
IC1
DDC112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN1
AGND
CX1BN
CX1BP
CX1AN
CX1AP
AVDD
TEST
CONV
CLK
DCLK
DXMIT
DIN
DVDD
DVDD
C1
AVDD
C2
10 mF
+
0.1 mF
AGND
+
10 mF
IN2
AGND
CX2BN
CX2BP
CXA2N
CXA2P
VREF
AGND
RANGE0
RANGE1
RANGE2
DVALID
DOUT
DGND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
C3
1 mF
7
C4
6
0.1 mF
OPA340
+
4
10 mF
IC2
2
3
10k
4.99k
+
10 mF
LM4040-4.1
IC3
0.1 mF
NOTES: C1 TO C4=250 pF
DGND
TO DIGITAL CONTROL
=ANALOG GROUND.
TO DIGITAL CONTROL
=DIGITAL GROUND.
Series input resistors allow a current-input ADC to measure a wide range of voltages.
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design
ideas
Figure 1
VIN
MUR160
R1
8 TO 16V DC
0.100
1/2W
R4
10k
Q4
220 pF
LTC1693CS8-2
6
470
mF
25V
1 mF
4
IC2B
2.2 nF
1M
4-mSEC PULSE
IC1
33 nF
250V
3M
7
R2
2.49M
4-kV PULSE
T
K
12
Q3
2N7002
LTC1624CSB
FSW=200 kHz
470
pF
1 mF 0.75 TO 1.5 Hz
Q1
1 S1
VIN 8
2
ITH BOOST 7
3
6
VFB
TG
4
GND
SW 5
10
6.8k
1M
+
7
2
IC2A
2.2 nF
1M
D1
7.5V
33
T1
COILTRONICS
VP3-0138
1:5
11.2
mH
100
MMBT3904
250V DC
1
nF
T2
COILTRONICS
CTX110655
1:67
C1
68 mF
400V
4
7
4.3
mH
1M
100 nF
100 nF
R3
12.4k
Q2
10
NOTES: Q1, Q2=FAIRCHILD NDT410EL.
FLASH TUBE=RADIO SHACK 272-1145.
FOR T1, CONNECT PINS 3 AND 11, 4 AND 10, 5 AND 9, AND 6 AND 8.
A complete circuit for an emergency lamp operates from a 12V automotive battery and generates a 250V-dc anode voltage and a 4-kV trigger pulse for
the Xenon flash tube.
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design
ideas
Figure 1
INPUT
10 mH
CDR74B-100
LX
MBRS130
POUT
10
5%
ONB
20k
5%
R3
0.22 mF
Q1
NDC632P
CLK/SEL
3.3V AT
800 mA
LBP
MAX1701
220 mF
10V
OUT
174k
1%
0.22 mF
47 mF
16V
+
165k
1%
R1
FB
3.3V
ON/OFF
ONA
100k
1%
AO
REF
0.22 mF
100k
1%
R2
AIN
This buck/boost circuit assumes the buck, or linear-regulator, mode for inputs above 3.3V and the boost, or switching-regulator, mode for inputs
below 3.3V.
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the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
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ZIP
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ideas
levels and one adjustable level for undervoltage conditions. The adjustable input
of the IC monitors the 12V supply. The
LTC1536 also acts as the logic input for
the open-drain outputs of the LTC1444
quad comparator.
Comparators A, B, and C of the
LTC1444, along with resistors R1 through
R6, monitor the 3.3, 5, and 12V positive
supplies, respectively, for an overvoltage
condition. The nominal overvoltage trip
points are 3.61, 5.28, and 12.6V. Com-
3.3V50.3V
0.1 mF
3
R1
2.37M
1% 4
Figure 1
R2
1.21M
5
1%
LTC1536
1
_
A
5V
5V55%
R4
1.21M
1%
R5
9.31M
1%
B
7
10
R6
1M
1%
PBR
2 V
CC5
3 V
SRST
CCA
RST
GND
RST
R9
1.05M
1%
R10
102k
1%
5 SYSTEM
RESET
_
C
11
VCC3
12V
R3
4.02M
1%
12V55%
LTC1444
16
12
_
D
13
15
112V510%
R8
R7
10.7M 1.21M
1%
1%
REF
1.221V
8
14
9
HYST
Two ICs monitor PCI-system quad supplies for undervoltage and overvoltage fault conditions.
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design
ideas
Figure 1
R
T1
PID
CONTROLLER
1
IC5
+
R
+
IC1
T2
R
1
IC6
+
R
+
IC2
Q1
TEC1
Q2
TEC2
Q3
TEC3
D1
PID
CONTROLLER
R
RB
R
RB
R
D2
R
R
NOTES:
PID
T3
R=10 kV, RB=1 kV, RSENSE=1V.
CONTROLLER
IC1 THROUGH IC8= TL084 QUAD OP AMP.
Q1 THROUGH Q4=TIP120 DARLINGTON
TRANSISTOR.
D1 THROUGH D4=1N914.
VREF
T1 THROUGH T3=10k AT 208C.
1
TEC1 THROUGH TEC3=1A AT 1V FULL RATING.
IC4
PID BLOCK IS A GENERIC RESISTANCER
+
INPUT AND VOLTAGE-OUTPUT ANALOG
CONTROL CIRCUIT.
IC3
1
VMAX
D3
D4
1
IC7
+
R
RB
R
R
VLIM
1
IC8
+
RB
Q4
RSENSE
A series connection of thermoelectric coolers provides more efficient temperature control and fewer supply-current requirements than circuits using
individual cooler controllers.
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design
ideas
practical realization of a
spread-spectrum technique
Figure 1
x2(t)
lowers a mPs clock-related
EMI by approximately 4 dB without the
D
drawbacks associated with modulation
IC1
IC2
x1(t)
CRYSTAL
(Figure 1). The spread-spectrum tech5
CLK
x(t)
OSCILLATOR
Q
nique is a popular method to reduce mPclock-related EMI (Reference 1). Using
IC3A
IC3B
this method, the mPs clock frequency
constantly shifts around and creates a
moving target for quasipeak EMI detection. Although this method dramatically reduces measured EMI, it has a few Simple logic gates implement a spread-spectrum technique that produces predictable clock behavdrawbacks.
ior and introduces no unwanted modulation frequencies.
The first drawback is an unpredictable
clock frequency. Peripheral devices that
share the same clock with the mP
Figure 2
and rely on a stable clock fre+1
quency might suffer. One example is an
x1(t)
ADC that relies on direct mP control to
21
define the sampling time. The second
+1
drawback is the periodic nature of the
x2(t)
frequency shift. The technique essential21
ly modulates the clock frequency with an
approximately 50-kHz frequency. This
+1
x(t)
frequency is slightly higher than the au21
dio band to prevent audio hum. In
(a)
some systems, however, this 50-kHz
v1
modulation frequency may be in band
with data-acquisition or other sensitive
analog circuitry. Under these circumstances, separate nonmodulated digitalcontrol and clock signals are necessary to
v1+v2
v12v2
prevent demodulation of 50-kHz frequency and to prevent analog noise.
Consider the product of two square
(b)
signals with unity amplitude, x1(t) and
x2(t), where x1(t) is a square signal with
frequency v1 and x2(t) is a square signal Multiplying x1(t) by x2(t) produces x(t) (a). In the frequency domain, the multiplication causes the
with frequency v2 in radians (Figure 2a). original main frequency component, v1, to split into two equal components (b).
The Fourier transforms of square waves
x1(t) and x2(t) are:
x(t) = x1(t)x 2 (t) =
sin(3 2 )
+
+
sin(
)
sin(31)sin( 2 )
sin(31)
+
sin(1)sin( 2 ) +
4
3
+
+
sin(
)
4
=
.
x
(
t
)
3
1
2
4
.
3
sin(
5
)
2
x1(t) =
, and
sin(3 2 )sin(1)
+L
L+
+L
sin(51)
+L
3
5
www.ednmag.com
design
ideas
for simplification:
x(t) =
4
sin(1)sin( 2 ) =
4 1
1
cos(112 )1 cos(11 2 ).
2
2
If v1 is the frequency of the crystal oscillator and v2 is the result of the frequency division of v1 by 128, for example, then you can rewrite the previous
equation as follows:
x(t) =
4
sin(1)sin 1 =
128
4 1
1
1 1
.
cos 11 1 cos 1 +
128 2
128
2
shift of 180 occurs during x2(t)s transient from logic 0 to logic 1; the second
shift of 2180 occurs during the transient from logic 1 to logic 0.
From the mPs perspective, the clock
signal loses one full period of x1(t) over
one full period of x2(t). In this example,
if you program the mPs internal timer to
127 cycles, the clock counts 128 cycles of
the original crystal frequency.
If you use this technique, you can easily predict the mPs clock behavior. For
example, sampling with every period of
x2(t) introduces no noise into the ADCs
reading. The frequency content of the
digital clock and other digital signals
contains no low frequencies, such as 50
kHz, so the digital clock does not cause
any noise in the analog sections. (DI
#2391)
Reference
1. Bolger, Steve, and Samer Omar Darwish, Use spread-spectrum techniques
to reduce EMI, EDN, May 21, 1998, pg
141.
design
ideas
5V
IC1
M-8870
DTMF
RECEIVER
(TELTONE
CORP)
Figure 1
ELECTRET MICROPHONE
(PANASONIC, WM-62A)
COMPUTER'S
SOUND-CARD
MICROPHONE
SPEAKER
INPUT
+
DTMF
.WAV
"BEEP"
MICROPHONE
SHIELD
5V
R1
10k
1 IN+
R2
10k
C1
0.1 mF
2
3
R3
470k
4 V
REF
EST
STD
15
14
Q3 13
8 OSC
2
Q1
VSS
OE
11
R5
1k
C2
0.1 mF
5
6
8
IC2C
4011
7
4
9
IC2D
4011
10
16
6 IC
Q2
14
12 IC
2B
13 4011
17
Q4
OSC1
IC2A
4011
5
5 IC
3.579545 MHz
X1
5V
VDD 18
IN1 ST/GT
GS
1
2
R4
330k
PUSH TO
RESET
S1
5V
R7
220
12
D1
11
10
5V
P1
PIEZO BUZZER
(RADIO SHACK,
273-065)
R6
1k
Q1
2N2222
Tired of missing incoming e-mail? This circuit provides a permanent indication of incoming messages.
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design
ideas
5V
Figure 1
5V
IC1
LM555
3k
3200 Hz
0.047 mF
5V
IC2
7490
14
5V
0V
14
0.33 mF
IC5
7400
0.15 mF 30k
4
100k
14
7
5V
7 10
5V
0.33 mF
1600-Hz BURST
12
0.33 mF
0V
5V
5V
0V
1600 Hz
0.33 mF
0.33 mF
3k
IC3
LM555
10
11
IC4
74121
100k
100k
12V
6 1
0.33 mF
0.5 TO 3 Hz
1M
5V
1M
0V
RATE
VOLUME
1 mF
10k
IC6
LM386N-1
0.5 TO 3Hz
250 mF/25V DC
+
5V
15V
4
0V
0.1 mF
2-IN.
SPEAKER
10
12V SOURCE
7812
7805
5V SOURCE
Sounding just like an old-fashioned metronome, this circuit sets the cadence for your music practice.
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design
ideas
VDD
Figure 1
R4
1k
D2
1N4001
T1
NTE5629
(OR ANY 400V,
4A TRIAC)
R5
27k
IC4
MOC3010
R3
1k POTENTIOMETER
R2
4k
LOAD
C5
100 nF
400V
D1
1N4001
AC
LINE
VDD
PIN 6
PARALLEL
PORT
VDD
IC1
DAC1220
14
PIN 8
16
2
15
PIN 7
13
22
11
12
7
IC2
OPA340
6
4
10
+3
C1
5.6 pF
CRYSTAL
ECS-V2.5-S
C2
5.6 pF
VDD
C4
3.3 nF
C3
10 nF
R1
24.9k
IC3
REF1004
1
Set your computer areas lighting intensity from the comfort of your swivel chair, using keyboard commands. A simple Pascal routine and some lowcost components do the trick.
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design
ideas
LISTING 1PC-CONTROLLED LIGHT DIMMER
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design
ideas
varies the full-scale current and, therefore, the voltage output from the DDS
device. You can provide the varying voltage by using a voltage-output DAC.
In Figure 1, an AD5310 provides a
variable voltage to the AD9830. With the
DAC output at 0V, the DDS device has
maximum full-scale current. Increasing
the voltage output from the AD5310
reduces the full-scale current of the AD-
AD5310
OUTPUT
BUFFER
VOUT
RESISTOR
NETWORK
RSET
REFIN
FULL-SCALE
ADJUST
FULL-SCALE
CONTROL
FSELECT
32-BIT
PHASE
ACCUMULATOR
FREQ0 REGISTER
ROM
10-BIT
DAC
IOUT
FREQ1 REGISTER
MULTIPLEXER
12
S
FOUR PHASE
REGISTERS
MCLK
INTERFACE
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D0 TO D15 A0 TO A2 WR
PSEL0 PSEL1
By using a voltage-output DAC, you can obtain amplitude modulation in a DDS device that does not
provide for variable output voltages.
September 2, 1999 | edn 133
design
ideas
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design
ideas
HORI1
VERT1
LGND
BLUEG1
REDG1
GREENG1
MGND1
GREEN1
BLUE1
RED1
VERTO
HORI0
LGND
GREENG0
BLUEG0
REDG0
MGND0
GREEN0
BLUE0
RED0
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Bit 6
Keyboard
Bit 5
Bit 4
Bit 3
VCC
VCC
IC1
PIC16F84
14
OSC1
VDD
5
VSS
OSC2
13
RB7
12
RB6
MCLK
11
RB5
10
RB4
RA0
9
RB3
RA1
8
RB2
RA2
7
RB1
RA3
RB0/INT 6
RA4/TOCK1
16
15
4
17
18
1
2
3
Bit 1
MOUSE
ALL
Bit 2
VTT
VGA
MOUSE
KEYBOARD
3.3k
3.3k
VGA
KEYBOARD
Bit 0
Monitor
3.3k
100k
100k
100k
10k
10k
10k
10k
VCC
IC3
MAX395
2
1
SCLK
SCLK
V+
4
24 CS
CS
GND
21
23 RESET
V2
RESET
3
22
D
OUT
DIN
GREENG0 5
NO0
GREENG 6
COM0
7
NO1
GREENG1 8
COM1
BLUOG0 9
NO2
BLUEG 10
COM2
11
NO3
BLUEG1 12
COM3
NO7 20
19
COM7
18
NO6
17
COM6
16
NO5
15
COM5
NO4 14
COM4 13
VCC
IC4
MAX395
2
1
SCLK
SCLK
V+
4
24 CS
CS
GND
21
23 RESET
V2
RESET
3
22
D
OUT
DIN
HORI1
MGND0
HORI
MGND
HORI0
VERT1
MGND1
VERT
VERT0
5
NO0
6
COM0
7
NO1
8
COM1
9
NO2
10
COM2
11
NO3
12 COM3
NO7 20
19
COM7
18
NO6
17
COM6
16
NO5
15
COM5
NO4 14
13
COM4
MOUSE
10k
1
RX
TX
2
3
RTS1T
RTST
5
6
RTS
RTS0T
RX1T
7
8
RXT
RX0T
1
RX1
2
3
VCC
1 mF
1C7
MAX238
10
C1+
C12
13 C2+
12
1 mF
14 C22
5 T1IN
RTS0T 18 T2IN
RXT
19 T3IN
VCC
21 T4IN
RX1T
6 R1OUT
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7 8
VERT
HORI
LGND
BLUEG
REDG
GREENG
MGND
5
LGND
BLUE
RED
GREEN
LGND
RTS1T
9 10 11 12 13 14 15
MONITOR
RX0T
RTST
R2OUT
22
17
R3OUT
R4OUT
VCC
11
V+
15
V2
GND
8
2
T1OUT
1
T2OUT
24
T3OUT
T4OUT 20
7
R1IN
R2IN 3
R3IN 23
16
R4IN
PC1
SERIAL
PORT
1 mF
1 mF
RTS1
7
8
1 mF
RTS1
RTS0
RX
TX
RX0
1
2
3
RX1
RX0
RTS
5
RTS0
PC0
SERIAL
PORT
6
7
8
9
design
ideas
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design
ideas
erence voltage. IC2 provides the base current for the Darlington transistor,
Figure 3
which discharges the battery at a
constant-power rate. Figure 2 shows profiles of the constant-power battery discharge. Figure 3 shows current, voltage,
and power profiles of the constant-power discharge process. When the battery
voltage decreases, the current discharge
increases, and the power remains constant. (DI #2394).
VBAT(V)
POWER (W)
IDISCH(A)
POWER
IDISCH
VBAT
TIME(SEC)
To provide constant-power discharge, the batterys voltage and current profiles have reciprocal,
mirror-image slopes.
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design
ideas
ical measurements show that the compensation is optimal with VREFt1.1V. IC2
amplifies the input signal by a temperature-dependent factor. You obtain
matching of the temperature coefficient
of the sensor to the coefficient of the LED
by inserting the additional 500V resistor
120
Figure 2
1.2
100
1
508C
80
0.4
20
0.2
(a)
20.5
0
VIN (V)
0.5
508C
PLED
(RELPWR) 0.6
40
21
108C
0.8
108C
ILED (mA) 60
0
21.5
0
21.5
1.5
21
(b)
20.5
0
VIN (V)
0.5
1.5
Using the circuit in Figure 1, an LED uses temperature-dependent operating current (a) to produce nearly constant optical power (b) at 10 and 50-C.
design
ideas
ming interface, so it should work with time to familiarize yourself with the anaGrounding may be less than optimum
most sound cards. SoundArb places rel- log limitations of your sound card before because no good way exists to connect
atively light demands on the system, so a relying upon it for important work. For the PCs ground to the ground of the defast CPU and large amounts of memory more information on this, search the on- vice under test. If glitches from the sync
are usually unnecessary. Long arbitrary line help index for the keyword Distor- line are a problem, you may be able to
waveforms may require more memory. tion.
disconnect that lines shield from its BNC
Low-cost sound cards rely on the comTo use the sound card for electronic shell, assuming that the waveform lines
puters main memory for waveform stor- testing, you probably need to make an shield remains connected to its BNCs
age, which means that, if the system is adapter cable (Figure 2). A convenient shell. If necessary, you can break a bad
slow or busy, the waveform may be in- way to make the cable is to obtain two ground loop by isolating, or floating, the
terrupted. The sound card must support male BNC-to-cable connectors, a stereo PC and its monitor from the power-line
the pulse-code-modulation, audio-wave miniphone plug, and a short shielded ground. You cannot use a cheater plug
format; must have 16 bits of resolution; wire. Because of the low frequencies in- because it defeats the safety aspects of
and must have a maximum sample rate volved, you need no coaxial cable. You grounding and can allow the PC chassis
of at least 44.1 kHz. Although standard then connect your normal BNC-to-clip- and peripherals to become hot. To isolate
sample rates are 10.25, 20.5, and 44.1 lead test cables to the male BNCs. Alter- the PC from the power line and its
kHz, many sound cards support any in- natively, you can make a longer cable by ground, use a medical-grade isolation
teger sample rate within a much wider terminating the right channel in a female transformer that includes a Faraday
range. Such a card is a more versatile BNC, which you can connect to the sync shield between the primary and secondfunction generator than one that sup- input of your oscilloscope. You can ter- ary windings. This transformer often reports only the standard sample rates.
minate the left channel in an alligator clip duces interference from noisy power
The resolution and full-scale range of or a minigrabber. If you dont use the lines and may reduce conducted EMI, esthe amplitude adjustment depend on the
design of the sound card. UnforSHIELDED CABLE
LEFT CHANNEL
Figure 2
tunately, no way exists to set the
RIGHT CHANNEL
FEMALE BNCSYNC OUTPUT
amplitude to a known voltage
other than by observing the waveform on
an oscilloscope. Many sound cards have
MALE BNCrelatively few amplitude levels, and these
WAVEFORM OUTPUT
GROUND
levels do not necessarily follow either lin1/8-IN. STEREO MINIPHONE PLUG
ear or logarithmic curves. One card tested provided 16 amplitude steps, including zero. The remaining 15 steps A convenient adapter cable comprises two male BNC-to-cable connectors, a stereo miniphone
followed a two-part piecewise-logarith- plug, and a short length of shielded wire.
mic curve.
If you have a stereo sound card, right-channel sync output, you can get by pecially if used with an RF-line-filter
SoundArb allows you to use the right with one BNC and one piece of cable be- block.
channel as a sync output to mark the cause the program supports only rightNever float the PC or any other test
start of the analog waveform. Note that channel-sync mode. The tip of the mini- equipment as a way to connect the
a sound card reproduces only audio fre- phone plug carries the left-channel ground to a high voltage, for example, to
quencies. Most provide no dc-coupled signal, the first ring carries the right- connect an oscilloscope probe across a
output. The output bandwidth typically channel signal, and the main ring pro- current-sensing resistor in a hot ac powapproximates the 20 Hz to 20 kHz audio vides the ground. Separate shielded ca- er line. Doing so could kill you, and you
band. A good first test of your sound card bles, rather than a shielded twisted pair, could destroy expensive test equipment
is to generate square waves of various fre- between each BNC and the phone plug whose power supply was not designed for
quencies and lengths while monitoring are recommended because with the a ground-to-neutral voltage of more
the output with an oscilloscope. Low-fre- twisted pair the sync pulse edges capaci- than 30V. If you need to connect test
quency square waves may show a pro- tively couple into the waveform and equipment to a high voltage, use optical
nounced droop due to an ac-coupled cause glitches. As an alternative to using or magnetic isolation in the signal wires,
output, and ringing on the edges may be a miniphone plug, most sound cards not in the equipments power supply.
severe. The amplitude and frequency of have an internal waveform output com- Small, modular isolation amplifiers with
the ringing may depend more on the prising a pin header on the card. Some low distortion are readily available at reasample rate than on the waveform repe- cards also have jumpers that you can use sonable prices.(DI #2409)
tition rate. Much of this depends upon to select between line out and speakTo Vote For This Design,
the analog-to-digital-conversion tech- er out, the difference being the output
Circle No. 341
nique that the sound card uses. Take the impedance or voltage.
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design
ideas
Figure 1
VIN
12.6V 61%
AT 2A
+
300 mV
10k
C2
0.1 mF
25V
12.3V'61%
AT 2A
Q1
R2
4.7k
R1
12.1k
0.5%
3
499k
0.5%
VOUT
LT1636
2 _
4
5
C1
0.02 mF
C3
4.7 mF
16V
SHUTDOWN
INPUT
NOTES:
Q1=35-mV P-CHANNEL MOSFET, Si4435 (SILICONIX).
SCHEMATIC SHOWS BODY DIODE.
ON
SHUTDOWN
A feedback loop comprising the op amp and Q1 produces a constant voltage drop between VIN and VOUT, thereby providing a low-voltage, series-zener
type of function.
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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design
ideas
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NEGATIVE
SUPPLY
(13 TO 144V)
1 mF
SENSE
ILOAD
A true low-side, precision current-sense amplifier provides a ground-referenced voltage that is proportional
to the negative supply current and does not float the
load off ground.
VOUT =1
VSENSE
R2 =
R1
ILOAD R SENSE
R2
.
R1
design
ideas
to eliminate base-current errors; however, operation as low as 3V is then unlikely. You can also replace the op amp with
a lower offset device at the expense of
high-voltage operation to 244V. (DI
#2410)
To Vote For This Design,
Circle No. 433
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design
ideas
Figure 1
300
50
24k
MMBTA56LT132
VIN 18 TO 72V
+
220 mF
220 mF
1
COL
3
V+
REF
8
MMBTA06LT1
GF
6
R1
100k
+ BIAS CAPACITOR
L1
VOUT
5V AT 7A
MBR2060CT
2:1
4.02k
5VREF
2
1500 pF 3
5
3k
100 mF
RM
GS
5 LT1431
IC1
0.1 mF
0.1 mF
MUR120
VCC
6
7
8
CT
SYNC
IAVG
12VIN
IC2
VC
SGND
GATE
PGND
RUN/SHDN
VFB
SENSE1
VREF
SENSE+
0.1 mF LT1680CSW
L2
33
10
3.74k
MBR2060CT
470 pF
0.001 mF
1.24k
16
15
330 mF
32
14
13
10
12
IRF640
11
10
MBRS120T3
9
100
R2
11.5k
2200
pF
0.033
A programmable reference, IC1, and a bias-capacitor network control the on/off cycling of IC2s step-up controller during a short-circuit fault condition.
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design
ideas
TRESTART =
C BIAS (VRUN1VUVLO )
.
ICHARGE
where
The output turns on when the bias capacitor reaches 12V (a). During a short-circuit fault, the bias
capacitor continually charges and discharges until you remove the fault (b).
VTHRESHOLD =
VULVO VOUT
.
VCC
design
ideas
5V
Figure 1
2N3906
3.3k
3.9k
3.9k
2.2k
1k
MBD301
680
A
(IN)
680
2A
1k
1k
2.2k
1k
AD8056
(DUAL)
+
2.2k
(A+B)2
1k
(A2B)2
150
+
MAX
4223
MAX
4224
150
+
VOUT
1
680
330
MAX
4224
680
50
330
2.2k
+
3.9k
B (IN)
3.9k
2N3904
15V
NOTE: ALTHOUGH NOT SHOWN, ALL OP AMPS HAVE MANUFACTURER-RECOMMENDED DECOUPLING CAPACITORS.
An MBD301 hot-carrier Schottky-diode bridge forms the core of a four-quadrant analog multiplier that performs continuous computations of the product of arbitrary input signals A and B.
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design
ideas
This four-quadrant analog multiplier from the transistors, thereby improving picofarads. With the 1-kV load for the
is a quarter-squares multiplier based on system bandwidth.
bridge and no bias network, the bridge
the identity:
Without this bias-current network, the output has a pronounced flat bottom
(A1B)22(A2B)254AB.
bridge requires an approximately 5-MV around the origin. Fortunately, with the
The MAX4223 differential amplifier, load resistor for parabolic behavior. This bias current of 1.08 mA in each 3.9-kV
which has a 1-GHz bandwidth, registers value precludes this designs use in high- resistor, the Schottky diodes become for(A1B)2 from the left bridge while sub- frequency circuits because the currents ward-biased into partial conduction with
tracting (A2B)2 from the right bridge to are extremely small and the time con- 340 mV for each path, and the bridge
form the product:
stants are very long when you connect yields an accurate and symmetric squareVOUT5AB/K,
the bridge to an amplifier input of a few law output with a low source resistance.
where the constant, K, is 12
You can use one such bridge
mV. You can add the carri- F i g u r e 3
with the differential amplifier
er at the differential amplias a fast squarer for frequencyfiers input for amplitude moddoubling and square-law deA
ulation as necessary.
tection, for example. With
The differential output
slightly more current, you can
across the 1-kV resistor of each
make the load resistor as little
B
diode bridge is a precisely symas 50V.
metric, even function of the
The multiplier test pattern
voltage across it: A1B for the
in Figure 2 results from a 5left bridge and A2B for the
kHz sine wave on both Input A
C
right bridge. Consequently, the
and the horizontal input and
bridges VOUT contains only
a 20-kHz square wave from a
even terms of the combined
100V source set at 0-, 6-, 12-,
(a)
VERTICAL SCALE=50 mV/DIV
Taylor series due to the four
18-, and 24-mV amplitude levHORIZONTAL SCALE=100 mSEC/DIV
diode currents. The constant
els at Input B. Over this range
terms cancel out because the
of inputs, this multiple expoDESCRIPTION
TRACE
MAX4223 subtracts the bridge
sure shows that the analog
MULTIPLIER OUTPUT WITH A 12-mV, 20-kHz
A
outputs, so the dominant term
multiplier exhibits linear beSQUARE-WAVE CARRIER AT INPUT B
is the square term. Higher orhavior with errors of less than
MULTIPLIER OUTPUT WITH A 12-mV, 20-kHz
B
der even terms do not con1% of full scale. In Figure 3a,
SINE-WAVE CARRIER AT INPUT B
tribute, provided that inputs A
Trace A shows a double-side2-kHz SINE-WAVE-MODULATION SIGNAL AT
C
and B stay at less than approxband, suppressed-carrier outINPUT A
imately 150 mV. For large input resulting from a 228 dBm,
puts, each bridge behaves as a
20-kHz square-wave carrier,
A
full-wave rectifier; the diodes
and Trace B results from a 20become forward-biased with
kHz sine-wave carrier. Trace C
B
resistance smaller than the
shows the 2-kHz modulation
C
1-kV load, and the parabolic
signal on Input A. Figure 3b
D
branches ultimately degenerate
shows double-sideband supinto straight lines that the load
pressed-carrier output signals
(b)
VERTICAL SCALE=10V/DIV
resistor dominates. Therefore,
at Input B frequencies of 10
the multiplier is unusable with
MHz (Trace A), 25 MHz
HORIZONTAL SCALE DESCRIPTION
TRACE
such large inputs.
(Trace B), and 120 MHz (Trace
MULTIPLIER
OUTPUT
WITH
A
500 NSEC/DIV
A
10-MHz SIGNAL AT INPUT B
The circuit includes a balC) using a 600-kHz sine-wave
anced, double current-mirror
modulator at Input A . Trace D
MULTIPLIER
OUTPUT
WITH
A
500 NSEC/DIV
B
25-MHz SIGNAL AT INPUT B
network that supplies the diode
shows that same signal as Trace
MULTIPLIER OUTPUT WITH A
bridge with four bias currents.
C but at 5 nsec/division, to
C
500 NSEC/DIV
120-MHz SIGNAL AT INPUT B
A single 1-kV potentiometer
show that the rise time of the
D
5 NSEC/DIV
TRACE C WITH AN EXPANDED
controls the current, and four
multiplier in this breadboard
TIME SCALE
3.9-kV resistors accurately disversion is just a few nanosecNOTE:
tribute equal, balanced curonds. (DI #2413)
INPUT A IS A 600-kHz SINE-WAVE-MODULATION SIGNAL.
rents to the two bridges while
To Vote For This Design,
preventing crosstalk between Example multiplier outputs include a double-sideband suppressed-carCircle No. 436
the bridges. These four resistors rier with a 20-kHz square-wave carrier at Input B (a) and outputs with
also isolate the diode bridges input frequencies as large as 120 MHz (b).
www.ednmag.com
design
ideas
Figure 1
1N4001
IN
+
9V
0.01 mF
78L05
OUT
R5
15k
GND
S1
TRIGGER
270
R3
15k
0.1 mF
0.1 mF
C1
R6
330k
0.01 mF
R2
15k
R4
330k
C2
12
11
R1
15k
14
IC1E 10 IC1D
9
7
20-mSEC DEBOUNCE
IC1F
3
IC1B
5V
6
0V
NOTES:
QUIESCENT BATTERY DRAIN <<1 mA.
NO POWER SWITCH NECESSARY.
IC1A TO IC1F=1/6 74C04 OR CD4069B.
IC1A
1
13
5
IC1C
100
mSEC
OUTPUT PULSE
IMPEDANCE~150V
This battery-powered debounced pulse generator conserves battery life without using an on/off power switch.
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
ZIP
design
ideas
www.ednmag.com
NEGATIVE
SUPPLY
(13 TO 144V)
1 mF
SENSE
ILOAD
A true low-side, precision current-sense amplifier provides a ground-referenced voltage that is proportional
to the negative supply current and does not float the
load off ground.
VOUT =1
VSENSE
R2 =
R1
ILOAD R SENSE
R2
.
R1
design
ideas
to eliminate base-current errors; however, operation as low as 3V is then unlikely. You can also replace the op amp with
a lower offset device at the expense of
high-voltage operation to 244V. (DI
#2410)
To Vote For This Design,
Circle No. 433
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design
ideas
Figure 1
300
50
24k
MMBTA56LT132
VIN 18 TO 72V
+
220 mF
220 mF
1
COL
3
V+
REF
8
MMBTA06LT1
GF
6
R1
100k
+ BIAS CAPACITOR
L1
VOUT
5V AT 7A
MBR2060CT
2:1
4.02k
5VREF
2
1500 pF 3
5
3k
100 mF
RM
GS
5 LT1431
IC1
0.1 mF
0.1 mF
MUR120
VCC
6
7
8
CT
SYNC
IAVG
12VIN
IC2
VC
SGND
GATE
PGND
RUN/SHDN
VFB
SENSE1
VREF
SENSE+
0.1 mF LT1680CSW
L2
33
10
3.74k
MBR2060CT
470 pF
0.001 mF
1.24k
16
15
330 mF
32
14
13
10
12
IRF640
11
10
MBRS120T3
9
100
R2
11.5k
2200
pF
0.033
A programmable reference, IC1, and a bias-capacitor network control the on/off cycling of IC2s step-up controller during a short-circuit fault condition.
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design
ideas
TRESTART =
C BIAS (VRUN1VUVLO )
.
ICHARGE
where
The output turns on when the bias capacitor reaches 12V (a). During a short-circuit fault, the bias
capacitor continually charges and discharges until you remove the fault (b).
VTHRESHOLD =
VULVO VOUT
.
VCC
design
Edited by Bill Travis and Anne Watson Swager
ideas
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design
ideas
VH
TEMPERATURE SET
VH
Figure 2
12V
10k*
V2
LM399
15V
5k
+F
+S
2.49k*
6.95V
FINE COARSE
0.1 mF
2
3 1
1.0k*
D1
CRYOSENSOR
HEAT
~15V
IC1A
5k
150k*
1
2k*
1M
1M
1.0k*
1M*
0.01 mF
2
8
10
1
IC1C
LT1004-2.5
2F
75k
0.01 mF
2
5
1
33k
IC1B
VH
+
1
3W
Q1
2N5087
0.001 mF
49.9k*
49.9k*
4.7-mF
METALLIZED
FILM
RESET
249k*
LF412
4
IC3A
100k*
GAIN
0.1 mF
2S 1.0k*
14k*
THERMAL
COUPLING
11
13 IC1D
14
2
12
1
2
1
80 mA TO 1.7A
100 mF
AT 35V
8.45k*
8.45k*
I1
0.01 mF
Q2
0 TO 1.7A=0 TO 45W
TIP
127
3.3k
6
2
1 5
12
IC3B
11
1C4D
VH
28V AT 2A MAXIMUM
+
VH
RETURN
IN 7815 OUT
T
100 mF AT 35V
+
GND
9 8 IC4C
6
10
15V
100 mF
AT 16V
SQUAREROOTER
FUNCTION
14
1C4E
13
11.3k*
7
5+1
4+2
1C4A,B
1 mA
(IREF)
12
3
CA3146
The logarithmic response of transistors IC4A through IC4C results in a square-root function for the heater-control voltage.
design
ideas
LISTING 1RS-232 TRANSMISSION-RATE-DETECTION ROUTINE
incoming bit stream and calculate the average time to receive 1 bit. This implementation of an autobaud routine assumes that the receiver knows the bit
sequence of the calibration value and that
the receiver knows when to calibrate. The
technique uses a PIC16C54B mC. The mC
connects to a PC via a MAX232 chip. The
PC sends the calibration character to the
mC. We chose the ASCII value of ? because of the bit sequence (00111111).
The autobaud routine measures the time
to receive the ones in the bit stream and
then divides the time by six. The result is
the time the routine takes to receive or
transmit 1 bit.
Because the PIC16C54B has no hardware USART, a software routine measures the timing of the bit sequence. Listing 1 gives the source code of the
autobaud routine. The calibration char-
design
ideas
six. Dividing by six entails shifting the 16bit counter/register three times to the
right while drawing zeros from the left.
After the division, the routine divides the
bit time by two, to calculate the transmission of half a bit. This time figure
serves in the receive routine to place the
bit sampling in the middle of a bit. The
division by two entails a simple shift of
the 16-bit counter by one position to the
left. The program stores the results of this
operation in two registers: AUTOHALF_LOW and AUTOHALF_HIGH.
Once the program completes this calculation, its necessary to adjust the transmission time of 1.5 bits to the software
overhead. This adjustment involves subtracting the number of instruction cycles
it takes to execute either the transmit or
the receive routine. After the subtraction,
the software verifies whether the result is
smaller than zero. If so, the incoming signal is too fast, and the routine sets an error flag in the AUTOB_STATUS register.
After the adjustment, the software verifies whether the incoming signal is too
fast by verifying that the value of the 16bit counter is zero. If the incoming signal is not too fast, the autobaud routine
returns to the operating system. Listing
1 is available for downloading from
EDNs Web site, www.ednmag.com.
Click on Search Databases and then enter the Software Center to download the
file for Design Idea 2418. (DI #2418).
2N3810
100k
100k
Q5
Q4
Q3
2N2222
VSUPPLY
12V
Q1
VOUT
Q2
102
1N3600
2N2060
R1
200
200
RS , 5
I
CURRENT TO BE SENSED
(b)
100
200
300
400
500
IRS5IEQ3R1.
Therefore, Q3s emitter
delivers a current propor-
A simple current sensor (a) can measure currents of 0 to 500A with a logarithmic output (b).
design
ideas
Figure 2
Q1
MBRS5206L
5V IN
R2
10k
R4
5.9
2 _
IC2A
LT1490
1
2
1
3
RESET
VCC
ON
SENSE
3 TIMER
GATE
C4
0.33 mF
IC1
GND
LTC1422
FB
D3
R1
0.03
MBR1060
C1
0.01 mF
R3
5.1
7
6
5
C3
0.1 mF
5V PRECHARGE
DRIVE 1
D1
1N4148
D4
5V PRECHARGE
DRIVE 2
MBR1060
5V PRECHARGE
D5
DRIVE 3
MBR1060
6 _
R5
1k
C6
0.1 mF
C5
0.1 mF
8
4
D2
1N4148
C2
0.1 mF
IC2B
LT1490
GND
A hot-swap-controller IC and a comparator provide a controlled ramp-up of the MOSFETs gate voltage and, consequently, the output voltage.
www.ednmag.com
design
ideas
Figure 1
6V
0.1 mF
47
6V
R1
15k
MOD IN 3VP-P
300 TO
3000 Hz
1k
SHIELD
C1
0.1 mF
A
1
2 IC1
R
R2
20k
CA
R3
47k
C2 +
10 mF
CB
CC
CD
CE
CF
3 8
1
+
2
4
2
5
CA
6
R
CA
CB
CC
CD
CE
A
B
C
D
E
F
NOTES:
UNLESS OTHERWISE NOTED, ALL RESISTORS=121k, 1%.
CA=4.7 nF, CB=3.3 nF, CC=2 nF, CD=1 nF,
CE=560 pF, CF=470 pF; ALL ARE CERAMIC OR
STACKED FILM 2%.
IC1 AND IC2=MC33182.
1
2 IC2
1 mF
5%
FILM
7
6V
8
7
100
Q1
6V
8
1
1
1
2 IC2
1 mF
16
MAX4528
IC3
200
6V
14
11
7
15
2
10k
0.1
mF
10k
T2
200 pF
IC3
470
2N3904
1 mF
SIDEBAND
SELECT
SSB
OUT
T1, SAME AS T2
3 I
VCC
4
EN
I
MAX2452
IC4
5
Q
GND
6
Q
1 mF
CF
3
+
2
2
100
0.01 mF
2.7k
+
2
+
6 2
MPSH10
100
1
2 IC1
CA
2N3904
R4
10k
6V
An RC network, three ICs, and a handful of discrete components provide an efficient SSB modulator for the HF band.
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design
ideas
VOUT5 (VIN2VCOM)LPF1VOS,
5V
VCC
SHDN
IN
OS
CLOCK
MAX7410
CLK
OUT
COM
GND
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02158
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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design
ideas
Figure 1
DQ
TO PC
PARALLEL
PORT
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
IC1D
SDin
SDlk
47 pF
1k
CLK
6
1k
1k
RST
IC1A
1
10
DCEN
CLR
REFOUT
REFIN
IC1B
3
SD_IN
SCLK
IC1C
RFOS
IC2
SYN
Sync
VOUT
LDAC
VDD
2
1
13
OUTPUT A
14
16
12V
Ldac
15
11
12
100 nF
47 pF
6
SD_IN
10
DCEN
CLR
REFOUT
REFIN
SYN
RFOS
IC3
VOUT
VDD
LDAC
2
1
13
OUTPUT B
14
16
12V
12
100 nF
5V
IC1F
13
15
IC1E
12 11
10
12V
1N4148
3 V
I
16V
WALL
ADAPTER
78L12ACZ
100 mF +
25V
VO
GND
2
100 nF
5V
78L05ACZ
3 V
I
VO
GND
VCC
OF IC1
100 nF
100 nF
0V
GROUND
OF IC1
NOTES:
IC1=74HC14.
IC2, IC3=AD7243.
Comparator exhibits
temporary hysteresis ..................................160
Two 12-bit DACs provide two PC-controlled reference voltages.
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design
ideas
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design
ideas
plified by 16 with four 0 MSBs. The amplification gives this channel the resolution necessary for small-error signals
while the robot is traveling a nearly
straight line.
The controller first reads the second
channel and checks for overflow. If no
overflow occurs, the result is the reading
plus four zeros for the MSB. If an overflow occurs, the controller discards this
first reading and proceeds to read the first
channel.
The controller can perform amplifieroffset correction any time the signal is in
the small-signal realm by reading both
channels, shifting 4 bits, and subtracting.
In most cases, this correction is unnecessary. (DI #2415)
To Vote For This Design,
Circle No. 318
VOUT1
TO UNIT
UNDER TEST
VOUT2
PE
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design
ideas
D1
1N4007
Figure 1
RA1
10k
D2
1N4148
R1
220
D3
1N4148
RX1
470k
+
2
VIN
C1
4700 mF
1
2
10M
CA1
1 mF
CX1
100 nF
D4
1N4148
Q1
IRF530
CX
RXCX
IC1A
CD4538
TR+
5
TR2
220 nF
Q
RESET
D5
1N4148
RX2
470k
15
CX
14
RXCX
12
CX2
100 nF
11
TO
SOLENOID
IC1B
CD4538
TR+
TR2
10
9
Q2
IRF530
RESET
13
This circuit can drive a latching solenoid valve over a 1-km distance.
www.ednmag.com
design
ideas
10 mH
22 mF
Figure 1
100k
MBR0520L
3V `
CLK/SEL
ONB
POUT
TRACK
5V 600 mA
OUT
ONA
GND
0.1 mF
IC1
MAX1705
+
165k
FB
REF
3.3 V
200 mA
400k
220 mF
22 mF
100k
LBP
`
0.33 mF
100k
LBN
LBO
50k
LDO
PGND
FBLDO
68k
22k
22 mH
2 TO 5V
AC
AC/DC
RECTIFIER
1N5817
MMFT
3055ELT
68 mF
SHDN
355k
100 mF
EXT
REF
150k
CS
IC2
MAX608
0.05
FB
0.1 mF
OUT
AGND
GND
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design
ideas
12V
Figure 1
R1
500
FERRITE
BEAD
4.7
12
180
1 nF
33k
510
7
1
1 nF
10 nF
~34V
C1
330 pF
C2
10 nF
1.24k
2
FERRITE
BEAD
C3
1.8 pF
FERRITE
BEAD
TL497
75
1 nF
FERRITE
BEAD
1 nF
FERRITE
BEAD
14 13 10
100 mF
12
120
10 mH
1 nF
12
78L05
C6
10 nF
R2
82.4
OUTPUT
1.24k
100 mF
470 mF
35V
MAR6
24V
MAR3
C4
1.8 pF
C5
47 pF
ERA5
180 pF
A 24V zener diode and a series of MMIC amplifiers create a broadband noise source.
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design
ideas
NORMALIZED FREQUENCY
(31023)
The probability-density function has a Gaussian shape, and the calculated rms value is 192.1 mV.
The calculated rms value from the histogram differs slightly from the powermeasurement value; this difference stems
from the limited bandwidth of the sampling gate used to acquire the samples.
To achieve a flat power-density spectrum of the noise in the low-frequency
region, some spectrum whitening is necessary because of the existence of 1/f-type
noise. This circuit achieves the necessary
frequency shape of the amplifier gain using properly chosen values of coupling
capacitors between amplifier stagesC1,
C2, and C6and by using a correcting
network before the last stageC3, C4, C5,
and R2. The values of all frequency-shaping components were chosen experimentally while observing the power-density spectrum on the analyzer screen.
To obtain good performance from the
circuit, you must obey all RF design rules.
In particular, keep the pins of the zener
diode as short as possible and locate all
decoupling capacitors near the MMIC
amplifiers. Screening the entire circuit is
also recommended. (DI #2406)
VCC
R2
1.6k
LM301
1
VOUT
R1
8.2k
C1
0.01 mF
drawback of this method is that the resulting hysteresis produces an offset thats
a function of the state of the comparator. With an asymmetric output, the offset of the comparators input is also
asymmetric. The result is asymmetry in
Replacing a resistor by a capacitor eliminates
asymmetry by providing temporary hysteresis.
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design
ideas
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design
ideas
8
7
6
UC384X
LM393
100k
FROM SECONDARY
CIRCUIT
1
100k
10 nF
MPSA2907
er operation, the voltage on Pin 1 is higher than the level imposed by the 100-kV
potentiometers wiper, and the UC384X
operates in its normal mode. When the
load disappears, the voltage on Pin 1
drops to reduce the primary peak-current setpoint. If you adjust the potentiometer for a given peak level, the only
way to further reduce the power is to stop
the output pulses. The comparator, deriving its power from the UC384Xs internal reference, biases the pnp transistor
and brings the current-sense pin to the
22k
1
(b)
UC384X
The classic arrangement in (a) reduces no-load standby power; the addition of a comparator (b)
cuts the standby power by 50%.
November 11, 1999 | edn 169
design
ideas
INVERTER OR
GENERATOR
OUTPUT
INVERTER OR
GENERATOR
CONTROL
DC SOURCE
THRESHOLD
AMPLIFIER
1
1
GALVANIC
ISOLATION
AND LOWPASS
FILTER
LOADS
www.ednmag.com
design
ideas
an ohmmeter that monitors the generator resistance of the generator or inverter output. Usually, the output comes
from a motor coil or a transformer winding having low resistance. The circuit in
Figure 1 can detect any load whose resistance is lower than 15 kV. When no
load exists, the voltage at the amplifier input (the generators voltage minus the
diode-junction voltage) does not exceed
the threshold, so the relay does not engage.
When one or more loads connect to
the circuit, the voltage at the amplifier input exceeds the threshold, actuating the
R1
Figure 2
rent flows through the output coil (inverter or generator transformer). The
high-voltage section of the circuit is galvanically isolated via the dc/dc converter and the optocoupler. An RC lowpass
filter delays the relays actuation; it takes
approximately 1 sec for the relay to engage after connecting the load and 2 sec
to disengage after disconnecting the load.
(DI #2435)
relay and starting the generator or inverter. When the ac load current flows
through the circuit, it keeps the relay engaged. When the load disconnects, the relay disengages. In operating a generator,
you should wire the system to start the
generator when no line power exists and
when the load requires power. Figure 2
shows a complete schematic. In the noload case, the voltage source (R1, R2, D1,
and D2) cannot forward-bias Q1s baseemitter junction, because of the voltage
drop across D3, D4, and D5. The junction
becomes forward-biased when a load
connects to the inverter, and the load cur-
R2
100
1k
D3
D1
D4
D2
1k
LINE
SENSE
50k
D5
10k
Q1
1M
1M
1M
1 mF
1k
VCC
LM7805
VIN
24 TO 12V
DC/DC CONVERTER
OUT
UPS
START/STOP
2
RELAY
VOUT
GND
+
100 mF
100 mF
24V INVERTER
BATTERY
+
2N2222
1k
DIGITAL
CONTROL
IN
OUT
1k
This galvanically isolated generator-control circuit turns on the emergency generator only when the load demands it.
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design
ideas
Figure 2
SLAVE ADDRESS BYTE
COMMAND BYTE
OUTPUT BYTE
SDA
MSB
LSB
ACK
MSB
LSB
ACK
MSB
LSB
ACK
SCL
STOP CONDITION
START CONDITION
This diagram shows the I2C timing protocol for the MAX517 D/A converter.
www.ednmag.com
design
ideas
Figure 2
(a)
(b)
A highly capacitive power supply causes a 4A current surge (a) in the power line; an incandescent bulb produces a 1.5A spike (b).
www.ednmag.com
design
ideas
put of the dc/dc converter and the output side of the ISO122P. The filtered output of the ISO122P provides the input to
a DSO. You use transient-capture mode
in the DSO to capture the power-on current surge. Figure 2 shows the waveforms
for:
A system with a 10,000-mF transformer/bridge-capacitor filter (Figure 2a). Steady-state rms current is
approximately 0.13A at 220V rms.
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design
ideas
VOUT
5V
V0
G
= 0 C .
VS j + C
R1
SCL
SDA
15V
CONTROL
AND
MEMORY
k2R2 (11k2R2)
ADDR
R1 + R 2
, and 0 k 2 1,
R1 + k 2 R 2
X9418W
15V
where k2 reflects the proportionate position of the wiper from one end of the po- Replacing Figure 1s potentiometer with digitally programmable potentiometers allows you digitaltentiometer (0) to the other end (1). The ly to control gain and cutoff frequency.
gain is programmable from 1 to
5V
(R11R2)/R1. The fixed resistor, R1,
10k
LT1220
RHIGH
RLOW
Figure 3
limits the circuits maximum volt3 +
7
5V
6
age gain, a limitation usually necessary
VOUT
W
2 1
4
for accuracy and bandwidth purposes.
R5
The upper cutoff frequency fC is a funcR4
15V
5k, 1%
R2 W 10k
5k, 1%
5V
tion of the input RC network:
300 pF
1
fC = C =
, and 0 k1 1.
2 2 (k1R)C
R3
1k, 1%
R1
910, 1%
SCL
SDA
where k1, like k2, reflects the proportionate position of the wiper from one end
of the potentiometer (0) to the other end
(1). The dual versions of the XDCP digital potentiometers use the same serial
bus with different addresses for the individual potentiometers.
HIGH LOW
CONTROL
AND
MEMORY
ADDR
R1
X9418W
15V
You can use the same serial bus to control both the gain and the cutoff-frequency potentiometers
in an amplifier circuit.
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ideas
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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ideas
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design
ideas
T1
VIN
5V
R1
51
+
1 nF
470 mF
35V
SANYO
MV-GX
1500 mF
6.3V
SANYO
MV-GX
Figure 1
VOUT
248V/0.5A
470 mF
35V
SANYO
MV-GX
MBRS340T3
BAV21
T2
0.82
15
10 mF
+
8
VIN
S2
D1
1N5235B
6.8V
+ 4.7 mF
30V
FILM
1 mF
Q2
ZTX649
T2
7
BOOST
TG
ITH/RUN
GND VFB
SW
220 pF
12k
Q4
2N5210
+
0.022 mF
30
Q3
ZTX749
1M
36k
4.7 mF
30V
FILM
MBRS340T3
Q1
IRL3705N
LTC1624
2.2 nF
C1
Q5
2N5210
10.5k
1%
NOTES:
T1=COILTRONIC CTX02-14261.
EFD20; SIX WINDINGS, EACH 12 mH.
T2=DALE LPE3325-A087EES CORE; 1 TO 70, LS=980 mH.
RESISTORS= 41 W, 5%.
248V
This circuit uses numerous tricks to boost efficiency to more than 85% in converting 5V to 148V.
www.ednmag.com
design
ideas
formance. The LTC1624s Boost pin normally provides the internal output driver (the TG pin) with a 5.6V regulated
supply, but TG produces only 4.2V with
a 5V input. Bypassing the internal regulator by connecting the Boost and VIN
pins increases Q1s gate voltage, resulting
in a gain of more than 3.2% in overall efficiency. R1 and D1 keep the Boost pin be-
low its 7.8V rating in the event of an input overvoltage condition. The addition
of Q2 and Q3 provides an additional 5.5%
of efficiency by speeding transitions and
increasing gate voltage from 5 to 5.3V.
This voltage peaking results from excess
emitter current as Q2 turns off after
charging Q1s gate capacitance. Q4 and Q5
translate the 248V output to the 1.2V
equivalent. The function performs the TABLE 1SECONDS TO CONVERT 100 MILLION INTEGERS
Irix (SGI Indy R5000)
Linux (PIII/500)
conversion through a
gcc
gcc-03
gcc
gcc-03
sequence of left shifts
476
160
80
28
and sums. To com- fast_d2b
9377
8542
2206
1672
pare the perform- classicC
ance of fast_d2b with
the function classicC, we ran several tests than classicC. You can download Listing
on two platforms, both running Unix- 1 from EDNs Web site. At the registeredlike OSs. We used the GNU C compiler user area, go into the Software Center
(gcc) with and without turning on ag- and download the file from DI-SIG
gressive optimization (the O3 flag). #2444. (DI #2443).
Table 1 shows the time to convert the first
100 million integers. The Unix time
To Vote For This Design,
command produces the running-time
Circle No. 452
figure. Fast_d2b is 20 to 58 times faster
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design
ideas
Resistor implements
half-duplex RS-232 with echo
Matt Bennett, Austin, TX
previous Design Idea (Single mC
pin makes half-duplex RSFigure 1
232, EDN, Aug 5, 1999, pg
1
118) presented a way to implement halfC1`
2
V`
duplex RS-232 communications without
C11 3
6
1
echo. Sometimes, an echo is desirable in
V1
RA2/AIN2
RA1/AIN1 18
4
C2`
a mC application.You can obtain the echo
2
RA3/AIN3
RA0/AIN0 17
5
by using a single resistor (Figure 1). You
C21
3
IC2
RA4/TOCKI
OSC1 16
insert a 5.1-kV resistor between the
MAX232
IC1
4
15
MCLR
OSC2
transmit and receive pins on the RS-232
14
PIC16C71
T1IN 11
T1OUT
5
VSS
VDD 14
driver (such as a MAX232). The I/O pin
10
7
T2IN
T2OUT
12
13
on the mC (RB0 on 14-bit PIC mCs) con6
RB0/INT
RB7 13
R1IN
R1OUT
9
8
nects directly to the transmit gate on the
5.1k
R2OUT
R2IN
12
7
RB1
RB6
RS-232 driver. This technique is useful
11
8
RB2
RB5
for implementing a user interface on a
10
9
RB3
RB4
Microchip PIC for applications in which
you communicate to the PIC via a terminal or a terminal-emulation program. The addition of a single resistor provides an echo in RS-232 half-duplex communications.
Full duplex is unnecessary with a user interface based on user-issued commands input. All RS-232 data sent to the mC is through the resistor and the mCs driver.
and mC responses, when the mC gener- immediately retransmitted via the resis- The mC ignores data sent to it. The mC
ates no spontaneous data that would tor that connects the receiver to the trans- now directly sends data down the serial
mask the user-issued commands. The mitter. Because the input has high im- line. The mC must immediately change
character echo is useful in determining pedance, the mC is essentially just the serial line back to high-impedance
whether the device is powered up and the monitoring the traffic on the RS-232 line. mode after transmitting or risk data loss.
RS-232 receiver is active, but an echo When the mC must send serial informa- (DI #2445).
alone does not tell you whether the mC tion, the mC converts its I/O pin to a lowis active; the mC must send data.
impedance driver. Anything now sent to
To Vote For This Design,
When the mC is in receive mode, it the mC shunts to ground or VCC (deCircle No. 453
makes the input pin a high-impedance pending on the mCs output state)
provides long battery life in this application. The optocoupler consists of a neon
lamp and a photocell. When the ac-power system is active, the neon lamp lights
via current-limiting resistor R1. A neon
lamp is ideal for this application because
of its low power drain. The resistance of
the photocell in the optocoupler is low
when the cell is illuminated and high
when its unilluminated. R2 serves as a
design
ideas
S1
Figure 1
9V
R1
220k
R3
1M
R2
1M
1
14
3
IC1A
C1
0.1 mF
IC1
4093
R4
1k
2
120V AC
IC1B
D1
1N4001
8
Q1
2N2222
IC1C
10
9
12
13
11
IC1D
OPTO 1
SIGMA 30 1T 1-150A 1
S1
9V
This circuit sets a flag or triggers a visual alarm when the ac-power line fails.
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design
ideas
nels from 902.72 to 906.62 MHz in 260kHz steps. R4 and C4 form a lowpass filter with corner frequency set to a value
substantially lower than the internal reference frequency of the synthesizer or the
data stream, whichever is lower. As with
any RF design, you should give careful
consideration to parts placement and
shielding. You should also apply generous decoupling. If desired, you can hold
Pin 17 of IC3 at logic zero for low-power-disabled operation. (DI #2429).
Figure 2
CLK
1A1
1Y1
4 1A2
1Y2
6
1A3
1Y3
10
1A4
IC2
1Y4
74HC368
12
2A1
2Y1
14
2A2
2Y2
1
1G
15
2G
VCC
10
4
DATA
3
1
2
PR
11
IC1A
74HC112
CLK
13
CL
PR
IC1B
74HC112
CLK
12 K
5
7
9
VCC
11
R1
1k
13
R2
1k
CL
14
R4, 10k
+
C6 +
D1
+
C1
2700 pF
R8
27 pF
0.5 pF
R3, 10k
C4
0.1
C5
15 pF
D2
9
2.7 pF
11
L1
1.8 nF
R3, 270 5
1000 pF
100 pF
C9
22
27 pF
2.2 pF
R4, 39k
C2
26
Y1
2.048 MHz
C16
OSC0
28
LD
10
FV
9
PV
T/R
21
10 nF
VCC
16
17
RF+
VCC
VCC
OSCC
VCC
51
OSCE
2.7 pF
12
27 pF
MMBV809LT1
RF2
OSCB
IC3
MC13146
100 pF
ANTENNA
MIX/BUF_IN
200
LINADJ
PA_OUT
PA_IN
C3
2.2 pF
MC
EN
L2
3.3 nF
PRSCOUT
CF1
CF6118702
1
3
2
1000 pF
PR
PD
N0 N1 N2 N3
11
12
13
14
IC4
MC145151
N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 FIN
15 16 17 18 19 20 24
25
22 23
27 pF
VCC
S1
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design
ideas
Figure 1
COILCRAFT
VP2-0216
1:5
VIN
10 TO 25V
FMMT619
1k
+
22 mF, 35V
AVX TPS
6
10 mH
VOUT
7
MURS160
3
8.2V, 4 W
100V AT 50 mA
MAXIMUM
100k
Si4480
MBRS1100
10 mF, 16V
CERAMIC
100k
MBR0520
10
+
1 mF
CERAMIC
6
VIN
1
560 pF
6800 pF
VC
100k
5
825k
1%
SW
IC1
LT1308
FB
GND
+
100k
SANYO CV-GX
ALUMINUM
ELECTROLYTIC
10.5k
1%
4
47k
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
Design Idea Title
ZIP
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ideas
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design
ideas
A0
24
IC2
A1 MAX158 CH1
23
CH2
A2
CH3
Figure 1
3
D0
D1
D2
P1
5
7
9
D3
1
A0
14
A1
15
D_Rdy
P_S1ct1
16
A2
17
N_S1ct
D4 12
D5 14
D6 16
D7 18
19
2G
2Y4
2Y3
IC1
1G
2Y2 74LS244
2A4
2Y1
2A3
1Y4
2A2
1Y3
2A1
1Y2
1A4
1Y1
CH4
1A3
1A2
1A1
CH5
17
15
13
11
8
6
10
4
2
21
11
19
20
22
DATA_LOW
DATA_HIGH
74LS32
9
8
10
13
12
18
CH6
D0
D1
CH7
D2
CH8
6
5
4
3
INPUT
CHANNELS
ONE TO
EIGHT
2
1
28
27
VCC (5V)
D3
D4
D5
VDD
26
VREF+
16
D6
D7
C1
47 mF
16V
C2
0.1 mF
INT
VREF2 15
RD
CS
GND
14
CONNECTOR DB25
74LS04
P_S1ct2
10
D6, D2
11
D7, D3
74LS32
11
4 13
12
D_RDY
74LS32
5
4
74LS04
1
74LS32
3
ADC_S1ct
24
12
D5 , D1
25
13
D 4, D 0
Only five input lines to the printer port are available, so the 8-bit data transfer from the ADC to the PC occurs in two nibbles from IC1, under the control of the N_Slct signal from the PC.
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design
ideas
Figure 1
IIN
5V
5V
1 mF
100 mA
0.01
10k
100 mA
VDD
REF200
(BURR-BROWN)
I/O
AIN1+
ADC
AIN12
I/O
IOUT
GND
A simple current source and a matched resistor set provide the necessary offset to bring the voltage within the ADCs common-mode range.
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design
ideas
Figure 1
2
200k
4
200k
GYRO
(TOKIN_CD_16C1)
10k
4.7 mF
V+/2
IC1B
LT1495
+
R1
1M
C1
4.7 mF
100k
+
IC2B
LT1368
6
2
1
2.2 mF
0.01 mF
4.99k
4.99k
2
IC1A
LT1495
+
2
3
V/2
3
0.01 mF
GYRO_AMP_OUT
0.1 mF
+
IC2A
LT1368
2
1
0.1 mF
Servo amplifier IC1A removes the dc level shift due to temperature-related drift effects of a piezoelectric-rate gyro.
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design
ideas
Si4501DY MOSFET in this topology exhibits less than a 0.1V drop at 5A for the
main element and contains both MOSFETs in an SO-8 package.
When the 2N7002 or similar control
MOSFET ties the gates together and pulls
them to ground, the p-channel MOSFET
is on. Pulling the gates above the supply
rail by turning the 2N7002 off results in
design
ideas
circuit. However, due to the fast switching of the MOSFETs, extra caFigure 1
pacitance beyond normal design
rules is probably unnecessary to maintain the operating voltage.
The arrangement of the n-channel device in the circuit ensures that the internal diode does not conduct while the
subcircuit is isolated. In this direction,
the n-channel MOSFET also provides a
fail-safe path for the circuits power
through the diode. The forward voltage
of the p-channel MOSFETs diode blocks
any current from back-feeding the secondary supply, assuming that the two
supplies are close in voltage.
An example of an application for this
circuit is the Advanced Configuration
and Power Interface in desktop computers providing instant-on and low power
consumption in standby. The main power supply is a high-power switching power supply, and the secondary supply is a
60-Hz transformer with linear regulation. (DI #2451)
12V
Si4500DY OR Si4501DY
MAIN
SUPPLY
SECONDARY
SUPPLY
LOAD
CONTROL
2N7002
(a)
ALWAYS-ON
SUPPLY
MAIN
SUPPLY
ALWAYS-ON
CIRCUIT
CONTROL
MAIN
CIRCUIT
(b)
R1
V+
IM (R M + R S ) = IMR S
.
R1 + R 2 R 3 200 A
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design
ideas
10 TO 60V
10 mF
TANTALUM
`
IC2
4.5 TO 36V
3
R5
1k
D2
D1
0 TO 200 mA
R1
1
IC1
OPA237
`
DC
MOTOR
EMF
DRV101
PWM
221N4148
Q1
2N7000
470k
10k
R2
15k
Reference
1. Burr-Brown Applications Bulletin
AB-152
To Vote For This Design,
Circle No. 308
IN40001
R3
1k
R4
10k
20 nF
RS
1
Positive feedback derived from current-sense resistor RS increases the duty-cycle drive from PWM
controller IC2 to compensate motor speed with varying loads.
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design
ideas
[ [ [ [[ [
V1
A C V2
=
I1
B D I2
I1
I2
B
V2
V1
C
where
A=
V1
V2
B=
I2=0
V2
I2
C=
V2=0
I1
V2
D=
I2=0
I2
I2
.
V2=0
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design
ideas
1,0 Z
0,0 1,0
1,0 0,0
1/Z 1,0 .
I1
3H
I2
V1
2F V2
1/2H
0,24
1,0
0,3
1,0
1,0 0,0
N4=
0,2 1,0
N1= 1,0
1/Z
[
;
N3= 1,0
0,0
N1z N2=
27,0 0,24
0,2 1,0
design
ideas
Figure 2
(a)
(b)
Series-string light sets come in two flavors: a continuous-series string (a) and an alternating-series string (b).
the input power divided by 10. The divide-by-10 operation keeps the voltage
within a manageable range. The output
is, then:
VOUT = VIN I /10 = 2.2
[DUTY _ CYCLE V
IN1
1 V
2 IN
].
To subtract the 1/2VIN term in the equation, the first op amp inverts the power
signal. The second op amp adds in the
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design
ideas
offset and again inverts the signal. Capacitors C1 and C2 provide filtering.
These capacitors connect back-to-back
to achieve nonpolar operation. Tests with
input currents of 27 to 17A and with a
source voltage of 2 to 5.25V showed bet-
J1
C3
C4
10 mF
10 mF
Figure 1
SUPPLY (2 to 5.5V)
J2
IC1
LM3812
1
2
RLOAD
C1
0.1 mF
C2
0.1 mF
SENSE 6VDD
GND
SENSE 1
GND 7
FILTER +
FILTER 1
PWM
SD
6
5
R4
R2
R5
400k
110k
5V
5V
R1
IC2A
1
110k
220K
LM412
R3
200k
IC2B
+
LM412
25V
J3
VOUT
_ 5V
design
ideas
rupts. Because the timer interrupt period differs for every note, the number of
Timer0 interrupts differs for every note.
A table called Durations in the source
code contains the note duration for the
corresponding note in the Notes table.
On each Timer0 interrupt, the Notes value loads into TMR0 and the note duration decrements. At the end of each note,
a pause of 1/64 occurs to emphasize the
note you are playing. The routine creates
the pause by not toggling the output pin
during the pause interrupts. Again, each
note requires a different number of interrupts to generate a pause of a set duration. To simplify the pause generation,
the program subtracts the number of interrupts required for a pause from each
note duration. The routine creates the
pause by setting the timer such that the
pause occurs from one timer interrupt. If
the clock frequency is such that you cannot create the pause with one interrupt,
you can alter the value STOP_LENGTH
in the source code. The program loads
the next note to play after the pause interrupt. A 0 in the Notes and Durations
tables in the source code denotes the end
of the song. At this point, the program
plays the song again.
Using internal memory to store the
notes and durations has some limitations. Without some extra table-handling
code, tables are limited to 255 elements
and must start on a 256-byte boundary.
Because the duration values are 16 bits
long, the number of notes the PIC mC
can play is 127. Depending on the size of
program memory, you can place many
songs in 256-byte blocks and play them
individually. By using two more I/O pins
(SCL and SDA), the PIC mC can interface
to an external serial EEPROM and play
any number of notes up to the maximum
memory size divided by 3. A 24LC01B
from Microchip Technology can hold
341 notes plus corresponding durations.
(DI #2456)
To Vote For This Design,
Circle No. 429
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design
ideas
fers from a long turn-on time and a limit on the capacitive load into which the
converter starts up. Another popular approach uses a transistor-based pass regulator, often in conjunction with an overwinding to keep power dissipation low in
normal run conditions. Although this
method can provide a fast start-up, it
generally exhibits high power dissipation
during an output short circuit. Attempts
to gate this type of circuit can be messy
and complicated. A buck regulator overcomes the disadvantages but can be complex and costly. The circuit in Figure 1
uses IC1, an LT1431 shunt regulator, lowcost transistors, and an off-the-shelf in-
design
ideas
ply power. Q2 and Q4 provide short-circuit protection; thus, the design is robust. Short-circuit current is typically
L1
36 TO 72V DC
11V
VIN
Figure 1
R1
1k
D03316P-105
COILCRAFT
Q1
MMBTA56
R10
4.7
VOUT
AT 50 mA
Q2
MMBTA56
Q4
MMBTA06
C1
12 mF
100V
R2
10k
R3
100k
R4
1k
R5
20k
COLL
IC1
LT1431
GND-F
C2
0.01 mF
V+
REF
GND-S
Q3
MMBTA06
R8
16.2k
R7
47k
R6
10
C3
10 mF
25V
R9
4.75k
D1
BAS21
A shunt-regulator IC and a handful of low-cost components form an efficient, robust bias supply.
design
ideas
Figure 1
SETUP DATA
FROM PC
UART (RX)
0 1 2 3 4 5 6 7
NC
LOAD
RUN
+
DATA
FPGA
+
DATA
LOAD DATA
CLOCK
RUN CLOCK
LOAD CLOCK
n-BIT MAGNITUDE
COMPARATOR
A<B
ERROR-FREE DATA
DATA CLOCK
Using a PC and an FPGA, you can generate any percentage of random errors in a data stream.
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