This document discusses the design and implementation of a low dropout voltage regulator with an on-chip capacitor. It provides background on the increasing demand for low voltage, low dropout regulators in portable electronics due to their higher efficiency. Conventional LDO regulators require an external capacitor for stability, but removing this increases integration. The document outlines challenges in stabilizing and providing fast transient response for a capacitor-less LDO regulator. It proposes revisiting the basic capacitor-less LDO topology to address these issues and realizes the goal of an on-chip capacitor LDO design.
This document discusses the design and implementation of a low dropout voltage regulator with an on-chip capacitor. It provides background on the increasing demand for low voltage, low dropout regulators in portable electronics due to their higher efficiency. Conventional LDO regulators require an external capacitor for stability, but removing this increases integration. The document outlines challenges in stabilizing and providing fast transient response for a capacitor-less LDO regulator. It proposes revisiting the basic capacitor-less LDO topology to address these issues and realizes the goal of an on-chip capacitor LDO design.
This document discusses the design and implementation of a low dropout voltage regulator with an on-chip capacitor. It provides background on the increasing demand for low voltage, low dropout regulators in portable electronics due to their higher efficiency. Conventional LDO regulators require an external capacitor for stability, but removing this increases integration. The document outlines challenges in stabilizing and providing fast transient response for a capacitor-less LDO regulator. It proposes revisiting the basic capacitor-less LDO topology to address these issues and realizes the goal of an on-chip capacitor LDO design.
This document discusses the design and implementation of a low dropout voltage regulator with an on-chip capacitor. It provides background on the increasing demand for low voltage, low dropout regulators in portable electronics due to their higher efficiency. Conventional LDO regulators require an external capacitor for stability, but removing this increases integration. The document outlines challenges in stabilizing and providing fast transient response for a capacitor-less LDO regulator. It proposes revisiting the basic capacitor-less LDO topology to address these issues and realizes the goal of an on-chip capacitor LDO design.
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Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
VLSI DESIGN AND EMBEDDED SYSTEMS, SCE Page 1
CHAPTER 1
INTRODUCTION
The demand for low-voltage, low drop-out (LDO) regulators are increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDOs are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life.
The low drop-out nature of the regulator makes it appropriate for use in many applications, namely, automotive, portable, industrial, and medical applications. The automotive industry requires low drop-out (LDO) regulators to power up digital circuits, especially during cold-crank conditions where the battery voltage can be below 6 V. The increasing demand, however, is especially apparent in mobile battery operated products, such as cellular phones, pagers, camera recorders, and laptops. In a cellular phone, for instance, switching regulators are used to boost up the voltage but LDOs are cascaded in series to suppress the inherent noise associated with switchers. LDOs benefit from working with low input voltages because power consumption is minimized accordingly, P = I load * V in .
Low voltage and low quiescent current are intrinsic circuit characteristics for increased battery efficiency and longevity. Low voltage operation is also a consequence of process technology. This is because isolation barriers decrease as the component densities per unit area increase, thereby exhibiting lower breakdown voltages.Therefore, low power and finer lithography require regulators to operate at low voltages, produce precise output voltages, and have characteristically lower quiescent current flow. By the year 2004, the power supply voltage is expected to be as low as 0.9 V in 0.14m technologies. Drop-out voltages also need to be minimized to maximize dynamic range within a given power supply voltage. This is because the Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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signal-to-noise ratio typically decreases as the power supply voltages decrease while noise remains constant. Lastly, financial considerations also require that these circuits be realized in relatively simple processes.
Industry is pushing towards complete System-on-Chip (SOC) design solutions that include power management. The study of power management techniques has increased spectacularly within the last few years corresponding to a vast increase in the use of portable, handheld battery operated devices. Power management seeks to improve the devices power efficiency resulting in prolonged battery life and operating time for the device. A power management system contains several subsystems including linear regulators, switching regulators, and control logic. The control logic changes the attributes of each subsystem; turning the outputs on and off as well as changing the output voltage levels, to optimize the power consumption of the device.
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CHAPTER 2 CONVENTIONAL LDO
The conventional LDO voltage regulator, for stability requirements, requires a relatively large output capacitor in the microfarad range. Large microfarad capacitors cannot be realized in current design technologies, thus each LDO regulator needs an external pin for a board mounted output capacitor. To overcome this issue, a capacitor less LDO has been proposed in that topology is, however, unstable at low currents making it unattractive for real applications (figure.1). Removing the large off-chip output capacitor also reduces the board real estate and the overall cost of the design and makes it suitable for SoC designs.
Fig 1 Conventional LDO voltage regulator.
Most of the conventional LDO performances are greatly affected when the external capacitor is reduced by several orders of magnitude. The absence of a large external output capacitor presents several design challenges both for ac stability and load transient response. Conventional LDO regulators use a large external capacitor to create the dominant pole and to provide an instantaneous charge source during fast load transients. Thus, a capacitor-less LDO requires an internal fast transient path to compensate for the absence of the large external capacitor. To realize the task at hand, the basic capacitor-less LDO regulator, is revisited in the following section. One of the most significant side effects in LDOs is stability degradation due to the several poles embedded in the loop. As shown in Fig. 2(a), the uncompensated capacitor-less LDO has two major poles: the error amplifier output pole and the load dependent output pole. Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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Moreover, the power pMOS transistor in classical LDO must operate in saturation region due to the stability problem at different input voltages. The change in voltage gain due to different drainsource voltage is not substantial when the transistor operates in saturation region. However, if the transistor operates in linear region at dropout, the transistor will operate in saturation region instead as the input voltage increases. As mentioned previously, when the loop gain increases, the classical LDO based on dominant-pole compensation may be unstable. Therefore, the power pMOS transistor needs to operate in saturation region throughout the entire range of input voltage, so a large transistor size is required to provide a small saturation voltage at the maximum output current.
Fig 2. (a) Equivalent circuit of LDO voltage regulator and (b) Pole locations for uncompensated capacitor-less LDO voltage regulator; Cout around 100pF. Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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The specifications of the LDO can be classified into three classes: 1) static-state specification; 2) dynamic-state specification; and 3) high-frequency specification. Line and load regulations, as well as temperature coefficient, are regarded as static-state specifications, while line and load transient responses, as well as ripple rejection ratio, are dynamic-state specifications. The high-frequency specifications are PSRR and output noise. All specifications are correlated, and they have tradeoffs with the LDO stability when dominant-pole compensation with pole-zero cancellation is used. Line and load regulations are two important specifications that relate to the output-voltage accuracy. PSRR depends highly on both loop-gain bandwidth and ESR. An LDO with a good PSRR and line transient response results in a good ripple rejection ratio.
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CHAPTER 3 PROBLEM STATEMENT
Output current and input voltage range directly affect the characteristics of the pass element in the regulator, which defines the current requirements of the error amplifier. As the maximum load-current specification increases, the size of the pass device necessarily increases. Consequently, the amplifiers load capacitance, in Fig. 1, increases. This affects the circuits frequency performance by reducing the value of the parasitic pole present at the output of the amplifier. Therefore, phase-margin degrades and stability may be compromised unless the output impedance of the amplifier is reduced accordingly. As a result, more current in the buffer stage of the amplifier is required, be it a voltage follower or more complicated circuit architecture. In a similar manner, low input voltages require that MOS pass device structures increase in size and thus yield the same negative effects on frequency response and quiescent current as just described. This is because the gate drive decreases as the input voltages decrease, thereby demanding larger MOS pass elements to drive high output currents.
Further limits to low quiescent current arise from the transient requirements of the regulator, namely, the permissible output voltage variation in response to a maximum load current step swing. The output voltage variation is determined by the response time of the circuit, the specified load-current, and the output capacitor [3]. The worst case response time corresponds to the maximum output voltage variation. This time limitation is determined by the closed-loop bandwidth of the system and the output slew-rate current of the error amplifier [9]. These characteristic requirements become more difficult to realize as the size of the parasitic capacitor at the output of the amplifier increases, which results from low-voltage operation and/or increased output current specifications. Consequently, the quiescent current of the amplifiers gain stage is limited by a bandwidth minimum while the quiescent current of the amplifiers buffer stage is limited by the slew-rate current required to drive.
The classical LDO using dominant- pole compensation, a high loop gain and a wide loop bandwidth are critical for the improvement of LDO performance, but static power consumption and stability are tradeoffs. It is further illustrated that classical LDOs cannot be applied Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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effectively to system-on-chip designs due to the required large output capacitor for stability. Therefore, an advanced LDO structure with advanced frequency compensation, which solves the tradeoff problems of classical LDOs, should be implemented.
For stability requirements, LDO requires a relatively large output capacitor in the microfarad range. Large microfarad capacitors cannot be realized in current design technologies, thus each LDO regulator needs an external pin for a board mounted output capacitor. To overcome this issue, a capacitor less LDO has been proposed in that topology is, however, unstable at low currents making it unattractive for real applications. Removing the large off-chip output capacitor also reduces the board real estate and the overall cost of the design and makes it suitable for SoC designs.
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CHAPTER 4 LITERATURE SURVEY
Due to the emerging need of high-performance low-voltage LDOs for low-voltage mixed-signal systems, many researchers have recently proposed many advanced methods to improve the performance of LDOs. Rincon-Mora et al. proposed current-efficient voltage buffer, forward-biased power transistor, pole-zero doublets for load-regulation enhancement, and capacitance multiplication [3]. Heisley et al. proposed using a DMOS power transistor. Chevalerias et al. proposed using an nMOS power transistor with charge-pumped gate drive. The main aims of all the proposed methods are: 1) to enable low voltage regulation; 2) to reduce slew-rate limit at the gate drive; and 3) to improve load regulation and transient response. However, the precision of the above reveals the fact that there are limitations on the structure and frequency compensation scheme of classical.
The off-chip capacitor, which is the key for stability and high LDO performance, cannot be eliminated. This off-chip capacitor is the main obstacle to fully integrating LDOs in system- on-chip designs. As a result, low-voltage high-stability and fast-transient LDOs with, preferably, capacitor-free operation should be developed. Solving the correlated tradeoffs on stability, precision, and recovery speed is the main challenge of capacitor-free LDO design [5]. A CMOS LDO that is targeted for CMOS system-on-chip designs is presented in [1]. The circuit architecture is based on Capacitor-Less Low-Dropout Voltage Regulator a three-stage amplifier design [7], and it provides a capacitor-free feature to eliminate the need of bulky off-chip capacitor. Both fast load transient response and high power-supply rejection ratio (PSRR) are achieved due to the fast and stable loop gain provided by the proposed LDO Structure and damping-factor-control (DFC) compensation Scheme. The power pMOS transistor in the proposed LDO operates in linear region at dropout, and hence, the required transistor size can be reduced significantly for the ease of integration and cost reduction. In addition, a novel CMOS voltage reference based on weighted difference of gatesource voltages enables full-CMOS implementation. LDO regulators are an essential part of the power management system that provides constant voltage supply rails. They fall into a class of linear voltage regulators with Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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improved power efficiency, [1]. Efficiency is improved over conventional linear regulators by replacing the common-drain pass element with a common-source pass element to reduce the minimum required voltage drop across the control device. Smaller voltage headroom in the pass element results in less power dissipation, making LDO regulators more suitable for low-voltage, on-chip, power management solutions.
Design And Implementation Of Low Dropout Voltage Regulator With On Chip Capacitor
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CHAPTER 5 EXPECTED OUTPUT
The targeted LDO has to be implemented using Bandgap reference voltage and Miller capacitance concept, using LTspice-IV tool for simulation in 130 nm CMOS technology. This LDO is expected to have good performance on PSRR at high frequencies. Mainly, expected to reduce the dropout voltage to 300mV from 750mV.
TARGETED SPECIFICATION
Gain Bandwidth ~ 1 MHz Settling Time < 5 s Loop Gain ~ 70 dB GND Current < 150 A Dropout Voltage 300 mV Output Current 0 ~ 50 mA PSRR < 40dB @ 100kHz Output Noise < 20 V Line Regulation <= 0.01% Load Regulation <= 0.02%
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REFERENCES
1. Sriranganatha Sagar. K. N, Poornima. N and Vijaya Kumar. V, Capacitor-Less Low- Dropout Voltage Regulator, IEEE J. Solid-State Circuits, pp.25-30, Jan. 2010. 2. G. A. Rincon-Mora and P. E. Allen, A low-voltage, low quiescent current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33, pp.3644, Jan. 1998. 3. G. A. Rincon-Mora, Active multiplier in Miller-compensated circuits, IEEE J. Solid- State Circuits, vol. 35, pp. 2632, Jan. 2000. 4. Texas Instruments, "Fundamental theory of PMOS low dropout voltage regulators," Application Report, Analog and Mixed Signal Products, SL VA068,pp. 1-5,Apr. 1999. 5. K. N. Leung, P. K. T. Mok. A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency, IEEE J. Solid-State Circuits, vol. 37, pp. 1691-1701, Oct. 2003. 6. K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, Three-stage large capacitive load amplifier with damping-factor-control frequency compensation, IEEE J. Solid-State Circuits, vol. 35, pp. 221230, Feb.2000. 7. Robert J Milliken Full on-chip CMOS low-dropout voltage regulator, IEEE transactions on circuits and systems: regular papers, vol. 54, no. 9, September 2007. 8. O. Chevalerias, F. Rodes, K. Salmi, and C. Scarabello, 4-V 5-mA low drop-out regulator using series-pass N-channel MOSFET, Electron Lett, Vol.35, pp.1214-1215, July1999. 9. Allen Hustings "The art of analog layout" Prentice hall, 2001. 10. Phillip E. Allen, Douglas R Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002.
Background of The Study 2. Statement of The Problem 3. Objectives 4. Significance 5. Scope and Limitations 6. Definition of Terms 7. Theoretical Framework RRL