8051 ARCHITECTURE

8051 architecture consists of these features:

• Eight bit CPU with registers A and B
• Sixteen bit program counter and data pointer
• Eight bit program status word
• Eight bit stack pointer
• Internal ROM of 4K
• Internal RAM of 128 bytes:
-Four register banks, each containing eight registers
-Sixteen bytes, which may be addressed at bit level
-Eighty bytes of general-purpose data memory
• Thirty two input/output pins arranged as four 8-bit ports: P0-P3
• Two 16-bit timer/counters: T0 and T1
• Full duplex serial data receiver/transmitter :SBUF
• Control register: TCON, TMOD, SCON, PCON, IP, and IE
• Two external and three internal interrupt sources
• Oscillator and clock circuits

8051 Functional diagram

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A and B CPU Registers:
The 8051 contains 34 general purpose , or working registers. Two of these, register A and
B, hold results of many instructions, particularly math and logical operations. A is also
used for data transfer between the 8051 and any external memory.

Data Pointer:
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its
intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or
as two independent 8-bit registers.

Stack Pointer
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during
PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at locations
08H.

Program counter: Program instruction bytes are fetched from locations in memory that
are addressed by PC.

Program Status Word

The PSW register contains program status information as detailed in Figure .

BIT SYMBOL FUNCTION

PSW.7 CY Carry flag.
PSW.6 AC Auxilliary Carry flag. (For BCD operations.)
PSW.5 F0 Flag 0. (Available to the user for general purposes.)
PSW.4 RS1 Register bank select control bit 1.
Set/cleared by software to determine working register bank. (See Note.)
PSW.3 RS0 Register bank select control bit 0.
Set/cleared by software todetermine working register bank. (See Note.)
PSW.2 OV Overflow flag.
PSW.1 — User-definable flag.
PSW.0 P Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of “one” bits in the Accumulator, i.e., even parity.
NOTE: The contents of (RS1, RS0) enable the working register banks as follows:
(0,0)— Bank 0 (00H–07H)
(0,1)— Bank 1 (08H–0fH)
(1,0)— Bank 2 (10H–17H)
(1,1)— Bank 3 (18H–17H)

Internal RAM:
The 128-byte internal RAM ,is organized into three distinct areas:

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1. Thirty-two bytes from address 00h to 1Fh that make up 32 working registers organized
as four banks of eight registers each.
2 .A bit addressable area of 16 bytes occupies RAM byte addresses 2oh to 2fh,forming a
total of 128 addressable bits.
3. A general purpose RAM area above the bit area, from 30h to 7Fh, adressable as bytes.

Internal ROM:

In 8051 data memory and program code memory are two different entities.Internal ROM
occupies code addresses 0000h to 0FFFh . If program address exceeds 0FFFh then 8051
automatically fetches code from external program memory.Code bytes could also be
fetched exclusively from external memory 0000h to FFFFh ,by connecting the EA pin to
ground.

Memory Expanding:

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In case the built-in amount of memory (either RAM or ROM) is not sufficient for your
needs, there is always an option of adding two external 64KB memory chips. When
added, they are addressed and accessed via I/O ports P2 and P0. From user's point of
view it's all very simple, because if properly connected most of the job is carried out
automatically by MCU.

8051 MCU has two separate read signals, RD# (P3.7) and PSEN#. The first one is active
when reading byte from the external data memory (RAM), and the second one is active
when reading byte from the external program memory (ROM). Both signals are active on
low logical level. The following image shows a typical scheme for such expansion using
separate chips for RAM and ROM, known as Harvard architecture.

Memory can be also mapped as a single block, functioning as both data memory and
program memory simultaneously (only one memory chip is used). This approach is
known as Von Neumann architecture. To be able to read the same block using RD# or
PSEN#, these two signals were combined via logical AND. In this way, output of AND
circuit is low if any of the two inputs is low.

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Using the Harvard architecture effectively doubles MCU memory, but that's not the only
advantage offered by the method. Keeping the program code separated from the data
makes the controller more reliable since there is no writing to the program memory.

Pin Description of 8051:

PIN DIAGRAM

VCC: Pin 40.Provides supply voltage to the pin, + 5V.

GND: Pin 20.

XTAL1 and XTAL2: XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven
as shown in Figure 2.

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Note: C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators GND
Note: C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators GND

Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs.Port 0 may also be configured to be the multiplexed loworder
address/data bus during accesses to external program and data memory. In this mode P0
has internal pullups. Port 0 also receives the code bytes during Flash programming,and
outputs the code bytes during program verification. External pullups are required during
program verification.

Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers
can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high
by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally
being pulled low will source current (IIL) because of the internal pullups.Port 3 also
receives some control signals for Flash programming and verification.

Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high
by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the
high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2
Special Function Register.Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers
can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high
by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally

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being pulled low will source current (IIL) because of the pullups. Port 3 also serves the
functions of various special features of the AT89C51 as listed below:

ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data Memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit
set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.
.
PSEN
Program Store Enable is the read strobe to external program memory.When the AT89C51
is executing code from external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory.

EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.

SFR Registers (Special Function Registers)

SFR registers can be seen as a sort of control panel for managing and monitoring the
microcontroller. Every register and each of the belonging bits has its name, specified
address in RAM and strictly defined role (e.g. controlling the timer, interrupt, serial
connection, etc). Although there are 128 available memory slots for allocating SFR
registers, the basic core shared by 8051 MCUs has but 22 registers. The rest has been left

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open intentionally to allow future upgrades while retaining the compatibility with earlier
models. This fact makes possible to use programs developed for obsolete models long
ago.

Counters and Timers

MCU clock employs quartz crystal. As this frequency is highly stable and accurate, it is
ideal for time measuring (similar oscillators can be found in watches). To determine the
amount of time past between two occurrences, all you need to do is count the generated
impulses. This is where the timer takes part; properly programmed, value of timer register
will increase or decrease with every MCU clock impulse. Since one instruction takes 12
oscillator cycles to complete, the math is easy. For example, if quartz oscillator works at
12 MHz, timer register will increase/decrease every microsecond (million times per
second). 8051 has two 16-bit timers/counters marked as T0, T1.

TMOD - Timer Mode

This register sets mode for timers T0 and T1. As shown in the image below, lower 4 bits
(bit 0 - bit 3) are associated with T0, while the higher 4 bits (bit4 - bit7) are associated
with T1.

The following table gives details on bits 0 - 7 :

Bit Bit Name Purpose Timer

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 7 GATE1 1 Timer works only if INT1 (P3.3) is set T1
0 Timer works regardless of INT1 (P3.3)
6 C/T1 1 Timer counts impulses on T1 (P3.5) T1
0 Timer counts impulses of internal oscillator
5 T1M1 Timer mode T1
4 T1M0 Timer mode T1
3 GATE0 1 Timer works only if INT0 (P3.2) is set T0
0 Timer works regardless of INT0 (P3.2)
2 C/T0 1 Timer counts impulses on T0 (P3.4) T0
0 Timer counts impulses of internal oscillator
1 T0M1 Timer mode T0
0 T0M0 Timer mode T0

Four bits from the previous table determine the operating mode of timers T0 and T1.
There are 4 of these modes, and each will be covered in details.

T0M1 T0M0 Mode Description

0 0 0 13-bit Timer
0 1 1 16-bit Timer
1 0 2 8-bit auto-reload
1 1 3 Split mode

Mode 0 (13-bit Timer)

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This mode is an antiquity kept just for the sake of compatibility with older MCUs. When
activated, whole higher byte TH0 and only the first 5 bits of lower byte TL0 are
accessible. Thus, with Mode 0, Timer T0 uses only 13 of its 16 bits. How does it work?
On each impulse, lower register is changed (the "trimmed" one). When TL0 is filled after
32 impulses, it is automatically reset, and TH0 is increased by one. This process repeats
itself until 8192 impulses are registered, upon which both registers are reset to zero.

Mode 1 (16-bit Timer)

Mode 1 uses all bits of registers TH0 and TL0, and is commonly used. Counting process
is same as with Mode 0, except the timer reaches value of 65.536 (max for 16 bits) before
reset.

Mode 2 (8-bit "auto reload" Timer)

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What is "auto reload" ? Simply, only one of two registers is used for counting; however,
it does not start from zero, but from a specified value stored in the other register (0-255).

Advantages of this mode will be illustrated on the following example: suppose that there
is a need to report every 55th impulse of the clock. If Mode 0 or Mode 1 was used, you
would need to store 200 (decimal) into T0, and then continually check for the overflow
(exceeding 255 decimal). Upon hit, value of 200 would need to be written to T0 again. In
Mode 2, MCU performs this task automatically. Namely, TL0 works as an 8-bit timer,
while TH0 stores the starting value, specifically 200 in our example. When TL0 is filled,
instead of reset, it will load value from TH0. Thus, to register every 55th impulse, all you
need to do is write 200 to TH0, and set the Timer Mode 2.

Mode 3 ("Split" Timer)

When Timer T0 is configured to Mode 3, you actually get an additional timer. In this
mode, registers TH0 and TL0 act as separate 8-bit timers: TH0 substitutes Timer 0, while
TL0 substitutes Timer 1. Consequently, all control bits associated with the original Timer
1 (16-bit register consisting of TH1 and TL1) are now in control of newly created "Timer
1". This means that, although it can be set to any mode (Mode 1, 2, or 3), the original
Timer 1 cannot be stopped anymore, because there is simply no control bit to do it. In this
mode, it will be constantly active in the background.

TCON - Timer Control

TCON is another register in direct control of the timers.

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Of the 8 bits, TCON uses only 4 bits for controlling the timers, while the other 4 are
associated with interrupts.

Bit Bit Name Purpose Timer

7 TF1 This bit is automatically set in T1
case of overflow in Timer T1
6 TR1 1 - Timer T1 is on T1
0 - Timer T1 is off
5 TF0 This bit is automatically set in T0
case of overflow in Timer T0
4 TR0 1 - Timer T0 is on T0
0 - Timer T0 is off

Starting Timer T0

Select this timer and set the desired mode.

This sets the Timer T0 to operate in Mode 1, and count the impulses of internal source
with frequency equal to 1/12 of the quartz oscillator's frequency.

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Right after the command for setting the bit TR0, Timer is operational. Assuming that
12MHz quartz crystal is installed, value in T0 will increase every microsecond. After
passing of 65.536 microseconds, both registers of the Timer will be full. MCU
automatically resets them and the Timer continues the loop, as long as the bit TR0 is set.

Reading Timer

Depending on the application, you need either the value written in Timer registers, or the
exact point of time at which the Timer is reset.

 If you need to read the value of the Timer which uses only one register for
counting (Mode 3, for example) just read the value of that register.
 If the Timer works in Mode 2, reading is a bit more complicated. For example,
you might have obtained values of the lower and the higher byte, respectively:

TH0=15, TL0=255.

Seemingly, the results are valid, but the true state of registers at the moment of
reading was:

TH0=14, TL0=255.

This widely inaccurate reading (255 impulses) may happen due to not so obvious,
yet perfectly logical reason. Lower byte was read ok (255), but while the Program
Counter was "loading" your new instruction for reading TH0, overflow occurred,
changing both registers (TH0: 14 -> 15, TL0: 255 -> 0). Solution to the problem
is simple: you need to read the higher byte first, then the lower byte, and then the

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 higher byte again. If two readings of higher byte do not match, the sequence has
to be repeated (this is a mini-loop in the program, not more than 3 instructions).

There is also another solution: just turn off the Timer for the time of reading (clear
the bit TR0 in TCON), and turn it on afterwards.

Detection of Overflow

Usually, there is no need to continually read the Timer registers; it is sufficient to detect
the moment at which they are reset, the so-called Overflow. When it happens, bit TF0 in
TCON will be automatically set. This moment can be "awaited", by writing a small loop
for testing the bit continually, or by enabling an interrupt. Suppose that there is a need to
suspend a program for duration of 0.05 seconds (5000 cycles):

First, you need to calculate a number to be written to Timer registers:

This value should be stored to Timer registers TH0 and TL0:

After that, when started (bit TR0 = 1), Timer will continue the counting up from our
written value. Now a program instruction can be used to test if the bit TF0 was set, which
should take place after exactly 50.000 cycles, i.e. 0.05 seconds.

Measuring Impulse Duration

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Measuring time past between two events is a common task in electronics; for example,
measuring for how long has device been active. Note the bit named GATE0 (in TMOD
Register) in the Timer schematics. If this bit is cleared, pin P3.2 has no effect on the
Timer. But, if GATE0 = 1, Timer will work only for as long as the pin P3.2 is set. This
means that, by bringing 5V externally to this bit, simultaneously with turning the power
on, Timer can measure the active period of the device, which was the original idea.

Counting Impulses

The answer is in bit C/T0 in TCON Register. Similar to the previous example, C/T0
"brings in" an external signal: if bit is cleared, Timer measures the time, i.e. impulses
generated by MCU clock. If bit is set, impulses from P3.4 (T0) are conducted to Timer's
input. Having no predetermined order or sequence, these impulses cannot be used for
measuring time, effectively turning the Timer into Counter. The highest frequency this
Counter can record equals 1/24 of frequency of used quartz-crystal.

UART (Universal Asynchronous Communication)

One of the things that makes this MCU so powerful is the hardware integrated UART,
better known as serial port. It is a duplex port capable of sending and receiving data
simultaneously. Without it, serial data transfer would be an endlessly complicated task,
with numerous checks performed at strictly defined pace. UART represents an elegant
solution: programmer just needs to set the mode and the rate of transfer. Register SBUF
holds data to be sent to line, and the same register accepts data from the line. Controller
takes care of all the details of transfer with no room for error.

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Before using the serial port, it should be appropriately configured. SFR register SCON
(Serial Control) is in control of the transfer parameters: size of one serial "word" in bits,
baud rate, and the source of impulses for synchronization.

SCON (Serial Port Control Register)

Bit Name Bit Address Purpose

SM0 9Fh Mode of work
SM1 9Eh Mode of work
SM2 9Dh Enables connecting multiple MCU's
REM 9Ch When set, enables receiving data
TB8 9Bh 9th bit for sending data in modes 2 and 3
RB8 9Ah 9th bit for sending data in modes 2 and 3
TI 99h Bit is automatically set when the whole byte is
sent
RI 98h Bit is automatically set when the whole byte is
received

As shown in the table, combination of bits SM0 and SM1 determines the mode of work
for serial port:

SM0 SM1 Mode Description Baud Rate

0 0 0 8-bit Shift register Quartz frequency / 12
0 1 1 8-bit UART Determined by timer T1 or T2
1 0 2 9-bit UART Quartz frequency / 32
1 1 3 9-bit UART Determined by timer T1 or T2

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Obviously, baud rate in modes 0 and 2 is fixed, and can be adjusted in modes 1 and 3
(details can be found in the chapter on timers). In addition, baud rate in modes 1, 2, and 3
is doubled if bit SMOD in register PCON is set (see below).

Mode 0

Mode 0 is not used for standard serial communication, but serves to provide additional
I/O pins. External shift registers convert the data into binary sequence, which is then
serially transferred to the controller. Although there is no limit on the number of I/O ports
that can be gained in this manner, the existing 32 I/O lines are sufficient for most of the
tasks, making this mode rarely used.

Mode 1

This is the standard RS-232 mode for serial transfer of 8-bit data. Sequence of ten bits is
sent via pin TXD or received via pin RXD in the following order: one start bit (always 0),
followed by 8 data bits (LSB bit is first), and one stop bit (always 1). Start bit is not
registered anywhere as its sole purpose is to start the mechanism for receiving data. When
data is received, stop bit is automatically copied to bit RB8 in register SCON. In order to
connect the controller to RS-232 line, this "raw" serial data needs to be inverted - this is
carried out automatically by the designated drivers.

Modes 2 and 3

These modes are frequently used for speedy transfers at short range (Mode 2) and for
standard RS-232 transfers with parity bit (Mode 3). Both modes transfer 9-bit data in the
following order: one start bit (always 0), followed by 8 data bits (LSB bit is first), 9th bit
which is copied from the bit TB8 before transfer, and to the bit RB8 after transfer, and
finally one stop bit (always 1).

Other bits of register SCON have following roles:

Bit Purpose
SM2 This bit is used if multiple microcontrollers exchange data using the
same line. Otherwise, it needs to be cleared to provide normal
functioning of the communication
REN Needs to be set to enable receiving data via serial communication
TB8 Auxiliary 9th bit in 9-bit transfer (modes 2 and 3)
RB8 Similar to TB8, but on receiving. When accepting 9-bit data, it stores

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 value of the ninth bit.
TI This bit is automatically set when the last bit of one byte has been
proceeded to the line. In this way, processor "knows" that the line is
free for sending another byte.
RI Similar to TI, but on receiving. It is a "doorbell" of a kind, which
indicates that one byte has been received, and that it should be read
before another one arrives.

Setting the Baud Rate

Once you have selected the mode of UART, you need to set the Baud Rate.

Baud Rate in modes 0 and 2 depends solely on the frequency of quartz crystal. Crystals
designed specifically for this purpose can be found in the market. Although their
frequencies might seem a bit exotic at first (e.g. 11.059 MHz), they produce standard
rates for serial communication after the clock has been divided by the controller.

Baud Rate in modes 1 and 3 is determined by timers T1 and/or T2. Timer T1 is most
commonly used in "Auto-Reload" mode (TMOD = 0010xxxx). In this case, rate is
determined by the frequency of overflow occurrence, and can be calculated according to
the formula:

Quartz oscillator frequency

Baud Rate =
384 * (256 - TH1)

If bit SMOD in register PCON is set, rate will be doubled:

Quartz oscillator frequency

Baud Rate =
192 * (256 - TH1)

Here, bits which are automatically set upon overflow are of no use, and should be cleared
to avoid causing an interrupt.

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If timer T2 is used for setting the Baud Rate, its bits will always have priority, allowing
the microcontroller to send and receive data at different rates:

RCLK TCLK Mode of work

0 0 Rates of sending and receiving are equal and set by timer T1
only
0 1 Receiving rate is set by T1, sending rate is set by T2
1 0 Receiving rate is set by T2, sending rate is set by T1
1 1 Rates of sending and receiving are equal and set by timer T2
only

Sending and Receiving Data via UART

Once UART is prepared for transfer, sending and receiving data is very simple. It all
comes down to simple writing and reading of register SBUF.

As soon as data is written to this port, MCU starts sending it, one bit at a time. At the end
of the sequence, bit TI in register SCON is set to indicate that one byte has been sent.
Similar procedure takes place when receiving data - after the bit RI (also in SCON) has
been set, you just need to read the register SBUF.

IE (Interrupt Enable)

Following table describes the bits of register IE

(same rule applies to all bits - logical state of 1 enables the appropriate interrupt):

Bit Purpose
EA Enables/disables all interrupt sources
ET2 Timer T2 interrupt
ES UART
ET1 Timer T1 interrupt
EX1 External interrupt: pin INT1

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 ET0 Timer T0 interrupt
EX0 External interrupt: pin INT0

Interrupt Priorities

It cannot be predicted with absolute certainty when will interrupt request take place. If
multiple interrupts are enabled, it's quite possible to have interrupt requests during
execution of another interrupt routine. In such cases, controller needs to resolve whether
to proceed with the current interrupt routine, or to enter a new one, based on a priority
check. Our microcontroller can differentiate between three priority levels:

1. Reset. If there is a request for reset, all processes are halted and the controller
behaves as if the power had just been turned on.
2. Priority 1 interrupts. Can be interrupted only by reset.
3. Priority 2 interrupts. Can be interrupted by any of above.

IP (Interrupt Priority)

SFR register IP determines the priority of existing interrupt sources

(Same rule applies to all bits : logical state of 1 assigns higher priority to the appropriate
interrupt):

Bit Purpose
PT2 Timer T2 interrupt priority
PS Serial port interrupt priority
PT1 Timer T1 interrupt priority
PX1 External interrupt INT1 priority
PT0 Timer T0 interrupt priority
PX0 External interrupt INT0 priority

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If two interrupt requests collide, the one with higher priority has precedence in execution.
If both interrupts are of same priority, the one with the later request has to hold one and
let the controller handle the first one.

How does interrupt execute?

Upon receiving an interrupt request, following scenario takes place:

1. Current instruction is executed first.

2. Address of the instruction that would be executed next if there was no interrupt
request is put away to stack.
3. Depending on the interrupt in question, program counter will take value of one of
possible 6 vectors (addresses) according to the table below.

Interrupt source Vector (address in hex)

IE0 3h
TF0 Bh
IE1 13h
TF1 1Bh
RI, TI, SPIF 23h
TF2, EXF2 2Bh

These addresses should hold the appropriate subroutines for handling the interrupts.
In practice, instead of actual routines, they only point to the location of appropriate
routines in the code.

4. Upon accomplishing the interrupt routine, address of the next instruction to be

executed is retrieved from the stack, and the program proceeds from the location
where it was interrupted.

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