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    Air University Fall 2005 Faculty of Engineering Department of Electronics Engineering Course Information

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    Ali Ahmad
    This document provides information about the course "EE 411 Introduction to ASIC Design Lab". The course is a 4 credit hour course that teaches ASIC design using VHDL and commercial CAD tools. Over 15 weeks, topics will include ASIC design flow, logic synthesis, simulation, combinational and sequential logic design, state machines, and system level design. The final exam accounts for 45% of the grade, with sessional exams, quizzes, assignments, and labs making up the rest. The objective is for students to learn ASIC design using commercial tools and pre-designed cell libraries.

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    Air University Fall 2005 Faculty of Engineering Department of Electronics Engineering Course Information

    Uploaded by

    Ali Ahmad
    37 views2 pages
    This document provides information about the course "EE 411 Introduction to ASIC Design Lab". The course is a 4 credit hour course that teaches ASIC design using VHDL and commercial CAD tools. Over 15 weeks, topics will include ASIC design flow, logic synthesis, simulation, combinational and sequential logic design, state machines, and system level design. The final exam accounts for 45% of the grade, with sessional exams, quizzes, assignments, and labs making up the rest. The objective is for students to learn ASIC design using commercial tools and pre-designed cell libraries.

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    Course Outline

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    This document provides information about the course "EE 411 Introduction to ASIC Design Lab". The course is a 4 credit hour course that teaches ASIC design using VHDL and commercial CAD tools. Over 15 weeks, topics will include ASIC design flow, logic synthesis, simulation, combinational and sequential logic design, state machines, and system level design. The final exam accounts for 45% of the grade, with sessional exams, quizzes, assignments, and labs making up the rest. The objective is for students to learn ASIC design using commercial tools and pre-designed cell libraries.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    37 views2 pages

    Air University Fall 2005 Faculty of Engineering Department of Electronics Engineering Course Information

    Uploaded by

    Ali Ahmad
    This document provides information about the course "EE 411 Introduction to ASIC Design Lab". The course is a 4 credit hour course that teaches ASIC design using VHDL and commercial CAD tools. Over 15 weeks, topics will include ASIC design flow, logic synthesis, simulation, combinational and sequential logic design, state machines, and system level design. The final exam accounts for 45% of the grade, with sessional exams, quizzes, assignments, and labs making up the rest. The objective is for students to learn ASIC design using commercial tools and pre-designed cell libraries.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    AIR UNIVERSITY Fall 2005 Faculty of Engineering Department of Electronics Engineering Course Information

    Course Title: EE 411 Introduction to ASIC Design Lab (Yes/No) Yes Credit hrs: 04 Prerequisites For this Course: CS 203 Digital Logic Design This Course is Prerequisite For: None Instructor: Muhammad Ali Raza Anjum e-mail :ali.raza.anjum@gmail.com Office: Academic Block B, Room # 103 Web: http://www.xyz.com Office hours:Mon-Friday:8:30 to 4:00 pm Text Book: [1] - J. S. Smith, Application-Specific Integrated Circuits, el, Addison- Wesley, VLSI Design Series, 1997 Reference Book(s): [1] - Peter Ashenden, The Designer's Guide to VHDL, el, Morgan-Kaufman Publishers, 1995

    Course Outline (one paragraph 3-4 lines) Introduction to standard cell design of VLSI digital circuits using VHDL hardware description language. Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing

    Lecture Plan: Week 1 2 3 4 5 6 Topic


    Course overview, introduction to ASICs , IC design flow, top down design, Types of ASICS, ASIC Economics Logic Synthesis: Introduction to Logic Synthesis with VHDL Simulation :Aspects of simulation: behavioral, functional, gate level and timing simulation, static timing analysis, switch level simulation Combinational logic design - schematic and VHDL: Decoders, Encoders, Multiplexers, Use of test benches, timing constraints, optimization trade-offs Sequential logic functions in VHDL: Counters, Shift Registers

    7 10-11 12-13 14-15 Final

    State machine design in VHDL: Moores Implementation, Mealays Implementation System level design in VHDL; Writing ASIC specifications, Packages & Components, Functions & Procedures, Case Study ASIC and programmable logic implementation technologies (full custom, standard cell, FPGA) Chip Construction, floor-planning, Testing Student presentations and final reports

    Grading and General Course Policies: Final:45% Sessional Exams:20% Quizes:10% Assignments:5% Labs:20%

    Objective of course: (one paragraph 3-4 lines)


    ASIC design, using commercial tools and pre-designed cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC design methods have become increasingly popular in industry for a wide range of electronic systems applications. This course will describe and present solutions for the most difficult current challenges in ASIC design

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