High Accuracy, Low IQ, anyCAP Adjustable Low Dropout Regulator ADP3334

FEATURES High Accuracy over Line and Load: 0.9% @ 25C, 1.8% over Temperature 500 mA Current Capability Ultralow Dropout Voltage Requires Only CO = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1.0 A (Typ) 2.6 V to 11 V Supply Range 1.5 V to 10 V Output Range 40 C to +85C Ambient Temperature Range APPLICATIONS Cellular Phones TFT LCD Modules Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Boxes DSP Supplies Personal Digital Assistants FUNCTIONAL BLOCK DIAGRAM
IN THERMAL PROTECTION Q1 OUT

ADP3334
CC
FB gm

DRIVER
SD

BAND GAP REF

GND

GENERAL DESCRIPTION

The ADP3334 is available in three different package options: 1. Excellent thermal capability, space saving 3 mm 3 mm LFCSP. 2. Popular low profile MSOP-8. 3. Traditional thermal enhanced SOIC-8.
ADP3334
IN

The ADP3334 is a member of the ADP333x family of precision low dropout anyCAP voltage regulators. The ADP3334 operates with an input voltage range of 2.6 V to 11 V and delivers a continuous load current up to 500 mA. The novel anyCAP architecture requires only a very small 1 F output capacitor for stability, and the LDO is insensitive to the capacitors equivalent series resistance (ESR). This makes the ADP3334 stable with any capacitor, including ceramic (MLCC) types for space restricted applications. The ADP3334 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. The dropout voltage of the ADP3334 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 A. The ADP3334 has low quiescent current of 90 A (typical) in light load situations.

OUT
OUT
R1
FB

VIN
CIN 1F

IN

VOUT

CNR

COUT 1F

SD

GND

R2

OFF ON

Figure 1. Typical Application Circuit

REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved.

ADP3334SPECIFICATIONS1, 2, 3 (V
Parameter OUTPUT Voltage Accuracy4 Symbol VOUT

IN

= 6.0 V, CIN = COUT = 1.0 F, TA = 40C to +85C, unless otherwise noted.)

Min 0.9 Typ Max +0.9 Unit %

Conditions VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TA = 25C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TA = 85C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TJ = 150C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA TA = 25C IL = 0.1 mA to 500 mA TA = 25C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 100 mA IL = 1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz100 kHz, CL = 10 F IL = 500 mA, CNR = 10 nF f = 10 Hz100 kHz, CL = 10 F IL = 500 mA, CNR = 0 nF IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) 100 mV IL = 0.1 mA SD = 6 V, VIN = 11 V LDO OFF LDO ON 0 SD 5 V SD = 2 V, VIN = 11 V

1.8

+1.8

2.3

+2.3

Line Regulation4

0.04

mV/V

Load Regulation Dropout Voltage VDROP

0.04

mV/mA

Peak Load Current Output Noise

ILDPK VNOISE

200 140 60 10 800 27 45

400 250 140

mV mV mV mV mA V rms V rms

GROUND CURRENT5 In Regulation

IGND

In Dropout In Shutdown SHUTDOWN Threshold Voltage SD Input Current Output Current in Shutdown

IGND IGNDSD VTHSD ISD IOSD

4.5 2.6 0.5 90 150 0.9 2.0 1.2 0.01

10 6 1.5 130 450 3

mA mA mA A A A V V A A

0.4 3 5

NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 Ambient temperature of 85C corresponds to a junction temperature of 125C under pulsed full load test conditions. 3 Application stable with no load. 4 VIN = 2.6 V to 11 V for V OUT(NOM) 2.2 V. 5 Ground current includes current through external resistors. Specifications subject to change without notice.

REV. B

ADP3334
ABSOLUTE MAXIMUM RATSINGS * PIN FUNCTION DESCRIPTIONS

Input Supply Voltage . . . . . . . . . . . . . . . . . . . 0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . 0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . 40C to +85C Operating Junction Temperature Range . . . 40C to +150C Storage Temperature Range . . . . . . . . . . . . 65C to +150C JA 2-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . 122.3C/W JA 4-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . . 86.6C/W JA 2-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 62C/W JA 4-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W JA 2-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 220C/W JA 4-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W Lead Temperature Range (Soldering 6 sec) . . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Mnemonic GND SD IN OUT FB

Function Ground Pin. Shutdown Control. Pulling this pin low turns on the regulator. Regulator Input. Output. Bypass to ground with a 1.0 F or larger capacitor. Feedback Input. FB should be connected to an external resistor divider that sets the output voltage. No Connection.

NC

PIN CONFIGURATIONS
OUT 1 OUT 2 FB 3 NC 4 NC = NO CONNECT
8

IN IN SD GND

OUT 1 OUT 2 FB 3 NC 4

IN IN SD GND

GND 1 SD 2 IN 3 IN 4 NC = NO CONNECT

NC FB OUT OUT

ADP3334ARM
TOP VIEW (Not to Scale)

7 6 5

ADP3334ACP
TOP VIEW*

7 6 5

ADP3334AR
TOP VIEW (Not to Scale)

7 6 5

*PINS UNDERSIDE NC = NO CONNECT

ORDERING GUIDE

Model ADP3334AR ADP3334ACP

Package Output Description ADJ ADJ

Package Option

Brand

ADP3334ARM

ADJ

Standard Small Outline RN-8 Package (SOIC-8) Lead Frame Chip CP-8 Scale Package (LFCSP) 3 mm 3 mm Body, 8-Lead MSOP Package RM-8

LLA

LLA

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3334 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

ADP3334Typical Performance Characteristics

2.202 2.201
OUTPUT VOLTAGE V

VOUT = 2.2V IL = 0
OUTPUT VOLTAGE V

2.201 2.200 2.199 2.198 2.197 2.196 2.195 2.194 VOUT = 2.2V VIN = 6V

140 120

IL = 100A

VOUT = 2.2V

2.200 2.199 150mA 2.198 2.197 300mA 2.196 2.195 2.194 2 4 6 8 INPUT VOLTAGE V 10 12 500mA

GROUND CURRENT A

100 80 60 40 20 0
IL = 0

2.193 0 100 200 300 OUTPUT LOAD mA 400 500

4 6 8 INPUT VOLTAGE V

10

12

TPC 1. Line Regulation Output Voltage vs. Supply Voltage

TPC 2. Output Voltage vs. Load Current

TPC 3. Ground Current vs. Supply Voltage

5.0 VIN = 6V VOUT = 2.2V 4.0

0.5 0mA 0.4

8
IL = 500mA

GROUND CURRENT mA

300mA

VIN = 6V VOUT = 2.2V

GROUND CURRENT mA

OUTPUT CHANGE %

0.3 0.2 0.1 500mA 0 0.1 500mA 0

6 5 4 3 2 1
100mA
50mA

3.0

300mA

2.0

1.0

200 300 100 OUTPUT LOAD mA

400

500

0.2 50 25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE C

0 0 50 25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE C

TPC 4. Ground Current vs. Load Current

TPC 5. Output Voltage Variation % vs. Junction Temperature

TPC 6. Ground Current vs. Junction Temperature

250

INPUT/OUTPUT VOLTAGE V

VOUT V

VOUT = 2.2V

3.0 2.5 2.0 1.5

DROPOUT VOLTAGE mV

200

VOUT = 2.2V SD = GND RL = 4.4

3 2 COUT = 1F 1 0 4 COUT = 10F

150

100

VIN V

1.0 0.5 0 1 2 3 TIME s 4

2 0 200 400 600 TIME s

VOUT = 2.2V SD = GND RL = 4.4 800

50

200 300 100 OUTPUT LOAD mA

400

500

TPC 7. Dropout Voltage vs. Output Current

TPC 8. Power-Up/Power-Down

TPC 9. Power-Up Response

REV. B

ADP3334
VOUT V VOUT V
VOUT V

2.210 2.200 2.190 2.180 2.170 3.500 VOUT = 2.2V RL = 4.4 CL = 1F

2.210 2.200 2.190 2.180 2.170 VOUT = 2.2V RL = 4.4 CL = 10F

2.3 2.2 2.1

IOUT mA

400 200 0 VIN = 6V VOUT = 2.2V CL = 1F 200 400 600 TIME s 800

VIN V

3.000 40 80 140 TIME s 180

VIN V

3.500 3.000 40 80 140 TIME s 180

TPC 10. Line Transient Response

TPC 11. Line Transient Response

VOUT V

TPC 12. Load Transient Response

VOUT V

2.3 2.2 2.1

2.2 VOUT V 0 FULL SHORT 2 1 0 VIN = 6V VOUT = 2.2V RL = 4.4 1F 10F 1F 10F

800m SHORT

IOUT mA

IOUT A

400 200 0 VOUT = 2.2V VIN = 6V CL = 10F 200 400 600 TIME s 800

2 VSD V 1 0 200 400 600 TIME s 800 VIN = 4V 2 0 200

400 600 TIME s

800

TPC 13. Load Transient Response

20 30 VOUT = 2.2V CL = 1F IL = 500mA CL = 1F IL = 50A CL = 10F IL = 500mA RMS NOISE V

TPC 14. Short Circuit Current

160 140 120 100 80 60 40
IL = 500mA WITHOUT NOISE REDUCTION IL = 500mA WITH NOISE REDUCTION IL = 0mA WITHOUT NOISE REDUCTION

TPC 15. Turn Off/On Response

100 VOUT = 2.2V IL = 1mA CL = 10F CNR = 10nF CL = 10F CNR = 0 CL = 1F CNR = 0

VOLTAGE NOISE SPECTRAL DENSITY V/ Hz

VOUT = 2.0V CNR = 10nF

RIPPLE REJECTION dB

10

40 50 60 70 80 90 10 100

0.1 CL = 1F CNR = 10nF

CL = 10F IL = 50A 1k 10k 100k FREQUENCY Hz 1M 10M

0.01

20 0 0
IL = 0mA WITH NOISE REDUCTION

10

20 30 CL F

40

50

0.001 10

100

1k 10k 100k FREQUENCY Hz

1M

TPC 16. Power Supply Ripple Rejection

TPC 17. RMS Noise vs. CL (10 Hz to 100 kHz)

TPC 18. Output Noise Density

REV. B

ADP3334
THEORY OF OPERATION

The new anyCAP LDO ADP3334 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 that is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier.
INPUT Q1 OUTPUT ATTENUATION (VBANDG AP / VOUT) COMPENSATION CAPACITOR R3 D1 PTAT FB VOS gm PTAT CURRENT R4

superior line noise rejection and very high regulator gain, which lead to excellent line and load regulation. An impressive 1.8% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit and thermal shutdown.
APPLICATION INFORMATION Output Capacitor

R1 CLOAD (a) RLOAD R2

NONINVERTING WIDEBAND DRIVER

ADP3334

GND

As with any micropower device, output transient response is a function of the output capacitance. The ADP3334 is stable with a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 1 F is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3334 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum over the operating temperature range or with the application of a dc voltage.
Input Bypass Capacitor

Figure 2. Functional Block Diagram

A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, offset voltage that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a virtual band gap voltage, implicit in the network although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the band gap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3334 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 mF capacitor on the output. Additional advantages of the pole-splitting scheme include

An input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. Connecting a 1 F capacitor from IN to ground reduces the circuits sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended.
Noise Reduction Capacitor

A noise reduction capacitor (CNR) can be placed between the output and the feedback pin to further reduce the noise by 6 dB to 10 dB (TPC 18). Low leakage capacitors in the 100 pF to 1 nF range provide the best performance. Since the feedback pin (FB) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible, and long PC board traces are not recommended. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values of 1 nF, this delay may be on the order of several milliseconds.
ADP3334
IN
VIN IN OUT

OUT

VOUT

CIN 1F
SD
OFF ON

R1

CNR

FB
GND

COUT 1F

R2

Figure 3. Typical Application Circuit

Output Voltage

The ADP3334 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2 and then fed back to the FB pin.

REV. B

ADP3334
To have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the value of the parallel resistance of R1 and R2 be kept as close as possible to 50 kW.
OUTPUT ERROR %
3.0 2.5

R1 R2 (1) = 50 kW R1 + R2 Also, for the best accuracy over temperature, the feedback voltage should be set for 1.178 V: VFB = VOUT R2 R1 + R2 (2)

2.0

1.5

1.0

0.5

where VOUT is the desired output voltage and VFB is the virtual band gap voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 gives the following formulas:
V R1 = 50 kW OUT V FB

0 0 2 3 4 Rp ERROR % 5 6

Figure 4. Output Voltage Error vs. Parallel Resistance Error

(3) (4)

The actual output voltage can be calculated using the following equation.

R2 =

50 kW VFB 1 - V OUT
Table I. Feedback Resistor Selection

R1 VOUT = 1.178 V + 1 R2 VOUT = 3.274 V

(5)

So worst-case error will occur when R1 has a 1% tolerance and R2 has a +1% tolerance. Recalculating the output voltage, the parallel resistance and error are:

VOUT (V) 1.5 1.8 2.2 2.7 3.3 5.0 10.0

R1 (1% Resistor) (k) 63.4 76.8 93.1 115.0 140.0 210.0 422.0

R2 (1% Resistor) (k) 232.0 147.0 107.0 88.7 78.7 64.9 56.2

138.6 VOUT = 1.178 V + 1 79.5 VOUT = 3.232 V 3.232 Resistor Divider Error = - 1 100% = - 2.1% 3.3
RPARALLEL = RPARALLEL R1 R2 138.6 79.5 = = 50.51 kW R1 + R2 138.6 + 79.5 50.51 Error = - 1 100% = 1.02% 50

(6)

Using standard 1% values, as shown in Table I, will sacrifice some output voltage accuracy. To estimate the overall output voltage accuracy, it is necessary to take into account all sources of error. The accuracy given in the specifications table does not take into account the error introduced by the feedback resistor divider ratio or the error introduced by the parallel combination of the feedback resistors. The error in the parallel combination of the feedback resistors causes the reference to have a wider variation over temperature. To estimate the variation, calculate the worst-case error from 50 kW, and then use the graph in Figure 4 to estimate the additional change in the output voltage over the operating temperature range. For example: VIN = 5 V VOUT = 3.3 V R1 = 140 kW, 1% R2 = 78.7 kW, 1%

(7)

So, from the graph in Figure 4, the output voltage error is estimated to be an additional 0.25%. The error budget is 1.8% (the initial output voltage accuracy over temperature), plus 2.1% (resistor divider error), plus 0.25% (parallel resistance error) for a worst-case total of 4.15%.
Thermal Overload Protection

The ADP3334 is protected against damage from excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced.

REV. B

ADP3334
Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150C.
Calculating Junction Temperature

Device power dissipation is calculated as follows: where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages, respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and VOUT = 2.8 V, device power dissipation is: PD = (5 - 2.8) 400 mA + 5.0 (4 mA) = 900 mW (9) As an example, the proprietary package used in the ADP3334 has a thermal resistance of 86.6C/W, significantly lower than a standard SOIC-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to:
DTJA = 0.900W 86.6C / W = 77.9C

PD = (VIN - VOUT ) I LOAD + (VIN ) IGND

(8)

As an example, the patented thermal coastline lead frame design of the ADP3334 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 86.6C/W thermal resistance for the SOIC-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. This yields a 15% improvement in heat dissipation capability as compared to a standard SOIC-8 package. The thermal resistance can be decreased by an additional 10% by attaching a few square centimeters of copper area to the IN or OUT pins of the ADP3334 package. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3334s pins since it will increase the junction-to-ambient thermal resistance of the package.
2x VIAS, 0.250 35m PLATING 0.73 0.30 1.80 0.90 0.50 2.36

(10)

To limit the maximum junction temperature to 150C, maximum allowable ambient temperature will be:

TAMAX = 150C - 77.9C / W = 72.1C

(11)
1.40 1.90 3.36

The maximum power dissipation versus ambient temperature for each package is shown in Figure 5.
3.5
48C/W LFCSP

3.0
POWER DISSIPATION W

Figure 6. 3 mm x 3 mm LFCSP Pad Pattern (Dimensions shown in millimeters)

LFCSP Layout Considerations

2.5
62C/W LFCSP

2.0
86C/W SOIC

1.5

122C/W SOIC

The LFCSP package has an exposed die paddle on the bottom, which efficiently conducts heat to the PCB. In order to achieve the optimum performance from the LFCSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the LFCSP package. 1. The pad pattern is given in Figure 6. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging.
80

1.0
158C/W MSOP 220C/W MSOP

0.5

0 20

20 40 60 AMBIENT TEMPERATURE C

Figure 5. Power Derating Curve

Printed Circuit Board Layout Consideration

All surface-mount packages rely on the traces of the PC board to conduct heat away from the package. In standard packages, the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages, one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins.

2. The thermal pad of the LFCSP package provides a low thermal impedance path (approximately 20C/W) to the PCB. Therefore the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 5 for the recommended via pattern. Note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Note that the thermal pad is attached to the die substrate, so the thermal planes that the vias attach the package to must be electrically isolated or connected to VIN. Do NOT connect the thermal pad to ground.

REV. B

ADP3334
3. The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in a minimum 60 micron (2.4 mils) clearance between the pad and the solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A No Clean Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3C/second or lower. The actual temperature profile depends on the board density and must determined by the assembly house as to what works best. Use the following general guidelines when designing printed circuit boards. 1. Keep the output capacitor as close as possible to the output and ground pins. 2. Keep the input capacitor as close as possible to the input and ground pins. 3. PC board traces with larger cross sectional areas will remove more heat from the ADP3334. For optimum heat transfer, specify thick copper and use wide traces. 4. Use additional copper layers or planes to reduce the thermal resistance. When connecting to other layers, use multiple vias if possible.
Shutdown Mode

Applying a TTL high signal to the shutdown (SD) pin or the input pin will turn the output off. Pulling SD down to 0.4 V or below or tying it to ground will turn the output on. In shutdown mode, quiescent current is reduced to much less than 1 A.

REV. B

ADP3334
OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8

8-Lead Mini Small Outline Package [MSOP] (RM-8)

Dimensions shown in millimeters
3.00 BSC

5 4

4.00 (0.1574) 3.80 (0.1497)

6.20 (0.2440) 5.80 (0.2284)

3.00 BSC
1 4

4.90 BSC

PIN 1

1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE

1.75 (0.0688) 1.35 (0.0532)

0.50 (0.0196) 45 0.25 (0.0099)

0.15 0.00

0.65 BSC 1.10 MAX 8 0 0.80 0.40

0.51 (0.0201) 0.33 (0.0130)

8 0.25 (0.0098) 0 1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075)

COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.38 0.22 COPLANARITY 0.10

0.23 0.08 SEATING PLANE

COMPLIANT TO JEDEC STANDARDS MO-187AA

8-Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body (CP-8)

Dimensions shown in millimeters
0.60 0.42 0.24 PIN 1 INDICATOR
1 2

3.00 BSC SQ 0.45 PIN 1 INDICATOR

TOP VIEW

0.60 MAX

2.75 BSC SQ

0.50 BSC 0.25 MIN

BOTTOM VIEW

1.50 REF

1.89 1.74 1.59

12 MAX 0.90 MAX 0.85 NOM SEATING PLANE 0.30 0.23 0.18

0.80 MAX 0.65 NOM 0.05 MAX 0.01 NOM 0.20 REF

1.60 1.45 1.30

DIMENSIONS SHOWN ARE IN MILLIMETERS

10

REV. B

ADP3334 Revision History

Location 3/03Data Sheet changed from REV. A to REV. B. Page

Edits to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added text to Output Voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Added Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Renumbered Figures 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1/03Data Sheet changed from REV. 0 to REV. A.

Added 8-Lead LFCSP and 8-Lead MSOP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Edits to product title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Removed pin numbers from Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added pinouts to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added text to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Added LFCSP Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Added Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated 8-Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

REV. B

11

12
C0261003/03(B)