Gate Drive Hexfet Power Mosfets
Gate Drive Hexfet Power Mosfets
Gate Drive Hexfet Power Mosfets
AN-937 (v.Int)
ID
The HEXFETis fundamentally different: it is a voltage-controlled power MOSFET device. A voltage must be applied between the gate and source terminals to produce a flow of current in the drain (see Figure 1b). The gate is isolated electrically from the source by a layer of silicon dioxide. Theoretically, therefore, no current flows into the gate when a DC voltage is applied to it though in practice there will be an extremely small current, in the order of nanoamperes. With no voltage applied between the gate and source electrodes, the impedance between the drain and source terminals is very high, and only the leakage current flows in the drain.
AN-937 (v.Int) When a voltage is applied between the gate and source terminals, an electric field is set up within the HEXFET. This field inverts the channel (Figure 2) from P to N, so that a current can flow from drain to source in an uninterrupted sequence of N-type silicon (drain-channel-source). Field-effect transistors can be of two types: enhancement mode and depletion mode. Enhancement-mode devices need a gate voltage of the same sign as the drain voltage in order to pass current. Depletion-mode devices are naturally on and are turned off by a gate voltage of the same polarity as the drain voltage. All HEXFETs are enhancementmode devices.
SOURCE METALLIZATION
INSULATING OXIDE
N SOURCE
GATE OXIDE
TRANSISTOR TRANSISTOR DRAIN DRAIN All MOSFET voltages are referenced to the source CURRENT CURRENT terminal. An N-Channel device, like an NPN transistor, has a drain voltage that is positive with respect to the source. Being enhancement-mode DIODE CURRENT devices, they will be turned on by a positive voltage Figure 2. Basic HEXFET Structure on the gate. The opposite is true for P-Channel devices, that are similar to PNP transistors. Although it is common knowledge that HEXFETtransistors are more easily driven than bipolars, a few basic considerations have to be kept in mind in order to avoid a loss in performance or outright device failure.
AN-937 (v.Int) 3 and 5. Figure 3 shows the waveforms of the drain current, drain-to-source voltage and gate voltage during the turn-on interval. For the sake of simplicity, the equivalent impedance of the drive circuit has been assumed as purely resistive.
DRAIN-SOURCE VOLTAGE
LOAD
DRAIN-SOURCE I
STRAY INDUCTANCE DRIVE CIRCUIT RESISTANCE G
VTH t 0 t1 t2 t3 t4
GATE-SOURCE VOLTAGE
SOURCE INDUCTANCE
VOLTAGE DROP ACROSS THIS L MEANS THAT THE DRAIN VOLTAGE FALL RESULTING IN DISCHARGE OF THIS CAPACITOR RESULTING IN MORE CURRENT THROUGH THIS RESISTANCE
DRIVE
+ IS
THIS INDUCED VOLTAGE SUBSTRACTS FROM THE DRIVE VOLTAGE RESULTING IN
G-S VOLTAGE "OPEN CIRCUIT" DRIVE PULSE t0 t1 t2 t4 GATE VOLTAGE GIVING I VTH t3
At time, t0, the drive pulse starts to rise. At t0 it reaches the threshold voltage of the HEXFETs and the drain current starts to increase. At this point, two things happen which make the gate-source voltage waveform deviate from its original path. First, inductance in series with the source which is common to the gate circuit (common source inductance) develops an induced voltage as a result of the increasing source current. This voltage counteracts the applied gate drive voltage, and slows down the rate of rise of voltage appearing directly across the gate and source terminals; this in turn slows down the rate of rise of the source current. This is a negative feedback effect: increasing current in the source produces a counteractive voltage at the gate, which tends to resist the change of current. The second factor that influences the gate-source voltage is the so called Miller effect. During the period t1 to t2 some voltage is dropped across unclamped stray circuit inductance in series with the drain, and the drain-source voltage starts to fall. The
AN-937 (v.Int) decreasing drain-source voltage is reflected across the drain-gate capacitance, pulling a discharge current through it, and increasing the effective capacitive load on the drive circuit. This in turn increases the voltage drop across the source impedance of the drive circuit, and decreases the rate of rise of voltage appearing between the gate and source terminals. Obviously, the lower the impedance of the gate drive circuit, the less this effect will be. This also is a negative feedback effect; increasing current in the drain results in a fall of drain-to-source voltage, which in turn slows down the rise of gate-source voltage, and tends to resist the increase of drain current. These effects are illustrated diagramatically in Figure 4. This state of affairs continues throughout the period t1 to t2, as the current in the HEXFETrises to the level of the current, IM, already flowing in the freewheeling rectifier, and it continues into the next period, t2 to t3, when the freewheeling rectifier goes into reverse recovery. Finally, at time t3 the freewheeling rectifier starts to support voltage and drain current and voltage start to fall. The rate of fall of drain voltage is now governed almost exclusively by the Miller effect, and an equilibrium condition is reached, under which the drain voltage falls at just the rate necessary for the voltage between gate and source terminals to satisfy the level of drain current estab-lished by the load. This is why the gate-to-source voltage falls as the recovery current of the freewheeling rectifier falls, then stays constant at a level corresponding to the drain current, while the drain voltage falls. Obviously, the lower the impedance of the gate-drive circuit, the higher the discharge current through the drain-gate self-capacitance, the faster will be the fall time of the drain voltage and the switching losses. Finally, at time t4, the HEXFETis switched fully on, and the gate-to-source voltage rises rapidly towards the applied open circuit value. Similar considerations apply to the turn-off interval. Figure 5 shows theoretical waveforms for the HEXFETin the circuit of Figure 4 during the turn-off interval. At to the gate drive starts to fall until, at tl , the gate voltage reaches a level that just sustains the drain current and the device enters the linear mode of operation. The drain-tosource voltage now starts to rise. The Miller effect governs the rate-of-rise of drain voltage and holds the gate-to-source voltage at a level corresponding to the constant drain current. Once again, the lower the impedance of the drive circuit, the greater the charging current into the drain-gate capacitance, and the faster will be the rise time of the drain voltage. At t3 the rise of drain voltage is complete, and the gate voltage and drain current start to fall at a rate determined by the gate-source circuit impedance.
VDS Q1
We have seen how and why a low gate drive VDS Q2 impedance is important to achieve high switching performance. However, even when A TRANSIENT switching performance is of no great concern, it ON THE GATE is important to minimize the impedance in the VGS Q1 gate drive circuit to clamp unwanted voltage transients on the gate. With reference to Figure 6, when one HEXFETis turned on or off, a step VGS Q2 of voltage is applied between drain and source of the other device on the same leg. This step of voltage is coupled to the gate through the gate-toFigure 6. Transients of Voltage Induced on the Gate by Rapid drain capacitance, and it can be large enough to Changes on the Drain-to-Source Voltage turn the device on for a short instant (dv/dt induced turn-on). A low gate drive impedance would keep the voltage coupled to the gate below the threshold.
AN-937 (v.Int) In summary: MOS-gated transistors should be driven from low impedance (voltage) sources, not only to reduce switching losses, but to avoid dv/dt induced turn-on and reduce the susceptibility to noise.
Logic Conditions
Logic Zero Min. sink current for VOL
(54LS) / 74LS (4) / 8 < (0.4V) / 0.5V -0.4mA > (2.5) / 2.7V 12ns
Logic One
Max. source current for VOH Typical Gate Propagation Delay -0.4mA >2.4V 10ns -0.5mA >2.4V 7ns
Table 1. Driving HEXFETs from TTL (Totem Pole Outputs) Open collector buffers, like the 7406, 7407, etc., possibly with several drivers connected in parallel as shown in Figure 9, give enough voltage to drive standard devices into full enhancement, i.e. data sheet on-resistance. The impedance of this drive circuit, however, gives relative long switching times. Whenever better switching performance is required, interface circuits should be added to provide fast current sourcing and sinking to the gate capacitances. One simple interface circuit is the complementary source-follower stage shown in Figure 9. To drive a MOSFET with a gate charge of 60 nC in 60 ns an average gate current of 1 A has to be supplied by the gate drive circuit, as indicated in INT-944. The on-resistance of the gate drive MOSFETs has to be low enough to support the desired switching times. With a gate charge of 60 nC and at a switching frequency is 100kHz, the power lost in the gate drive circuit is approximately: P = VGS x QG x f = 12 x 60 x 10 x 100 x 10 = 72mW The driver devices must be capable of supplying 1A without significant voltage drop, but hardly any power is dissipated in them.
-9 3
PULL-UP RESISTOR
VH
LOAD
AN-937 (v.Int) 2. 3. C-MOS can operate from higher supply voltages than 5V so that HEXFETsaturation can be guaranteed. Switching times are longer than those for TTL (Table 2). VH
12V
680
680 IRF320
7407 Figure 8. High Voltage TTL driver and its waveforms When C-MOS outputs are directly coupled to the gate of a HEXFET, the dominant limitation to performance is not the switching time, but the internal impedance (assuming that C-MOS are operated from a 10V or higher voltage supply). It will certainly not be able to turn OFF the HEXFETas fast as the TTL, while the turn-ON waveform will be slightly better than what can be achieved with a 7407 with a 680 ohm pull-up resistor. Of course, gates can be paralleled in any number to lower the impedance and this makes C-MOS a very simple and convenient means of driving HEXFETs. Drivers can also be used, like the 4049 and 4050 which have a much higher current sinking capability (Table 2), but they do not yield any significant improvement in current sourcing. For better switching speeds, buffer circuits, like the one shown in Figure 9, should be considered, not only to provide better current sourcing and sinking capability, but also to improve over the switching times of the CMOS output itself and the dv/dt noise immunity.
VH
LOAD
7 8 1 K 2 1
INPUT
7407 4 3
AN-937 (v.Int)
15V 5V Logic Conditions 5V 10V Logic Zero: 1.5mA 3.5mA 4mA 20mA Approximate sink current for VOL < 1.5V -0.5mA -13mA -3.4mA -1.25mA Logic One: > 4.6V > 9.5V > 13.5V > 2.5V Minimum source current for VOH Typical switching times of logic drive signals: 100ns 50ns 40ns 100ns RISE 100ns 50ns 40ns 40ns FALL Table 2. Driving HEXFET s from C-MOS (Buffered) When analog signals determine the switching frequency or duty cycle of a HEXFET, as in PWM applications, a voltage comparator is normally used to command the switching. Here, too, the limiting factors are the slew rate of the comparator and its current drive capability. Response times under 40ns can be obtained at the price of low output voltage swing (TTL compatible). Once again, the use of output buffers like the ones shown in Figures 9, may be necessary to improve drive capability and dv/dt immunity. If better switching speeds are desired. a fast op-amp should be used. In many applications, when the HEXFET is turned on, current transfers from a freewheeling diode into the HEXFET. If the switching speed is high and the stray inductances in the diode path are small, this transfer can occur in such a short time as to cause a reverse recovery current in the diode high enough to short out the dc bus. For this reason, it may be necessary to slow down the turn-on of the HEXFETwhile leaving the turn-off as fast as practical. Low impedance pulse shaping circuits can be used for this purpose, like the ones in Figures 12 and 13.
+12V
VH
LOAD IRF7309 OR IRF7509 FET INPUT OP AMP INPUTS + 4 -12V 5 6 3 0.1 F CER 7 8 2 1
+12V
+ 4
3 0.1 F CER 5 6
AN-937 (v.Int) basically three ways of developing a gate drive signal that is referenced to a floating point: 1. 2. By means of optically coupled isolators. By means of pulse transformers.
LOAD
Figure 12. A pulse shaper. The 555 is used as an illustration of a Schmitt Trigger pulse shaper
VH
LOAD C 7 8 2
R CA3103
INPUT
+ 4 C 5 6
Figure 15a shows an MGD with under-voltage lockout and negative gate bias. When powered with a 19 V floating source, the gate drive Figure 13. Pulse shaper implemented with an integrator voltage swings between +15V and 3.9V. D1 and R2 offset the emitter voltage by 3.9V. The switching waveforms shown in Figure 15b are similar to those in Figure 14b except for the negative bias. Q3, D2 and R5 form the under voltage lockout circuit. The LED D2 is used as low voltage, low current reference diode. Q3 turns on when the voltage at the anode of D2 exceeds the sum of the forward voltage of LED and the base-emitter voltage of Q3. This enables the operation of the optocoupler. The tripping point of the under voltage lock-out circuit is 17.5V. The start-up wave forms are shown in Figure 16.
AN-937 (v.Int)
BATT1 15V
8 7 6 5 C1 0.1
3 + C2 10 5 6 3.9V EMITTER
VEE
Figure 14a. Simple high current optoisolated driver The auxiliary supply for the optocoupler and its associated circuitry can be developed from the drain voltage of the MOSFET itself, as shown in Figure 17, 18 and 19. This supply can be used in conjunction with the UV-lockout shown in Figure 15 to provide a simple high-quality optoisolated drive. The circuit in Figure 17a can be modified to provide higher output current. By changing C1 to 680pF and R3 to 5.6k, its performance changes to what is shown in Figures 20, 21 and 22. Other methods of developing isolated supplies are discussed in Section 9.
Input: 5V/div
BATT1 19V
IN+
R1 3.3k
C2 10 D1 3.9V
IN-
VEE
HCPL2200
Figure 15a: Optoisolated driver with UV lockout and negative gate bias
AN-937 (v.Int)
Output : 5V/div
FILE: 01A-POL.DAT Horiz: 500ns/div Figure 15b: Waveforms of the circuit in Figure 21a when loaded with 100nF
Horiz: 20ms/div File: 01-UV.dat Figure 16. Start-up waveforms for the circuit of Figure 15a.
Gate Voltage: 10V/div
VCC(300V) Q1 IRF840 R1 DRIVE 10 DRVRTN Q2 IRF840 R4 R 15VRTN R2 100 D1 1N4148 C2 0.1 D3 15V C1 D2 1N4148 R3 +15V
Figure 17b. Waveforms of the circuit in Figure 23a.C1 = 100 pF, R3 = 5.6 k, f = 50 kHz
2 C2 voltage: 5V/div.
Figure 18. Zener current (max output current) for the circuit in Figure 23a.
Horiz.: 500s/div File: GPS-3.PLT Figure 19. Start-up voltage at 50 kHz for the circuit in Figure 23a.
AN-937 (v.Int) They have the additional advantage of providing a negative gate bias. One additional limitation of pulse transformers is the fact that the gate drive impedance is seriously degraded by the leakage inductance of the transformer. Best results are normally obtained with a few turns of twisted AWG30 wire-wrap wire on a small ferrite core. Lower gate drive impedance and a wider duty-cycle range can be obtained with the circuit in Figure 24a. In this circuit, Q1 and Q2 (a single Micro-8 package) are used to buffer the input and drive the primary of the transformer. The complementary MOS output stage insures low output impedance and performs wave shaping. The output stage is fed by a dc restorer made by C2 and D1 that references the signal to the positive rail. D1 and D2 are also used to generate the gate drive voltage. The input and output wave form with 1nF load capacitance are shown in Figure 24b. The turn-on and turn-off delays are 50ns. The rise and fall times are determined by the 10 Ohm resistor and the capacitive load. This circuit will operate reliably between 20 and 500 kHz, with on/off times from 0.5 to 15 microsecs.
20 Gate voltage: 10V/div. Zener Current (mA)
10
C2 ripple voltage: 1V/div 0 Horiz: 2s/div 10 File: gps-4.plt 20 30 40 50 60 70 Frequency (kHz) 80 90 100
Figure 20. Waveforms of the circuit in Figure 23a. with C1=680pF, R3=1k, f=100kHz.
Figure 21. Zener current (max output current) for the circuit in Figure 23a. with C1 = 680pF, R3 = 1k
C2 voltage: 5V/div
VGS 0
Figure 22. Start-up voltage at 100 kHz for the circuit in Figure 23a. with C1=680pF, R3=R3=1k Due to the lack of an under voltage lock-out feature, the power-up and power down behavior of the circuit is important. Intentionally C1 and C2 are much bigger in value then C3 so that the voltage across C3 rises to an adequate level during the first incoming pulse. The power-up wave forms at 50kHz switching frequency and 50% duty cycle are shown in Figure 25. During the first pulse, the output voltage is 10V only, and drops back below 10V at the fifth pulse.
AN-937 (v.Int)
D1 IN4148
2 3 Q3
1 C1 T1 C2 1
R2 10 R3 G
Q4
3 2
D2 5 6
IN4148 IRFL014 OR IRFD014 T1: CORE: 331X1853E2A A1=2600 (PHILIPS, OD=0.625", Ae=0.153CM^2) PRIMARY: 17T, SEC.: 27T
Input: 5V/div.
Output: 5V/div.
HORIZ: 50S/div.
FILE: X2-START.PLT
Figure 25. Waveforms during start-up for the circuit in Figure 24a.
R3 8.2K 8 7 6 5 R4 220
D5 C 11DF6 R2 1K G
FAULT CS COM VS
IR2127/8
C5 10n E
T1: CORE: 331X185 3E2A, A1=2600 (OD=0.625", Ae=0.153 CM^2) PRIMARY: 17T, AWG 28 SEC: 27T, AWG 28
AN-937 (v.Int) The power down of the circuit is smooth and free from voltage spikes. When the pulse train is interrupted at the input, the C2 capacitor keeps the input of the CMOS inverter high and R1 discharges C3. By the time the input to the CMOS inverter drops below the threshold voltage of Q4, C3 is completely discharged the output remains low. The addition of a MOS-Gate Driver IC improves the performance of the circuit in Figure 24a, at the expenses of prop delay. The circuit shown in Figure 26a has the following features: - No secondary supply required - Propagation delay ~500ns (CL= 10nF) - Duty cycle range 5% to 85% - Nominal operating frequency 50kHz (20kHz to 100kHz) - Short circuit protection with Vce sensing. Threshold Vce = 7.5V - Undervoltage lock-out at Vcc = 9.5V - Over voltage lock out at Vcc = 20V
Output: 5V/div.
The short circuit protection is implemented with a Vce sensing circuit in combination with the current sense input (CS) of IR2127/8. When the HO pin if U2 goes high R3 starts charging C5. Meanwhile the IGBT turns on, the collector voltage drops to the saturation level, D5 goes into conduction and C5 discharges. When the collector voltage is high, D5 is reverse biased and the voltage on C5 keeps raising. When C5 voltage exceeds 250mV the IR2127/8 shuts down the output. The fault to shut-down delay is approximately 2 microsecs. For operation with a large duty cycle, several options are available. The circuits described in AN-950 use a saturating transformer to transfer the drive charge to the gate. The circuit shown in Figure 28a, on the other hand, achieves operation over a wide range of duty cycles by using the MGD as a latch. It has the following features: - Frequency range from DC to 900kHz. - Turn-on delay: 250ns. - Turn-off delay 200ns - Duty cycle range from 1% to 99% at 100kHz. - Under voltage and over voltage lockout. - Optional short circuit protection, as shown in Figure 26a In the circuit of Figure 28a the transformer is small (8 turns), since it transmits only short pulses to the secondary side. The MGD on the secondary side of the transformer is latched by the feedback resistor R4. Figures 28b and 28c show the performance of this circuit at the two extremes of 900 kHz and 2.5 Hz
AN-937 (v.Int)
IRF7509 OR IRF7309 +12V 7 8 C1 1 IN 4 3 1nF R1 560 5 12VRTN TRANSFORMER: CORE: 266CT125-3E2A, (OD=0.325", Ae=0.072cm,^2, A1=2135) PRIMARY: 8T, AWG 28 SEC: 8T, AWG 28 6 2 1 C2 R2 T1 4.7K R3 18K 1 2 3 4 R4 18K U1
VCC IN ERR VSS VB HO CS VS
+15V 8 7 6 5
R5 18K G C3 1 E 15VRTN
IR2121
Output: 10V/div.
Reference 60Hz: 10V/div. Output: 25.ns/div. Horiz.: 25.ns/div. File: XP-900K.PLT Horiz: 50ms/div. File: XP-2P5HZ.PLT
Figure 28b. Waveforms associated with the circuit of Figure 28a operated at 900 kHz
Figure 28c. Waveforms associated with the circuit of Figure 28a operated at 2.5 Hz
AN-937 (v.Int) Logic level HEXFETs are specifically designed for operation from 5V logic and have guaranteed on-resistance at 5 or 4.5 V gate voltage. Some have guaranteed on-resistance at 2.7 V. Some important considerations for driving logic level HEXFETs are discussed in this section and typical switching performance of these is illustrated when driven by some common logic drive circuits.
While input characteristics are different, reverse transfer capacitance, on-resistance, drain-source breakdown voltage, avalanche energy rating, and output capacitance are all essentially the same. Table 3 summarizes the essential comparisons between standard and logic level HEXFETs.
Logic level HEXFET has same value of RDS(on) VGS = 5V as standard HEXFETat VGS = 10V RDS(on) of logic level HEXFET also speed at VGS = 4V Typically 39% larger for logic level HEXFET Typically 33% larger for logic level HEXFET Essentially the same Essentially the same Essentially the same Essentially the same Essentially same as VGS = 10V
Same ID Same EAS + 20V +10V VGS Table 3: Essential Comparisons of Standard and Logic Level HEXFETs
The gate charge for full enhancement of the logic level HEXFETis, however, about the same as for a standard HEXFETbecause the higher input capacitance is counteracted by lower threshold voltage and higher transconductance. Since the logic level HEXFETneeds only one half the gate voltage, the drive energy is only about one half of that needed for the standard HEXFET. Since the gate voltage is halved, the gate drive resistance needed to deliver the gate charge in a given time is also halved, relative to a standard HEXFET. In other words, for the same switching speed as a standard HEXFETpower MOSFET, the drive circuit impedance for the logic level HEXFETmust be approximately halved. The equivalence of switching times at one half the gate resistance for the logic level HEXFETis illustrated by the typical switching times for the IRL540 and the IRF540 HEXFETs shown in Table 4, using data sheet test conditions.
AN-937 (v.Int)
Gate Resistance
RG () 9 4.5
Gate Voltage
Drain Current
VGS tr tD on ID tD on (V) (A) 10 28 15 72 40 5 28 15 72 44 Table 4: Typical Resistive Switching Times for IRL540 and IRF540
TTL families do not actually deliver 5V in their VOH condition, even into an open circuit. The 5V level can, however, be reached by the addition of a pull-up resistor from the output pin to the 5V bus, as illustrated in Figure 30. Without the pull-up resistor, the RDS(on) value at VGS = 5V may not be attained, and the value specified at VGS = 4V should be used for worst case design.
CONTROL INPUT
15 V +5V
4 8 7 3 555 2 5 8
RET
Figure 30. Pull-up resistor used to deliver 5V gate drive Figure 29.
LS
LS
S LW
RET.
AN-937 (v.Int) Common source inductance plays a significant role in switching performance. In the circuit of Figure 31a the switching performance is degraded due to the fact that VGS is reduced by (LS + LW) di/dt, where di/dt is the rate of change of the drain current. By eliminating LW from the drive circuit, VGS can approach the applied drive voltage because only LS (the internal source inductance) is common. This can be done by separately connecting the power return and the drive signal return to the source pin of the switching HEXFET, as shown in Figure 31b. Thus, the load current ID does not flow through any of the external wiring of the drive circuit; consequently, only the internal source inductance LS is common to both load and drive circuits. In the case of logic level HEXFETs, for which VGS is 5V and not 10V, the loss of drive voltage due to common mode inductance has proportionately twice the effect as it would on a 10V drive signal, even though actual values of LS and LW are the same.
15
Figure 32. Switching test circuit. Logic level driver is one-quarter of a quad NAND gate. Only the 5 volt families have been tested as logic level HEXFETdrives: bipolar and CMOS (and their derivatives), as indicated below. TTL GATES DM7400N: 74F00PC: DM74S00N: DM74LS00N: DM74AS00N: Standard TTL High Speed TTL Schottky TTL Low Power Schottky TTL Advanced Schottky TTL
AN-937 (v.Int) CMOS GATES 74AC00PC: 74ACT00PC: MM74HC00N: MM74HCT00N: Advanced CMOS TTL Compatible CMOS Micro CMOS TTL Compatible Micro CMOS
The test conditions for the resistive switching performance is shown in Table 5. The resistive switching times obtained with the above TTL and CMOS gates are tabulated in Table 6. In this table ton = Time in microseconds from 90% to 10% VDD and toff = Time in microseconds from 10% to 90% VDD. Inductive switching gives faster voltage rise times than resistive switching due to the resonant charging of the output capacitance of the device. Voltage fall times are essentially the same.
RDSON ( )
0.24 0.12 0.06 0.034 0.60 0.30 0.18 0.085
RL ( )
3.25 1.5 1.2 0.7 9.5 5.9 4.0 1.9
Logic Level HEXFET, IRLZ34 IRLZ44 IRL514 IRL524 ton toff ton toff ton toff ton toff
0.700 0.429 0.503 0.706 0.446 0.125 0.125 0.227 0.227 0.014 0.076 0.068 0.032 0.146 0.023 0.027 0.016 0.147 0.123 0.007 1.491 0.863 1.068 1.438 0.896 0.251 0.233 0.508 0.504 0.032 0.146 0.146 0.142 0.342 0.149 0.139 0.127 0.328 0.269 0.016 0.151 0.104 0.116 0.155 0.111 0.036 0.033 0.058 0.068 0.021 0.022 0.004 0.006 0.040 0.005 0.004 0.044 0.044 0.035 0.004 0.238 0.159 0.183 0.240 0.161 0.052 0.052 0.092 0.092 0.036 0.041 0.034 0.041 0.062 0.127 0.028 0.027 0.068 0.051 0.004
Typical Test Oscillograms IRLZ24: 60V, 0.1 Ohm, N-Channel, TO-220 logic level HEXFETwas driven by each of the logic families listed in Table 4 and the comparative resistive switching times photographed.
AN-937 (v.Int)
+12V
V0
1F RL
CD4093
f = 100kHz (OD = 0.75", Ae=0.148CM^2, AI=3000) PRIMARY: 14 TURNS, AWG 30 TEFLON INSULATED WIRE SECONDARY: 24 TURNS, AWG 30 TEFLON INSULATED WIRE
SMALL SIZE. To reduce the interwinding capacitances the transformer must be made small. This implies operation at high frequency. Small size and compact layout help reducing the EMI and RFI generated by the converter. Figure 33a shows a forward converter made with two CD4093 gates to generate the clock and drive the MOSFET. Energy as transferred to the secondary when the MOSFET is on, in about 33% of the cycle. When the MOSFET is off, the secondary winding is used to demagnetize the transformer and transfer the magnetizing energy to the load, thus eliminating the need for a demagnetizing winding. The switching waveforms are shown in Figure 33b. The ringing in the drain voltage during the fly-back period is due to the loose coupling between the primary and the secondary windings. The load current vs. output voltage characteristic of the circuit is shown in Figure 34. When the output current falls below 5 mA, the circuit works as flyback converter because the demagnetizing current flows through the output. A minimum load of 5mA is required to limit the output voltage at 15V.
35 Drain voltage: 10V/div. 30 Output Voltage (V) Gate voltage: 5V/div. Horiz: 2s/div. 25
20 15
Figure 34. Load current vs. output voltage at 100 kHz, Rout = 27.7 Ohms
AN-937 (v.Int) If the converter is loaded with a 4X constant and predictable load, a zener IN4148 V0 +12V can provide the necessary regulation. T1 14 1 1F 3 1K 1N4148 Otherwise a three-terminal regulator 2 or a small zener-driven MOSFET may IRFD110 9 6K be necessary. 10 1F 8 The circuit in Figure 35a is similar to 100 RL 13 5 the previous one, except that the 11 4 6 12 higher switching frequency is higher (500 kHz) and the transformer is f = 500kHz 220p smaller. The remaining three gates in 7 CD4093 12V the package are connected in parallel RTN to drive the MOSFET and reduce the T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135 switching losses. The switching waveforms are shown in Figure 35b. PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30 The output resistance (Rout) of this Figure 35a. 500 kHz Forward converter circuit is higher than the circuit shown in Figure 33a, mainly because the stray inductance of the smaller transformer is higher and the effects of the stray inductance are higher. Figure 37a shows a pushpull operated at 500 kHz. The single gate oscillator produces a 50% duty cycle output, while the remaining gates in the package are used to drive the push-pull output stage. The primary of the transformer sees half the voltage compared to the previous circuit, therefore the number of turns at the primary were reduced to half.
30 Drain Voltage: 10V/div. 25 Output voltage (V) Gate voltage: 5V/div. Horiz.: 250ns/div.
20
15
Figure 36. Load current vs. output voltage, Rout = 27.7 Ohms
AN-937 (v.Int) In the case of the MOSFET, there is the possibility that, for low current levels, the current flows through both MOSFET channels, instead that one MOSFETs and diode, thereby achieving lower overall voltage drop. The MOSFET channel is a bidirectional switch, that is, it can conduct current in the reverse direction. If the voltage across the MOSFET channel is less than the VF of the intrinsic diode (which typically has a higher VF than discrete diodes), then the majority of the current will flow through the MOSFET channel instead of the intrinsic diode. The gate drive for both the MOSFETs and IGBTs must be referenced to the common sources or emitters of the devices. Since this node will be swinging with the AC waveform, an isolated drive is necessary. The PVI can be used, as shown in Figure 40.
7, 8 100nF 100nF T1 1 3 7T 2T 5, 6
1N4148
V0
1F
RL
IRF7307
7 f = 500kHz
1N4148 T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135 PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30
Horiz.: 500ns/div Figure 37b. Waveforms associated with the circuit in Figure 37a
20 19 18 17 16
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