Haps70 Brochure
Haps70 Brochure
Haps70 Brochure
`` High-Speed
Time-Domain Multiplexing and Enhanced HapsTrak 3 Connector Deliver Ultra Fast Prototype Performance System Architecture Scales from 144 Million ASIC Gates Multi-FPGA Partitioning by up to 10x
`` Modular
`` Accelerate `` Enhanced
Universal Multi-Resource Bus Host Connectivity of up to 400MB/s Trace Debug Increases Signal Tracing Capacity by 100X Synopsys DesignWare IP
`` Deep
`` Pre-validated
Overview
Todays ASIC IP and SoC design teams face the dual challenge of very short delivery schedules and high risk of their product being rejected by the market if chip designs ship with defects. Synopsys FPGA-based prototyping solution enables a more parallel hardware/software development strategy where software developers, validation engineers, and system integration experts have access to prototypes running at near real time speed months before tape-out of new ASIC silicon. FPGA-based prototypes are ideal for pre-silicon software development, system validation, and hardware/software integration of ASIC IP and SoC designs. Prototyping teams benefit from an easyto-use flow from ASIC RTL to the FPGA-based prototype, high debug visibility, and a scalable hardware architecture to support and streamline IP and SoC system level validation. Synopsys High-Performance ASIC Prototyping System HAPS-70 with Symmetrical System Architecture (SSA) offers the best system performance, reliability, and design automation in the industry. `` Enhanced HapsTrak 3 I/O connector technology with highspeed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing `` Modular system architecture scales from 12-144M ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs `` Design planning tools reduce time-to-prototype by 2-3 months streamlining transition from block level IP validation to full system integration `` New capability in Synopsys Certify software in combination with HAPS flexible interconnect architecture accelerates multiFPGA partitioning by up to 10x `` Enhanced Universal Multi-Resource Bus (UMRBus) host connectivity of up to 400MB/s facilitates debug and increases hybrid prototyping performance with Synopsys Virtualizer `` Pre-validated Synopsys DesignWare IP with HAPS systems enables efficient integration of small IP blocks and earlier software development `` System definition and bring-up utilities speed hardware assembly and ensure the prototypes electro-mechanical integrity `` Improve debug efficiency with 100x greater visibility and 8x faster download time of debug trace buffer data The HAPS-70 SSA is designed to provide a near seamless integration path for single-FPGA IP module to be integrated into a system of multi-FPGA SoC modules maximizing prototype reuse across engineering teams. SSA enables a bottom-up ASIC-like design flow for high-capacity FPGA-based prototypes by allowing lower capacity HAPS-70 design project constraints and optimization options to be reused in the context of a higher capacity target. This modular approach is enabled by the mechanical symmetry of the PCB and connector layout of the HAPS-70 system and project flows automated by the Synopsys Certify Multi-FPGA Design Environment. In both IP and SoC usage modes, the solution delivers unparalleled performance, ease of use, debug visibility, and system control. High prototype performance is delivered by the industry leading Behavioral Extraction Synthesis Technology (B.E.S.T.) of Synopsys Synplify
8 8
Premier combined with the automated pin multiplexing and Swarm Intelligence Partition Engine (SWIPE) of Certify. To help solve the toughest interconnect problems, Certify takes advantage of the Virtex-7 family SerDes I/O channels to route multiple signals using high-speed time-domain multiplexing (HSTDM) at greater than 1Gbit/s data rates.
usage, and rubber banding of connections. The interactive displays allow you to manage both the RTL design and the electro-mechanical elements of the HAPS-70 system hardware. Automate repetitive tasks and project processing with the Tcl command interface. Ensuring a fast and automated path to a partitioning solution the integrated HAPS-70 System Aware Certify software employs a second generation automated partitioner, Swarm Intelligence Partition Engine (SWIPE) with pin-reduction algorithms to implement HSTDM of I/Os. All of the HAPS-70 I/Os are HSTDM capable delivering faster convergence on a partitioning solution while maximizing system performance.
design, users have as much as 100x additional design visibility by utilizing off-chip, external memory storage. Sample results are available quickly over the high-performance HAPS Universal MultiResource Bus (UMRBus) Interface Pod link between the debugger workstation and the HAPS-70 system. During the early phases of ASIC prototyping, fast turnaround time between debug sessions is required and realized by Identifys Mux Groups feature. When greater depth of signal capture is required at higher system speeds, the HAPS Deep Trace Debug capability ensures multi-megabyte of signal storage while maintaining the at-speed performance required by the hardware/software development and validation teams.
Prototype design debug is given a new level of visibility when utilizing HAPS cycle accurate co-simulation capability with VCS and other popular simulators. In this simulator controlled debug session, the user picks blocks of the design to reside in HAPS with the remaining elements co-simulated within the RTL simulator. The blocks within simulation maintain 100% RTL debug visibility while interacting at a cycle by cycle level with the rest of the design implemented within HAPS. The UMRBus enables co-simulation for hierarchical block level bring-up and debug to ensure that the SoC level prototype is available earlier in the design cycle. Validate individual RTL blocks as soon as they become available in the context of their golden simulation regression testbenches utilizing cosimulation with HAPS. Unmodified testbench code can be utilized to exercise the encapsulated RTL block executing cycle accurately in HAPS. As a portion of the design is running within the simulator, non-synthesizable testbench tools such as verification IP can be utilized as part of the validation and bringup steps.
DUT
...
Module n Module n
Module 1 Module 1
...
Module n
PLI interface
The creation of user defined bus monitors and protocol checkers is simplified by leveraging the automated flow, non-intrusive and zero pin overhead of the UMRBus Client Application Interface Modules (CAPIMs). These UMRBus RTL building block modules provide the basis of user defined debug to stimulate and monitor
Design interaction and monitoring Memory preload and readback System conguration
modules that enable the user to interact with the HAPS-70 system through the provided UMRBus application programming interface. This API enables design interaction via simple TCL or the building of more complex analysis tools via the C++ documented interface.
Prototyping use modes System monitoring Co-simulation Hybrid prototyping Transactionbased validation
Bus monitoring
UMRBus
Figure 5: UMRBus Interface
High Performance Features Include: `` Enhanced FPGA-Module for high-speed signaling `` HapsTrak 3 connector technology with significant performance improvements making it easy to support high performance I/O interfacing to components such as DDR3-1333 `` High-performance HapsTrak 3 interconnect cables for highspeed interconnectivity between FPGAs and systems `` Access to sixteen multi-gigabit channels per Xilinx Virtex-7 2000T FPGA providing direct access to high speed transceivers `` Improved system stability with advanced power and thermal management
IP validation MIPI Graphics Processor Display L1 L2 ICT SD controller Sensor processor Peripherals Audio processor Memory controller Power and clocks HDMI USB 3.0 SIM card controller I/O processor IP interface L1 Video V7 2000T
SoC/system validation
V7 2000T
Video
V7 2000T
V7 2000T
V7 2000T
Interface
HAPS-70 Prototyping System Highlights `` Support for IP and SoC Designs up to 144M ASIC gates `` New HapsTrak 3 connector technology for high speed I/O interfaces `` Modular and scalable architecture from 1 to 12 FPGAs `` Highest flexibility with 1126 user accessible I/Os per FPGA module `` Unique low latency host system communication for highspeed data transfer `` Gigabit transceiver support up to 10.5 Gbps
HAPS-70 S12 FPGA Type Number of FPGAs ASIC Gate Capacity I/O Connectors HapsTrak 3 User Accessible I/O Resources High Speed I/O Transceivers Routing Granularity Clock Resources Debug Modes Daughter Board Portfolio Prototyping Use Modes System Control Software Configuration Encryption Key Power 1 Up to 12M 23
HAPS-70 S24
HAPS-70 S36
HAPS-70 S48
HAPS-70 S60
HAPS-70 S72
HAPS-70 S96
HAPS-70 S120
HAPS-70 S144
Virtex-7 XC7V2000T 2 Up to 24M 46 3 Up to 36M 69 4 Up to 48M 92 5 Up to 60M 115 6 Up to 72M 138 8 Up to 96M 184 10 Up to 120M 230 12 Up to 144M 276
1126
2252
3378
4504
5630
6756
9008
11260
13512
16
32
48
64
80
96
128
160
192
50 I/Os per connector, variable voltage region (1.8 V, 1.5 V, 1.35 V, 1.2 V) per connector
2 PLLs, 2 external PLL inputs, 2x2 external PLL outputs, 2x6 clock input and outputs, frequency range from 5 MHz to 200 MHz, clock stopping support RTL Level Debug, Sample Mux Groups, Multi-FPGA Distributed Debug, Deep Trace Debug PCIE Gen 2, SATA, Ethernet, DDR3-1333, DDR2, SRAM, FLASH, MSDRAM, MICTOR
JTAG, USB 2.0, Parallel Flash, SD Card, UMRBus via Configuration and Data Exchange (CDE) interface Battery backup support 110-240 AC, 12V
Table 1: HAPS-70 Series Features
L2 cache controller Interconnect UARTs GPIOs RTC Timers Watchdog Interface Generic Battery Keyboard/ Mouse Interface DesignWare Ethernet Embedded memories Color LCD Controller DesignWare USB 3.0
Reference SW stack
VCK analyzer
The enhanced UMRBus is capable of supporting up to 400 MB/s of high speed connectivity to ensure a high performance and very low latency link between virtual prototypes (Virtualizer) and HAPS FPGA-based prototyping systems.
Pre-validated DesignWare IP
The HAPS-70 system supports Synopsys DesignWare IP enabling digital controllers and mixed signal DesignWare PHY daughter boards to be rapidly integrated. All DesignWare IPs are validated on HAPS systems ensuring no last minute interoperability issues providing reduced risk and effort allowing users the capability to start firmware and software development earlier in the product development cycle. For more information about Synopsys products, support services or training, visit us on the web at: www.synopsys.com, contact your local sales representative or call 650.584.5000.
Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 www.synopsys.com 2012 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners. 10/12.CE.CS2269.