of Principles of Cmos Vlsi Design
of Principles of Cmos Vlsi Design
of Principles of Cmos Vlsi Design
Grading Policy
Mid-terms + quizzes + hw will account for 75% of the grade
3 mid-terms Mandatory and has to be taken on the scheduled day of the exam.
Project will account for 25% of the grade. Late projects will not be accepted. You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above. Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing g y g grade. Instructor reserves right to change project requirements.
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Text:
Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall, Second edition
References:
Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley Circuits, Interconnects, and Packaging for VLSI, H. Bakoglu, Addison Wesley
Class Notes:
http://www.ece.purdue.edu/~vlsi/ee559/20001
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Course Outline
Introduction: Historical perspective and Future Trend Semiconductor Devices CMOS Logic Layout techniques Logic, MOS devices, SPICE models Inverters: transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters Designing combinational logic gates in CMOS
Static CMOS design: Complementary CMOS, ratioed logic, pass-transistor logic Dynamic CMOS logic
Designing sequential circuits Interconnect and timing issues Designing memory and array structures Designing arithmetic building blocks VLSI testing and verification S f
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Lab URL
http://min.ecn.purdue.edu/~mgcdevel/ee559_lab.html
Course Project
Complete design of a functional logic block or system
Complexity of 1000+ transistors or novelty Design using the CADENCE tools and HSPICE
Design your own library from scratch
Functionality to be verified Critical path timing should be verified using HSPICE Project report due the last day of class Project presentation by each group in the last week of class Work in a group of 2 will be allowed in special cases Start early! Emphasis on new ideas, power dissipation, performance, reconfigurability, low voltage design
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V=0
SOURCE
DRAIN
Leff
Tox
V=Vmin=Ebmin Eb
Vg
Vd
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The Babbage Differential g Engine (1834) 25,000 mechanical parts Cost 17,470
Reliability issues and excessive power consumption Did not go far until the invention of the transistor at Bell Lab in 1947
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HISTORY
MOS field-effect transistor: Lilienfeld (1925), Heil (1935) Bipolar transistors: Bardeen (1947), Schockley (1949) First Bipolar digital logic: Harris (1956)
IC Logic family:
Transistor-Transistor Logic (TTL) (1962) Emitter-Coupled Logic (ECL) (1971) Integrated Injection Logic (I2L) (1972)
PMOS and NMOS transistors on the same substrate: Weimer ( (1962), Wanlass (1965) ), ( ) PMOS-only logic until 1971 when NMOS technology emerged NMOS-only logic until late 1970s, when CMOS technology took over Later developments: BiCMOS, GaAs, low-temperator CMOS, super-conducting technologies, Nano-electronic
5 m
1 m
100 nm
I ON ~ 102~6 I OFF
Drain
n+
n+
Junction leakage
Bulk
1.5
0.7
Technology ()
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Technology Trend
Fully-depleted body
VG
Nano devices
VD
Bulk-CMOS
VG VS Gate VD Source Floating Body Drain
VS Source
Gate
Drain
DGMOS
FD/SOI
FinFET
Trigate
PD/SOI
Multi-gate devices
Things Manmade
Head of a pin 1-2 mm
The Challenge
Ant ~ 5 mm
10-3 m
0.1 0 1 mm 100 m
Microworld
10-5 m
0.01 mm 10 m
Infrared
O O
Pollen grain Red blood cells Zone plate x-ray lens Outer ring spacing ~35 nm
10-6 m
Smaller is different!
10-7 m
Nanoworld
Ultraviolet
Fabricate and combine nanoscale building blocks to make useful devices, e.g., a photosynthetic reaction center with integral semiconductor storage.
10-8 m
0.01 m 10 nm
10-9 m
Soft x-ray
1 nanometer (nm)
More is different!
DNA ~2-1/2 nm diameter Atoms of silicon spacing ~tenths of nm 10-10 m 0.1 nm Quantum corral of 48 iron atoms on copper surface positioned one at a time with an STM tip Corral diameter 14 nm
Office of Basic Energy Sciences Office of Science, U.S. DOE Version 10-07-03, pmd
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Device 1
Device 2
1 .3 1 .2
30%
130nm
1 .1 1 .0 0 .9
Source: Intel
5X
1 2 3 4 N o rm a liz e d L e a k a g e ( Is b ) 5
Channel length
# dopant atoms
Source: Intel
1000 100 10
1000 500 250 130 65 32
Reliability
Temporal degradation of performance -- NBTI
Failure probability y
Tech. generation
Time Defects Interface trap generation over time Life time Lif ti degradation
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I ON = 10 4 I OFF
Pentium proc
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Nano-Scaled Si Devices
Si Fin
DGMOS
Planar double-gate structure
FinFET or Tri-Gate
Quasi-planar DG structure
Bulk Si MOSFETs
30%
130nm
1 .1 1 .0 0 .9 1 2 3
Source: Intel S I t l
5X
4 5
Leakage (normalized)
10000
Source: Intel
1000 100 10
1000 500
250 130
65
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Evolution in Complexity
Processor Trends
800 700 600 500 400 300 i386 200 100 0 i386C-33 HP PA8000 UltraSparc-167 PPro 150 PPro-150 MIPS R10000 SuperSparc2-90 A21164-300 HP PA7200 PPro200 Die Size (mil2) PPC 604-120 A21064A MIPS R4400 PP-100 PPC 601-80 486-66 i486C-33 DX4 100 PP-133
PP-66 PP 66
'91
'93
'94
'95
'96
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200 Freq(MHz)
M R4400 IPS
HP PA8000 UltraSparc-167
150
PP166 PPro-150
50
Higher Performance: Higher Frequencies (2x/Generation) Higher Device counts (2x /Generation)
Power Trends
40 35 30 25 Power(W) 20 15 10 5 0 PP-66 PPC 601-80 i486C-33
'91
A21164-300
HP PA8000
SuperSparc2-90 PPC 604-120 MIPS R4400 PP-100 PP-133 MIPS R5000 PP166
PPC603e-100
'95 '96 [Source: Microprocessor Report]
i386 i386C-33
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Heat Dissipation
Chips fail when they get hot Need compact and cost-effective cooling solns p g
CPU 486/33mhz 486DX2 66mhz Pentium 66mhz Thermal Soln Cost HeatSink $0.50 Heatsink $1.00 Larger Heatsink $2.00 System Fan $4.00
CPU Power increasing (Predicted in 1994 Low power workshop) Graphics & Chipset Power increasing faster than predicted
Power reduction is not only a CPU problem
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Dunnington is the first IA (Intel Architecture) processor with 6-cores, is based on the 45nm high-k process technology, and has large shared caches.
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Technology (um) T h l ( ) Year # transistors On-Chip Clock (MHz) Area (mm2) Wiring Levels
Technology (um) 2cm line delay (ns) 1mm line delay (ns)
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Interconnect Complexity
Technology (um) Length (m) Wiring Levels Opt. # buffers per net Opt. # wiresizes per net Opt. # buffers per chip 0.25 0.18 820 1,480 6 6-7 6 few few 5K 25K 0.13 2,840 7 0.10 5,140 7-8 8 0.07 10,000 8-9 89 many many 230K 797K
54K
Nu umber of Interconnect ts
0.07 um tech.
1E+00
10
20
30
Length (mm)
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Technology Scaling
Technology scaling improves: Transistor & interconnect performance Transistor density Energy consumed per switching transition 0.7X scaling factor (30% scaling) results in: 30% gate d l reduction (43% f t delay d ti freq. ) 2X transistor density increase (49% area ) Energy per transition reduction
Technology Scaling
Speed & Performance
High drive current and low parasitics Low gate delay and high frequency
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D=
scales
0.7
= 0.7
E = CVdd
scales 0.7
Power
Pentium R Processor
0.1 0.1
1 2 3 4
0.01 0.01
00
1.0 0.8
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Pentium R II Processor
1000 1000
21
5 VCC or VT (V)
V CC or V T (V)
5 4 3
VCC
4 3
22 11 00
0
VCC=1.8V
VT
1 2 3 4
VT =.45V
1.4 1.0 0.8 0.6 .35 .25 .18 Technology Generation (m)
Voltage scaling is good for controlling ICs active power, but it requires aggressive VT scaling for high performance
59
Leakage power Short-channel effects Special circuit functionality, noise Soft error Parameter variation
60
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100
10
Technology Generation
61
Delay
CV d = L DD ID
d =
CL V W ( ) C oxV DD (1 T ) 2 2L V DD
d =
CL WC ox SAT (1 VT ) VDD
[1]
[1] C. Hu, Low Power Design Methodologies, Kluwer Academic Publishers, p. 25.
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Low VT
IDS
K1e
(VGS VT )
I OFF I subth
I D ( SAT )
Weff Leff
High VT
VD = VDD fixed Tox
Weff Leff
K 2 (VGS VT ) 2
VG
IOFF vs VT
1E-04
IOFF (A)
1E-05
1E-06
Log IOFF
1E-07
1E-08
I OFF e (VGS VT )
1E-09
1E-10 -0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
VT (V) - Normalized
VTP (V)
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100
10
30
40
50
60
70
80
90
100 110
Temperature (C)
1.E+01
Active Power
Power (W) )
0 101
1.E+00
10
-1 10-1
-2 -3
1.E-01
386
-2 1010 -3 1010
1.E-02
1.E-03
10-4 10-5 10
1.E-04
1.E-05
1.E-06 0 1 2 3 4 5 6 7
Barrier
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Power Trends
Enable development of ultra low voltage circuits Vt Variation for optimum energy At lower Vt, 2.5
Normalized Energy
Vdd = 0..5V
f=20MHz
Vdd = 0..9V 0.5 Multiple on-chip Vt Vt, 0 0.2 dynamic Vt Other challenges for low voltages ? 0.4 0.6 Threshold Voltage (Vt) 0.8 1
Trends in Microelectronics
Improvement in device technology
Smaller circuits Faster circuits More circuits on a chip
Higher Integration
More complex systems Lower cost of computation Higher reliability
Limitations
Intrinsic device scaling limits Cost of fabrication Interconnect limitation Large scale design management
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Problems of Microelectronics
Design Cost:
design time fabrication time impossibility t repair i ibilit to i reduce design cost to be competitive in price
Marketing Issues:
use most recent technologies to stay competitive in performance volume production is inexpensive time-to-market is critical evolving market
Solution:
Hierarchical and abstraction Different design styles Computer-Aided-Design
3 design domains
Behavioral
specifies what a particular system does
Structural
how entities are connected together to effect the prescribed manner
Physical
how to actually build a structure that has the required connectivity to implement the prescribed behavior
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MODULE + GATE
CIRCUIT
DEVICE G S n+ D n+
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Boolean equation Within this domain, there are various level of abstraction
Algorithm Register transfer level (communication between registers)
Acc
Boolean equations
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Structural Domain
The levels of abstraction include
module gate switch circuit
MODULE carry (co, a, b, c) input a, b, c; output co; wire x, y, z , AND g1 (x, a, b) AND g2 (y, a, c) AND g3 (z, b, c) OR g4 (co, x, y, z); ENDMODULE
a b g1
b c g3
a c g2
x y z g4
co
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Transistor Level
MODULE carry (co, a, b, c) input a, b, c; output co; wire i1, i2, i3, i4, cn; NMOS n1(i1, vss, a) NMOS n2(i1, vss, b)
. . . . . .
Physical Representation
MODULE carry ; Input a, b, c; p , , ; output co; boundary [0, 0, 100, 400] port a aluminum width = 1 origin = [0,2] port b aluminum width = 1 origin = [0,7] port
. . .
Port ci polysilicon .
ENDMODULE
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CMOS Logic
a s b s b a
NMOS transistor
a s=0 b a s=1 s=1 b a b s=1 a
PMOS transistor
a
Inverter (A)
VDD
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NAND (AB)
A+ B
A B 0 Out A 1 B B
A.B
NOR (A+B)
A. B
B 0 B A B 1
A+B
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Complex Gates
F = (( A + B + C ).D ) = D + ABC
F = ( A + B + C ).D
A B C D
Breadth of field
Semiconductor physics and technology Integrated electronics Systems design Testing Computer-Aided Design
Depth of field p
Complexity of fabrication technology Difficulty of design problems
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