VHDL Lab Programs

VHDL Lab Programs by
VENKATRAO
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Digital System Design Lab Report
1. HALF ADDER
Aim: To design the half adder using dataflow model. Theory: A half-adder an arithmetic circuit block that can be used to add two bits. Such a circuit thus has two inputs that represent the two bits to be added and two outputs, with one producing the SUM output and the other producing the CARRY. The program gives the sum of Boolean addition of inputs a, b. It indicates if a carry is generated. Sum= A XOR B; Carry= A AND B; Schematic diagram:
Figure 1.Half adder circuit diagram.
P.VENKATRAO (M.Tech)
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Truth-table: Table 3.1: Truth table of half adder A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1
VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity half_adder1 is Port ( a,b : in sum,carry : out end half_adder1; architecture Behavioral of half_adder1 is begin sum<= a xor b; carry<= a and b; end Behavioral; VHDL Test-bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY HA_tb IS END HA_tb; ARCHITECTURE behavior OF HA_tb IS COMPONENT half_adder1
P.VENKATRAO (M.Tech) Page 2 of 50
STD_LOGIC;
STD_LOGIC);
PORT( a : IN b : IN std_logic; std_logic; std_logic; std_logic
sum : OUT carry : OUT ); END COMPONENT;
--Inputs signal a : std_logic := '0'; signal b : std_logic := '0'; --Outputs signal sum : std_logic; signal carry : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: half_adder1 PORT MAP ( a => a, b => b, sum => sum, carry => carry ); stim_proc: process begin a<='0'; b<='0'; wait for 10 ns; a<='0'; b<='1'; wait for 10 ns;
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a<='1'; b<='0'; wait for 10 ns; a<='1'; b<='1'; wait for 10 ns; wait; end process; END; Simulated waveforms:
Figure 2. Simulated waveform of half adder. Conclusion: Half adder is implemented using VHDL in data flow model.
2. FULL ADDER
Aim: To design the full adder in dataflow model. Theory: Full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output. Such a building block becomes a necessity when it comes to adding binary numbers with a large number of bits. The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits only. The program gives the sum of Boolean addition of inputs a, b, c. It indicates if a carry is generated. SUM= A xor B xor C CARRY= (A and B) or (B and C) or(C and A)
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Schematic diagram:
Figure 3. Full adder circuit diagram. Truth table: Table 2: Truth Table of Full Adder
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1
VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity fulladder1 is Port ( a,b,c : in sum,carry : out end fulladder1; architecture Behavioral of fulladder1 is begin sum<=a xor b xor c; carry<= (a and b)or(b and c) or (c and a); end Behavioral; VHDL Test-bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fulladder_tb IS END fulladder_tb; ARCHITECTURE behavior OF fulladder_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fulladder1 PORT( a : IN b : IN c : IN std_logic; std_logic; std_logic; std_logic; std_logic STD_LOGIC; STD_LOGIC);
sum : OUT carry : OUT ); END COMPONENT;
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--Inputs signal a : std_logic := '0'; signal b : std_logic := '0'; signal c : std_logic := '0'; --Outputs signal sum : std_logic; signal carry : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fulladder1 PORT MAP ( a => a, b => b, c => c, sum => sum, carry => carry ); stim_proc: process begin a<='0';b<='0';c<='0'; wait for 10 ns; a<='0';b<='0';c<='1' ;wait for 10 ns; a<='0';b<='1';c<='0' ;wait for 10 ns; a<='0';b<='1';c<='1' ;wait for 10 ns; a<='1';b<='0';c<='0' ;wait for 10 ns; a<='1';b<='0';c<='1' ;wait for 10 ns; a<='1';b<='1';c<='0' ;wait for 10 ns; a<='1';b<='1';c<='1' ;wait for 10 ns; wait; end process; END;
Simulated waveform:
Figure 4.Simulated waveform for different inputs of full adder circuit diagram. Conclusion: Full adder is implemented using VHDL in data flow model.
3. COMPARATOR (4 BIT)
Aim: To simulate a 4 bit comparator in VHDL in data flow model. Theory:

A magnitude comparator is a combinational circuit that compares two given numbers and determines whether one is equal to, less than or greater than the other. The output is in the form of three binary variables representing the conditions A = B, A>B and A<B, if A and B are the two numbers being compared. Depending upon the relative magnitude of the two numbers, the relevant output changes state. This program compares two four bit vectors a, b and indicates Greater= 1 if A>B, Lesser =1 if A<B, Equal = 1 if A=B.
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Schematic of Full Adder:
Figure 5. Magnitude comparator diagram. Truth Table: Table 3. Truth Table of comparator
Inputs A>B A=B A<B Equal 0 1 0 Greater 1 0 0 Smaller 0 0 1
VHDL Code: Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; entity comparator1 is Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC);
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equal,greater,lesser : out
end comparator1; architecture Behavioral of comparator1 is begin equal<= '1' when (a=b) else '0' ; greater<= '1' when (a>b) else '0' ; lesser<= '1' when (a<b) else '0' ; end Behavioral; VHDL Test-Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY comparator_tb IS END comparator_tb; ARCHITECTURE behavior OF comparator_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT comparator1 PORT( a : IN b : IN std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic; std_logic; std_logic
equal : OUT greater : OUT lesser : OUT ); END COMPONENT;
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--Inputs signal a :std_logic_vector(3 downto 0):=(others => '0'); signal b :std_logic_vector(3 downto 0):=(others => '0'); --Outputs signal equal : std_logic; signal greater : std_logic; signal lesser : std_logic;
BEGIN -- Instantiate the Unit Under Test (UUT) uut: comparator1 PORT MAP ( a => a, b => b, equal => equal, greater => greater, lesser => lesser ); stim_proc: process begin a<="0000"; b<="0000"; wait for 10 ns; a<="0001"; b<="0010"; wait for 10 ns; a<="0011"; b<="0100"; wait for 10 ns; a<="0101"; b<="0100"; wait for 10 ns; a<="0111"; b<="1000"; wait for 10 ns; wait; end process; END;
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Simulated waveform:
Figure 6. Simulated waveform of magnitude comparator of 4- bit. Conclusion: The coding for comparator is done and output waveforms for the comparator are successfully plotted.
4. SHIFT REGISTER (16-BIT)

Aim: To design a shift register in dataflow modeling using VHDL coding. Theory: Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All flip-flops is driven by a common clock, and all are set or reset simultaneously. A shift register shifts the given binary value to 1-bit right or left.
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Schematic diagram:
Figure 7: Schematic of 16-bit shift register VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity shiftregister1 is Port ( data : in STD_LOGIC ; clk : in STD_LOGIC; STD_LOGIC_VECTOR (15 downto 0) );
output : out end shiftregister1;
architecture Behavioral of shiftregister1 is signal temp : std_logic_vector (15 downto 0):=X"0000"; begin temp<=data & temp(15 downto 1)when(clk='1'and clk'event); output<=temp;
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end Behavioral;
VHDL Test Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SHIFT_REG_TB IS END SHIFT_REG_TB; ARCHITECTURE behavior OF SHIFT_REG_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT shiftregister1 PORT( data : IN clk : IN std_logic; std_logic; std_logic_vector(15 downto 0)
output : OUT ); END COMPONENT;
--Inputs signal data : std_logic := '0'; signalclk : std_logic := '0'; --Outputs signal output : std_logic_vector(15 downto 0); -- Clock period definitions
constantclk_period : time := 10 ns; BEGIN uut: shiftregister1 PORT MAP ( data => data, clk =>clk, output => output ); clk_process :process begin clk<= '0'; wait for clk_period/2; clk<= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin data<='1'; wait for 10 ns; end process; END;
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Simulated waveform:
Figure 8. Simulated waveforms of the shift register 16-bit. Conclusion: The shift register of 16 bit is implemented using VHDL in data flow model
5. MULTIPLEXER WITH TRISTATING

Aim: To simulate a multiplexer with tri-stating in VHDL In data flow model. Theory: When multiple input lines are given depending on select a particular output line will be selected. When no output can be selected it goes to a high impedance state. Simulated diagram: The gate level schematic diagram for multiplexer is
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Figure 9: Simulated diagram of Multiplexer. Truth Table: Table 4: Truth table of Multiplexer. S(0) S(1) Y 0 0 1 1 VHDL coding: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multiplexer is Port ( i : in s : in y : out end multiplexer; architecture Behavioral of multiplexer is begin with s select
0 1 0 1
A(0) A(1) A(2) A(3)
STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC_VECTOR (1 downto 0); STD_LOGIC);
y <= i(0) when "00" , i(1) when "01" , i(2) when "10" , i(3) when "11" , 'Z' when others; end Behavioral; VHDL Test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_multiplexer IS END test_multiplexer; ARCHITECTURE behavior OF test_multiplexer IS COMPONENT multiplexer PORT( i : IN s : IN y : OUT ); END COMPONENT; signali :std_logic_vector(3 downto 0) := (others => '0'); signal s :std_logic_vector(1 downto 0) := (others => '0'); signal y : std_logic; BEGIN uut: multiplexer PORT MAP ( i =>i, std_logic_vector(3 downto 0); std_logic_vector(1 downto 0); std_logic
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s => s, y => y ); stim_proc: process begin i(0)<='1';i(1)<='0';i(2)<='0';i(3)<='0';s(0)<='0';s(1) <='0';wait for 100 ns; i(0)<='0';i(1)<='1';i(2)<='0';i(3)<='0';s(0)<='1';s(1) <='0';wait for 100 ns; i(0)<='0';i(1)<='0';i(2)<='1';i(3)<='0';s(0)<='0';s(1) <='1';wait for 100 ns; i(0)<='0';i(1)<='0';i(2)<='0';i(3)<='1';s(0)<='1';s(1) <='1';wait for 100 ns; wait; end process; END; Stimulated waveforms:
Figure 10. Stimulated waveform for multiplexer. Conclusion: Multiplexer with tristating is implemented using VHDL in data flow model.
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6. DECODER WITH TRISTATING

Aim: To design a 2 to 4 decoder with tristating output using dataflow model. Theory: It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. Based on the two input lines one output line among four is selected. In this program we designed the decoder in dataflow model using when-else statement. So we use a tristate buffer at the end of each input. If the enable E is high, output is equal to input otherwise output is high impedance.
Schematic diagram:
Figure 11. Schematic diagram of Decoder
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Truth table: Table 5: Truth table for decoder

INPUT Enable OUTPUT Y(0) Y(1) Y(2) Y(3) XX 00 01 10 11 0 1 1 1 1 Z 0 0 0 1 Z 0 0 1 0 Z 0 1 0 0 Z 1 0 0 0
VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder2x4 is Port ( en : in sel : in y : out end decoder2x4; architecture Behavioral of decoder2x4 is begin y<= "ZZZZ" when en='0' else "0001" when sel="00" else "0010" when sel="01" else "0100" when sel="10" else "1000"; End Behavioral; VHDL Test Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decoder_tb IS
STD_LOGIC; STD_LOGIC_VECTOR (1 downto 0); STD_LOGIC_VECTOR (3 downto 0));
END decoder_tb; ARCHITECTURE behavior OF decoder_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT decoder2x4 PORT( en : IN sel : IN y : OUT ); END COMPONENT; --Inputs signal en : std_logic := '0'; signalsel '0'); --Outputs signal y : std_logic_vector(3 downto 0); -- appropriate port name BEGIN -- Instantiate the Unit Under Test (UUT) uut: decoder2x4 PORT MAP ( en => en, sel =>sel, y => y ); -- Stimulus process stim_proc: process begin
std_logic; std_logic_vector(1 downto 0); std_logic_vector(3 downto 0)
std_logic_vector(1
downto
0)
:=
(others
=>
sel<="00" ;en<='1'; wait for 100 ns; sel<="01" ;en<='1'; wait for 100 ns; sel<="10" ;en<='1'; wait for 100 ns; sel<="11" ;en<='1'; wait for 100 ns; sel<="00" ;en<='0'; wait for 100 ns; sel<="01" ;en<='1'; wait for 100 ns; sel<="10" ;en<='0'; wait for 100 ns; sel<="11" ;en<='1'; wait for 100 ns; wait; end process; END; Simulated waveform:
Figure12.Simulated waveform of decoder with tristating decoder
Conclusion:
Decoder with tristating using VHDL is implemented in data flow model.
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7. BINARY COUNTER (4-BIT) Aim: To simulate a 4-bit binary counter using VHDL. Theory:
A counter that can change state in either direction, under the control of an up/down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count. Here we design a 4bit binary counter using behavioral model. The circuit is working with raising edge of clock. When raising edge of clock happened the count will increment Schematic diagram:
Figure 13.Circuit diagram of binary counter VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is Port (count :inoutstd_logic_vector(3 downto 0):="0000"; urd,clk :in std_logic;
reset :in std_logic); end counter; architecture Behavioral of counter is begin process(clk,urd) begin if(clk='1' and clk'event) then if reset='1' then count<="0000"; elsif(urd='1') then count<=count+"0001"; elsif(urd='0') then count<=count-"0001"; end if; end if; end process; end Behavioral; VHDL Test Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY counter_t IS END counter_t; ARCHITECTURE behavior OF counter_t IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT counter PORT(count : INOUT std_logic_vector(3 downto 0); urd : IN std_logic; clk : IN std_logic; reset :in std_logic
); END COMPONENT; --Inputs signalurd : std_logic := '0'; signalclk : std_logic := '0'; signalreset:std_logic := '0'; --BiDirs signal count : std_logic_vector(3 downto 0); -- Clock period definitions constantclk_period : time := 20ns; BEGIN -- Instantiatethe Unit Under Test (UUT) uut: counter PORT MAP ( count => count, urd =>urd, clk =>clk, reset=> reset ); -- Clock process definitions clk_process :process begin clk<= '0'; wait for clk_period/2; clk<= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin urd<='1','0' after 300 ns; reset<='0','1' after 100 ns,'0' after 120ns; wait for clk_period*10;
wait; end process; END; Simulated waveforms:
Figure 14: Stimulated waveform of binary counter

Conclusion:
Binary counter is implemented using VHDL in behavioral model.
8. DECADE COUNTER
Aim: To simulate a decade counter using VHDL. Theory: The decade counter is also known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). This program builds an up/down decade counter (mod-10) which counts on each rising edge of clock pulse. Schematic Diagram:
Figure 15: Schematic diagram for Decade Counter.

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitycdecade is port( count : inoutstd_logic_vector(3 downto 0):="0000"; urd,clk :in std_logic; reset :in std_logic); endcdecade; architecture Behavioral of cdecade is begin process(clk,urd) begin if(clk='1' and clk'event) then if reset='1' then count<="0000"; elsif(urd='1') then count<=count+"0001"; if (count+"0001")>"1010" then count<="0000"; end if; elsif(urd='0') then count<=count-"0001"; if (count-"0001")>="1111" then count<="1010"; end if; end if; end if; end process; end Behavioral;
VHDL Test Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY cdecade_t IS END cdecade_t; ARCHITECTURE behavior OF cdecade_t IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT cdecade PORT( count : INOUT std_logic_vector(3 downto 0); urd : IN std_logic; clk : IN std_logic; reset : IN std_logic ); END COMPONENT; --Inputs signalurd : std_logic := '0'; signalclk : std_logic := '0'; signal reset : std_logic := '0'; --BiDirs signal count : std_logic_vector(3 downto 0); -- Clock period definitions constantclk_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: cdecade PORT MAP ( count => count, urd =>urd, clk =>clk, reset => reset );
-- Clock process definitions clk_process :process begin clk<= '0'; wait for clk_period/2; clk<= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin urd<='1','0' after 300 ns; reset<='0','1' after 240 ns,'0' after 260ns; wait for clk_period*10; wait; end process; END; Simulated waveforms:
Figure 16: Simulated waveform for decade counter CONCLUSION: Binary counter is implemented using VHDL in behavioral model.
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9(a).BCD ADDER
Aim: To design BCD adder in behavioral modeling using VHDL coding. Theory: The BCD adder counts only up to 9, when the count becomes more than 9 or carry will be generate it adds binary number 6 to it. Schematic diagram: The gate level schematic diagram for BCD adder is
Figure 17: Schematic diagram for BCD adder. VHDL coding: Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity adder is Port ( a,b : in c :inout End adder; Architecture Behavioral of adder is
STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC_VECTOR (4 downto 0));
begin process (a,b) variabletemp:std_logic_vector(4 downto 0):="00000"; begin temp := ('0' & a) + ('0' & b); if (temp(3 downto 0) >= "1010") then temp:= temp+ "00110"; end if; c<=temp; end process; end Behavioral;
VHDL Test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_bcdadder IS END test_bcdadder; ARCHITECTURE behavior OF test_bcdadder IS -- Component Declaration for the Unit Under Test (UUT)
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COMPONENT adder PORT( a : IN b : IN ); END COMPONENT; --Inputs signal a : std_logic_vector(3 downto 0) := (others => '0'); signal b : std_logic_vector(3 downto 0) := (others => '0'); --BiDirs signal c : std_logic_vector(4 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: adder PORT MAP ( a => a, b => b, c => c ); stim_proc: process begin a<="1000";b<="0011"; wait; end process; END; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(4 downto 0)
c : INOUT
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Stimulated waveforms:
Figure 18: Stimulated waveform for BCD adder. CONCLUSION: BCD adder is implemented using VHDL in behavioral model.
9(b).BCD SUBTRACTOR
Aim: To design BCD subtractor in behavioral modeling using VHDL coding. Theory: The binary subtractor works on 2s complement form. Two's complement subtraction is the binary addition of the minuend to the 2's complement of the subtrahend (adding a negative number is the same as subtracting a positive one). Schematic diagram: The RTL gate level schematic diagram for BCD subtractor is
Figure 19: Schematic diagram for BCD subtractor.

VHDL Coding: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitybcdsubractor is Port ( a,b : in c : out endbcdsubractor; architecture Behavioral of bcdsubractor is begin process (a,b) variable temp: STD_LOGIC_VECTOR (4 downto 0):=(others=>'0'); begin temp:= ( '0' & a)-('0' & b); if (a < b) then temp:= not(temp) + "10001"; end if; c<=temp; end process; end Behavioral; VHDL Test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC_VECTOR (4 downto 0));
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ENTITY test IS END test; ARCHITECTURE behavior OF test IS COMPONENT bcdsubractor PORT( a : IN b : IN c : OUT ); END COMPONENT; --Inputs signal a : std_logic_vector(3 downto 0) := (others => '0'); signal b : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal c : std_logic_vector(4 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: bcdsubractor PORT MAP ( a => a, b => b, c => c ); -- Stimulus process stim_proc: process begin a<="1000";b<="0111";wait for 100 ns; a<="1000";b<="1011"; wait; end process; END;
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(4 downto 0)
Stimulated waveform:
Figure 20: Stimulated waveform for BCD Subtractor. Conclusion: BCD Subtractor is implemented using VHDL in behavioral flow model.
10. D FLIP-FLOP
Aim: To design a D flip-flop in behavioral flow modeling using VHDL coding. Theory: D flip-flop gives a one bit delay to the input at the rising edge of the clock. The D flipflop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an inverter. The result may be clocked. Schematic diagram: The RTL gate level schematic diagram for flip-flop.
Figure 21: Schematic diagram of D flip-flop.

Truth table: Table 6: Truth table for Delay flip-flop. Q 0 0 1 1 D 0 1 0 1 Q(t+1) 0 1 0 1
VHDL Coding: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitydff is Port ( d : in q :inout qn : out clock : in enddff; architecture Behavioral of dff is begin process (reset,d,clock) begin if (reset='1') then q<='0'; elsif(clock='1' and clock'event) then q<=d;
STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);
reset : in
end if; qn<=not q; end process; end Behavioral;
VHDL Test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY testdff IS END testdff; ARCHITECTURE behavior OF testdff IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dff PORT( d : IN std_logic; std_logic; std_logic; std_logic; std_logic); ---Inputs signal d : std_logic := '0'; signal reset : std_logic := '0'; signal clock : std_logic := '0'; --BiDirs
reset : IN q : INOUT qn : OUT clock : IN END COMPONENT;
signal q : std_logic; --Outputs signalqn : std_logic; -- Clock period definitions constantclock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: dff PORT MAP ( d => d, reset => reset, q => q, qn =>qn, clock => clock ); -- Clock process definitions clock_process :process begin clock<= '0'; wait for clock_period/2; clock<= '1'; wait for clock_period/2; end process; stim_proc: process begin d<='0';wait for 50 ns; d<='1';wait for 50 ns; d<='0';wait for 50 ns;
d<='1';wait for 50 ns; d<='0';wait for 50 ns; d<='1';wait for 50 ns; wait; end process; END; Stimulated Wave form:
Figure 22: Stimulated wave form for D flip-flop. Conclusion: Delay flip-flop is implemented using VHDL in behavioral model.
11. T FLIP- FLOP

Aim: To implement a T Flip-Flop using VHDL coding in behavioral model. Theory: T flip-flop is called as Toggle flip-flop because when T input is high the output will toggle. T flip-flop can derive from JK by connecting J&K to T. asynchronous T flip-flop is works with a reset pin. If the reset pin is high the output will change at the clock edge.
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Schematic diagram:
Figure 23. Internal block diagram of T-flip flop. Truth Table: Table 7: Truth table for Toggle flip-flop.
Q(t) 0 1 0 1
T 0 0 1 1
Q(t+1) 0 1 1 0
VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitytff is Port ( t : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC); clock : in q :inout qn : out
reset : in
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endtff; architecture Behavioral of tff is begin process (t,clock,reset) begin if(reset='1' ) then q <='0'; elsif(clock='1' and clock'event)and t=1then q<= not t; end if; qn<= not q; end process; end Behavioral;
VHDL Test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY testtff IS END testtff; ARCHITECTURE behavior OF testtff IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT tff PORT( t : IN std_logic; std_logic;
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clock : IN
q : INOUT qn : OUT reset : IN ); END COMPONENT;
std_logic; std_logic; std_logic
--Inputs signal t : std_logic := '0'; signal clock : std_logic := '0'; signal reset : std_logic := '0'; --BiDirs signal q : std_logic; --Outputs signalqn : std_logic; -- Clock period definitions constantclock_period : time := 50 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: tff PORT MAP ( t => t, clock => clock, q => q, qn =>qn, reset => reset );
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-- Clock process definitions clock process :process begin clock<= '0'; wait for clock_period/2; clock<= '1'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin t<='0'; wait for 100 ns; t<='1'; wait for 100 ns; t<='0'; wait for 100 ns; t<='1'; wait for 100 ns; t<='0'; wait for 100 ns; wait; end process; END; Stimulate waveform:
Figure 24:Stimulated waveform of T-flip flop. Conclusion: Toggle flip-flop is implemented using VHDL in behavioral model.
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12. JK FLIP-FLOP
Aim: To implement a JK FF using VHDL coding in behavioral model. Theory: The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge. This program builds a JK-FF which gives output according to the following truth table on each rising edge of clock pulse. Schematic diagram:
Figure 25: Schematic diagram of jk flip-flop Truth table: Table 8: Truth table for JK flip-flop.
j 0 0 0 1
k 0 1 1 1
Q(t+1) On 0 1 Qn_bar
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VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityjk is Port ( jkin: in std_logic_vector(1 downto 0); clock : in q : out qn: out endjk; architecture Behavioral of jk is signal state : std_logic ; begin process(jkin,clock) begin if ( clock='1' and clock'event) then casejkin is when "11" => state <= not state; when "00" => state <= state; when "01" => state <='0'; when "10" => state <= '1'; when others => null; end case; end if; q <= state;
STD_LOGIC;
STD_LOGIC:='0'; STD_LOGIC:='1');
qn<= not state; end process; end Behavioral; VHDL Test Bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY jktest IS END jktest; ARCHITECTURE behavior OF jktest IS COMPONENT jk PORT( jkin : IN clock : IN q : OUT qn : OUT ); END COMPONENT; --Inputs signaljkin : std_logic_vector(1 downto 0:= (others => '0'); signal clock : std_logic := '0'; --Outputs signal q : std_logic; signalqn : std_logic; -- Clock period definitions
std_logic_vector(1 downto 0); std_logic; std_logic std_logic;
constantclock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: jk PORT MAP ( jkin =>jkin, clock => clock, q => q, qn =>qn ); -- Clock process definitions clock_process :process begin clock<= '0'; wait for clock_period/2; clock<= '1'; wait for clock_period/2; end process;
-- Stimulus process stim_proc: process begin jkin<="00"; wait for 100 ns; jkin<="01"; wait for 100 ns; jkin<="10"; wait for 100 ns; jkin<="11"; wait for 100 ns; wait; end process; END;
Stimulated Waveform:
Figure 26: Stimulated wave form for Jk Flop-Flop. Conclusion: JK Flip-Flop is implemented using VHDL in behavioral model.
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Digital System Design Lab Report

Figure 1.Half adder circuit diagram.

Digital System Design Lab Report

Truth-table: Table 3.1: Truth table of half adder A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1

Digital System Design Lab Report

PORT( a : IN b : IN std_logic; std_logic; std_logic; std_logic

sum : OUT carry : OUT ); END COMPONENT;

Digital System Design Lab Report

Digital System Design Lab Report

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL;

Digital System Design Lab Report

sum : OUT carry : OUT ); END COMPONENT;

Digital System Design Lab Report

Digital System Design Lab Report

Aim: To simulate a 4 bit comparator in VHDL in data flow model. Theory:

Digital System Design Lab Report

Schematic of Full Adder:

Digital System Design Lab Report

equal : OUT greater : OUT lesser : OUT ); END COMPONENT;

Digital System Design Lab Report

Digital System Design Lab Report

4. SHIFT REGISTER (16-BIT)

Digital System Design Lab Report

output : out end shiftregister1;

Digital System Design Lab Report

output : OUT ); END COMPONENT;

Digital System Design Lab Report

Digital System Design Lab Report

5. MULTIPLEXER WITH TRISTATING

Digital System Design Lab Report

A(0) A(1) A(2) A(3)

STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC_VECTOR (1 downto 0); STD_LOGIC);

Digital System Design Lab Report

Digital System Design Lab Report

Digital System Design Lab Report

6. DECODER WITH TRISTATING

Figure 11. Schematic diagram of Decoder

Digital System Design Lab Report

Truth table: Table 5: Truth table for decoder

STD_LOGIC; STD_LOGIC_VECTOR (1 downto 0); STD_LOGIC_VECTOR (3 downto 0));

Digital System Design Lab Report

std_logic; std_logic_vector(1 downto 0); std_logic_vector(3 downto 0)

Digital System Design Lab Report

Figure12.Simulated waveform of decoder with tristating decoder

Digital System Design Lab Report

Digital System Design Lab Report

Digital System Design Lab Report

Digital System Design Lab Report

wait; end process; END; Simulated waveforms:

Figure 14: Stimulated waveform of binary counter

Binary counter is implemented using VHDL in behavioral model.

Figure 15: Schematic diagram for Decade Counter.

Digital System Design Lab Report

Digital System Design Lab Report

Digital System Design Lab Report

Digital System Design Lab Report

STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC_VECTOR (4 downto 0));