tea

Faculteit der Elektrotechniek

Vakgroep Elektromechanica en Vermogenselektronica
StageversJag
Modeling an Insulated Gate Bipolar
Transistor (IGBT) with PSPICE.
Carniel Verboeve
EMV 91-08
Hooglera(a)r(en):
Mentor(en)
Eindhoven.
Ir. S.W.H. de Haan
juli, 1991.
De Faculteit der Elektrotechniek van de Technische Universiteit Eindhoven aanvaardt geen verantwoordelijkheid voor
de inhoud van stage- en afstudeerverslagen.
SUMMARY
In this report we made a model of the Insulated Gate Bipolar Transistor (IGBT) with
PSPICE. This model was made by deriving the device parameters from the device
structure. Most of the device parameters are calculated from estimated values,
because we didn't have detailed information about the IGBT. These parameters are
used in a PSPICE input file. A measurement circuit was built to compare the
simulation results, calculated by PSPICE, with the measurements.
The comparison of the transient characteristics shows that the model is in fair
agreement with the reality. However the model still needs some adaption, especially
the gate structure needs to be reconsidered and the model parameters have to be
recalculated with the exact values of the used device. Then we have a qualitative
good model, which we can use for simulation purposes.
- 1 -
CONTENTS:
Page
Summary 1
Chapter 1 Introduction 3
Chapter 2 . The IGBT 4
2.1 General action 4
2.2 Transient characteristics 6
Chapter 3 Modeling the IGBT 7
3.1 Equivalent circuit 7
3.2 Model parameters 9
Chapter 4 Comparison measurements with simulations 17
4.1 The measuring circuit 17
4.2 Experimental results 19
Chapter 5 Conclusions 31
Literature 32
Appendices
- 2 -
CHAPTER 1
Introduction.
Power electronics are getting more and more significant in electrical engineering. For
instance to control machines, for power supplies and so on. Most of these control
equipment contain semiconductors devices, because they are compact and easy to
control.
A rather new semiconductor device, suitable for high-power applications, is the
Insulated Gate Bipolar Transistor (IGBT). The IGBT is a MOST-like device, which
can turn a current on and off. The main advantage of this device is that the IGBT
can handle large currents and voltages (like a thyristor or GTO) and it needs a
relative small control power (like a MOSFET).
To make the design of power converters more easy, we want to have a computer mo-
del, so that we can predict the the behaviour before building it. In this report I made
a simple IGBT-model for PSPICE, because in our group the simulation program
PSPICE is used and the program hasn't a model for it. I used the equivalent circuit
and parameters that could be derived from the device structure and estimated doping
profiles to make a subcircuit. This subcircuit can be used in any PSPICE inputfile and
can be specified to the used type of IGBT.
I firs! made a 'rough' model for a qualitative comparison with the measured results,
after this we can make it more detailed.
- 3 -
CHAPTER 2
The insulated Gate Bipolar Transistor (IGBT).
2.1, General action.
As said the IGBT is a new power electronic device, which combines the high conduc-
ting capacitance of the bipolar transistor with the easy gate control of a MOSFET.
The symbol and the general structure of the IGBT are as follows:
EMITTER GATE
EMITTER
COLLECTOR
N+
p+
Jl
GATE
N
J2
EMITTER
p
COLLECTOR
Figure 2.1. Symbol and general structure of an IGBT.
Next we shall give an explanation of the action of the IGBT. First we apply a voltage
to the collector and emitter. This voltage is positive. The middle junction J1 now is
reverse biased. In a thyristor or a transistor this junction is made conducting by
injection of electrons (minority carriers) from the cathode (thyristor) or emitter
(transistor). In case of an IGBT it is done by creating a n-type channel in the p-Iayer.
In this way there is created a current path from the collector to the emitter.
To prevent the (parasitic) thyristor structure from conducting (latching), the gate and
the cathode are short-circuited. The gate-emitter voltage controls the channel and
therefore the current in the IGBT. Contrary to the thyristor the IGBT can be turned
off. The static characteristics are given in figure 2.2.
- 4 -
20
18
16
15
Vi 14
c..
~ 12
~ 10
8
6
4
2
IXGH20N60
~ ~
T
c
'" 25'C
~ ~ ~
1/ II _/
~ c : v , ,,"J 0"
I / ~ ~ I VOS '" BV
I)
/
I
I r/ I
VOS =7V
"
'/
.....-
" I I
f/
/1
r/
V VO
S
= 6V
~ h
'/
'rK
I
VOS =SV
o 2 3 4 5 6 7 B 9 10
Vos (VOLTS)
Figure 2.2. Static behaviour of the IGBT.
(In this figure the MOSFET nomenclature is used.)
- 5 -
2.2. Transient characteristics.
Typical transient characteristics of the IGBT are given in figure 2.3.
20V
It
II I
I I I
II I
ID IdIOn).,
I
I
I
I
I
I
I
I

NOTE. I, I" - 1'2
I
I
I

I
I
10",.
10V
Figure 2.3. Transient characteristics of the IGBT.
The waveform of the gate-emitter voltage is mainly determined by two phenomena.
First the gate capacitance; this capacitance has to be charged to create a channel. The
gate capacitance can be decreased by making the channel length smaller, but the
length can't be made too small because then one decreases the forward blocking
voltage. On the other hand this turn-off characteristic is determined by the stored
charge. The big p- and n-Iayers will accumulate an amount of charge, that has to be
removed when the IGBT is turned off. This is the cause of the tail-current of the
IGBT. One can reduce this tail-current by implementing impurities in this region.
Then one creates recombination centres where the charge can be collected. A
disadvantage of this technique is that the 'on'-voltage of the IGBT is increasing.
In the next chapter we try to determine the main parameters of the IGBT. More
detailed information about the IGBT used is given in appendix A This is the
datasheet of the IGBT we used.
- 6 -
CHAPTER 3
The modeling of the IGBT.
3.1: EQuivalent circuit
The IGBT that we want to simulate is a IXYS-IGBT (Power-MOSIGT), type
IXGH25NlOOA This is a high-speed version, which can handle currents of 50A
(max.) and voltages of 1000V (max.). For more information we refer to appendix A
To make an equivalent circuit of the IGBT, we have to look at the device structure of
the component. See figure 3.1.
Rl
Q1
o
CJEl
02
COLLECTOR
C1
~ G A T E
M'l 1
c2

Figure 3.1. The equivalent circuit for the IGBT.

This is a general model for an IGBT. This model consists mainly of aMOS-transistor
and a parasitical thyristor. The gate and the cathode of the thyristor are shortcircuited
to prevent the thyristor from conducting (latching). The bulk of the MOST is also
connected with the emitter of the IGBT.
At the same time we have to deal with parasitic capacitances. In this way we have a
capacitor between the gate and the emitter and a capacitor between the thick n-Iayer
and the gate of the IGBT, because they are (partly) overlapping. Capacitor Cl
respectively C2 in our model. Because PSPICE has no breakdown mechanisms in its
transistor model, we have to put two diodes in the model, D1 and D2. Diode D1 has
- 7 -
the purpose to represent the forward collector-emitter voltage and D2 has to
represent the reverse collector-emitter voltage.
Initially further parasites, like inductance of the connecting wires, are not considered
here, because the inaccuracy of this model is still so big that these influences are of
negigible.
The components of figure 3.1 will be discussed in section 3.2.
- 8 -
3.2. Model parameters
It will be clear that the components of the equivalent circuit are not normal, because
the structure of them is essentially different from normal ones. Therefore we cannot
use the default parameters given by PSPICE. The model will only act as a real IGBT
if we adjust the parameters of the components used.
The estimated values that we used to calculate the model parameters are given in the
next tabel. (See table 3.1.)
Table 3.1. Estimated values of the IGBT.
Width and length of the gate and oxide layer:
Size of the collector
Thickness of the oxide
Channel length
Thickness of the different layers:
upper n-Iayer (emitter)
upper p-Iayer (emitter)
lower n-Iayer
lower p-Iayer (collector)
Doping of the different layers:
upper n-Iayer (emitter)
upper p-Iayer (emitter)
lower n-Iayer
lower p-Iayer (collector)
Spacecharge in the oxidelayer
10-
2
m x 2.10
4
m
10-
2
m x 10-
3
m
10-
7
m
10.
7
m
10
18
cm
3
10
17
cm
3
10
14
cm-
3
10
18
cm-
3
For ease of description, we assume that the IGBT is a block with a rectangular gate
with the sizes mentioned above (see table 3.1). The oxide thickness and the channel
length are default PSPICE parameters. Thickness and doping of the different layers
are taken from papers. These values are assumed to be typical IGBT values. The
space charge in the oxide is also a default PSPICE value. The data in table 3.1 is
used to calculate the passive components in figure 3.1 and to adapt the parameters of
the active components in figure 3.1. The default PSPICE values are used for the cases
where reliable data is missing.
To see what components in figure 3.1 have to be adjusted, we have to look at the
current path of the IGBT. See figure 3.2.
- 9 -
EMITTER
------lJl
-------iJ2
GATE
p
N
EMITTER
COLLECTOR
Figure 3.2. The current path in the IGBT.
We start with the pnp-transistor 01 (see figure 3.1) in our model. For an IGBT most
of the current of this transistor goes from the emitter through the base to the MOS-
transistor Ml. If we look at the transistor model used by PSPICE (see figure 3.3), we
see that a low collector current can be achieved by making the common emitter
current-gain P
r
equal to one. (The common emitter current-gain P
r
is: Ie / lb.)
Figure 3.3. PSPICE transistor model (Gummel-Poon)
- 10 -
The equations for the bipolar transistor are:
I
bd
l
bel
I
b
=area(- +/
bc2
+-+l
bc2
)
13, 13
r
I =l
b
+l
e c
The default values of area, K
qb
and f3
r
are equal to 1. Area is the relative device area,
K
qb
is the base charge faktor and f3
r
is the reverse current-gain. These parameters
have no meaning in our first model. Currents I
bc2
and I
bc2
are non-ideal currents and
are equal to zero in our model. Currents I
bc1
and I
bc1
are the forward and the reverse
diffussion currents:
l
bel
=IS{e Y , J ( N F Y ~ -1)
l
bel
=IS{e Y.,/(HRYJ -1)
NF=l
NR=1
lT
V=-
r q
Where IS is the transport saturation current and is default 1.10-
16
This current also
has to be adjusted. The fomula for IS is:
IS=J :A=A{qDI' PMJ + qD,. n,o)_A{qDI' PMJ)
$ L
p
L,. L
p
A=1O-
1
em
2
2
D -10 em
p s
With a PnO = 10
6
em-
3
and a diffusion length ~ ~ 1.1-10-1 ern, we get a saturation
current IS of 1.4-10-
9
A.
Another point of attention in the transistor model, are the depletion' capacitances.
- 11 -
Because they determine the rise- and falltime of the IGBT. It is possible to imple-
ment these capacitances in the PSPICE transistor model, however to keep the model
simple and well organized, I choose to make these capacitances outside the transitor,
to make an first order approach. We calculate the capacitance between the emitter
and the base of the pnp-transistor first.
The general formula for the depletion capacitance, when no voltage is applied, is:
A
C =-
JO W
r--------
w= ..
qN..N
D
If we calculate the capacitance between the emitter and the base (CJEl) we get a
capacitor of 35 nF. The capacitance between the base and the collector (CJCl) of the
pnp-transistor (which is the same as the capacitance between the base and the
collector of the npn-transistor) is in our calculations equal to 3.5 nF. (We assume that
the area of the upper junction (emitter) is lOx smaller than the lower p-n junction.)
And the capacitance between the base and the emitter (CJE2) of the npn-transistor is
equal to 10 nF. At this moment it is not required to consider the pnp-transistor in
more detail.
The npn-transistor is not considered here, because it has no particular meaning in our
first approximation model. The transistor gets a function when the latching of the
parasitical th)Tistor is under discussion.
An other important feature of the IGBT is the diffusion charge in the lower p- and n-
layer (junction J2). This charge is the main cause of the tail current of the IGBT.
This charge is accumulated in the emitter and the base of the pnp-transistor. We
assume that most of this charge is in the base of this very inefficient transistor. The
base charge is generally given as follows:
, ,I.
Q.*'\/ J.=r:ri=t/l
b
Jl,m,
t=--
I qA
cm
2
Jl =450-
p Vs
m
p
=O.Sm
o
=0.45'lO-30kg
q=1.61O-
19
C
With an A of 10-
5
m
2
, this results in a 'f r of 100 IJ,S. However the simulations showed
that this value of 'f f was too big, because the program didn't converge. So we have
adjusted this to 1 IJ,S, which showed acceptable results.
- 12 -
The first part of the current path is modeled now. Next we have to look at the MOS-
transistor. Therefore we consider the current formulas of the MOST.
If Vgs - VtO < 0:
Id=O
If Vds < Vgs - VtO:
W
K
I
d
=-.::f(1 +1 Vetr)'V
etr
-(2'(V'"-V.o>- Vetr>
L 2 0-
If 0 S Vgs - VtO $ Vds:
I
d
= WK
p
(l +AVetr)-(V.
s
_ V~ 2
L 2 0
A normal MaS-transistor can only take small currents, so we have to adjust some of
the parameters of the PSPICE MOST for our purpose. At first we have to adjust the
sizes of the channel. The default value for the width W and the length L are 10
4
m.
We have adjusted the width to 10-
2
m. We leave the length L to 10
4
m. These values
are for a rectangular gate structure, as assumed in the beginning of this section.
After this we have to look at the transconductance coefficient ~ . The coefficient ~
is calculated as follows:
Where JJ is the mobility of the minority carriers in the substrate of the MOST, in this
case they are electrons. So JJ
n
= 1450 (cm
2
/Vs).
,=3.9
0=8.85'10-
12
.As
Vm
We assume a oxidethickness of 10-
7
m. That makes ~ = 0.5.
- 13 -
For the ihre5ho1d vultage VtOt the formula is given as follows:
with the following values:
e =LOS 010-
12

6 em
q=1.61O-
19
C
2WB-
0
.
7V
e
or
-4 F
C
ox
=--3.4S
0
10 --
t
ox
em-
2
If we calculate Vto' with an impurity concentration N
A
of 10
17
cm-
3
, we get approxi-
mately 5 Volt.
We have now created a current path in the IGBT by calculating new values for the
main components. But we still have some components in our equivalent circuit which
need some attention, like the 'overlapping' capacitances C1 and C2. These are very
trivial:
eA
C=-
d
If we calculate these C's with our estimated values, we get a capacitance C1 about
100 pF and a capacitance C2 about 30 pF.
Next we consider the diodes D1 and D2. The diodes may not affect the transistors so
we have made the saturation current of these diodes very small. (IS = 1.0-10-
30
.) The
breakdown voltage of D1 (Le. the maximum forward voltage of the IGBT) is set at
2500 V. This may be considered very high, but this is because than no forward break-
down occurs during our simulations. The breakdown voltage of D2 (Le. the maximum
reverse voltage of the IGBT) is set at 20 V.
At last we consider the resistors R1 and R2. In practice they are the same, so they
have the same value. A value of 1 10'0 will be sufficient to prevent the thyristor from
latching.
- 14 -
Now we have completed our model and the PSPICE subcircuit for the IGBT is given
as follows:
.SUBCKT MODELIGBT 1 2 3
*#1: COLLECTOR #2:GATE #3: EMITTER
*TESTMODEL ONTWIKKELD DOOR CAMIEL VERHOEVE
R1341UOHM
R2 631UOHM
D145 DMOD1
D2 15 DMOD2
Q145 1 QMODI
Q25 4 3 QMOD2
Ml 523 6 MMODI W= 10MM
CI 23 150PF
C2 2 5 30PF
CJEI I 5 3.5NF
CJCl 4 5 0.3NF
CJE23 4 O.INF
.MODEL DMODI D(BV=2500)
.MODEL DMOD2 D(BV=20,IS =1.0E-30)
.MODEL QMODI PNP(BF= 1,IS= 1.4E-9,TF= IUS)
.MODEL QMOD2 NPN
.MODEL MMODI NMOS(VTO=5V,KP=0.5)
.ENDS MODELIGBT
If we make a first static analysis with this model, see the static analysis inputfile in the
appendix, we get the following result:
- 15 -
2 5 ~ -; -1- - ....;.. _ - - _.. - -.. -- ---- --
: V
ge
- lOV .
, ,
,
~ - - - - - - - - - - - - - - - - - - - - , V
ge
- S.sv
,
+
~ - - - - - - - - - - - - - - - - - - - - , : V
ge
- 5.4V
r - - - - - - - - - - - - - - - - - - - - ~ ~ Vge - S. 3V
Figure 3.4. Simulated static analysis of the IGBT.
8V
V
ge
- 5. 2V
V
ge
~ OV
lOV
This figure shows that this model has the static behaviour of an IGBT
t
only the gate
voltage is less lineair with the current as in practice. Figure 2.2 shows the static
behaviour of the used IGBT. In our model the collector current rises very quickly
when the gate-emitter voltage is more than 5 Volt.
At the end of this chapter I want to emphasis
t
that the model parameters are estima-
ted ones and therefore very inaccurate. This is because I didntt have detailed
information about the structure, dopingprofiles and so on. Some of the modelparame-
ters have been adjusted during the simulation runs to match simulation to experimen-
tal data.
- 16 -
CHAPfER4
Comparison measurements with simulations.
Section 4.1 gives the test conditions and in section 4.2 we will first consider the
measured results and than compare them with the simulated results.
With the subcircuit derived in chapter 3, we made two PSPICE inputfiles (see
appendix). One for the turning-on of the IGBT and the other for the turning-off
characteristics. We calculated the collector-emitter voltage, the gate-emitter voltage,
the collector current and the gate current.
4.1. The measuring circuit.
To measure the transient characteristics of the IGBT while conducting currents of
some Amperes, we built the circuit from figure 4.1.
VMG
RL
#IV
LL
VMA
+
VA
Figure 4.1. The measuring circuit.
The IGBT was connected to a voltage source in series with an adjustable resistor,
which was set at 25 n. We applied a voltage of 100 V. The impedance of the voltage
source is negligible. Because the resistor is a winded one, we have to deal with a
parasitic inductance. The measured value is 1.4 mHo A clamping diode is not used.
We also wanted to have a gatedriver at our disposal, which could adjust the value of
the gate resistance from In to lkn. Therefore we built a gatedriver as shown in figure
4.2.
- 17 -
1 k Oh III
5V
Figure 4.2. The gatedriver.
HPCL
220eC
T2:2N3906
16V :::
15V n (CATE)
This gatedriver also uncouples the function generator from the main circuit. The gate
resistance was set to 100 n. We applied a square waveform at the driver input of 15
V with a frequency of 50 Hz and a rise- and fall time of 15 ns.
- 18 -
4.2, Experimental results.
The following signals are measured: Vce' Vge and Ie. The gate current I ~ is not
measured, because the distortion and the noise was in the same order as the SIgnal.
First we will show the gate driver input signal (see figure 4.3). (This signal is measu-
red with a lOx probe.)
I.S
1.8
EI.S
8.8
-
I I I I I
-
I- -
-
-
-
r- -
'- -
-
-
-
-
I- -
'- -
'- -
-
-
r--
-
I- -
-
-
-
-
I- -
I I I I
8.8s iEl.8ms ZEI.8ms 3E1.Elms
TIME
Figure 4.3. The measured gate driver input signal (10 VIV).
"EI.Elms
If we decrease the measurement time, we get more detailed pictures of the slopes of
the signals. In the following we will only show the detailed figures of the slopes.
The turn-on behaviour of the IGBT is given in figure 4.4 to 4.10 and the turn-off
behaviour is given in figure 4.11 to 4.17. Figure 4.4 gives the measured collector
current of the transistor. This was measured with a current probe, so the current is
given in Volt.
- 19 -
4B.Bus 3B.Blls 2B.BllS
TIME
B.Bs
8.2
8.3
8.1
8. Br-'*--..,----------;------;--------;-------..,-----
Figure 4.4. Measured collector current Ie (10 A/V); (turn-on).
As one can see, the current is mainly determined by the inductance of the load
circuit. The formula for the current in this case is:
,
u --
I =-(l-e t )
C R
L
't:-
R
The measured timeconstant f m is 17 ~ s . With L = 1.4mH and R = 250 the theoreti-
cal value is 5 2 ~ s . In our simulations we use a 450 ~ H inductor because this gives
better results (see figure 4.5). Not only for the collector current, but also for the
simulated voltages and currents. I have had no time to figure out why the measured
value of L was not correct.
- 20 -
4 OAT------------+------------+------------+------------+------------+------t
3 OAt t
,
,
,
,
,
,
,
,
,
OAt
,
2
+
,
,
,
,
1 OAf
+
o OA ------------+------------+------------+------------+------------+------+
Ous lOus 20us 30us 40us SOus
D 1 ( v m ~ )
Figure 4.5. Simulated collector current Ic;(turn on).
If we compare this with the measurements (figure 4.4), we see that this corresponds
very good. The timeconstant f here is about 19 I-LS, which is the almost the same as
f m =17 #loS. This is not strange because we adjusted the value of the conduntance.
Next we look at the collector-emitter voltage VCC' given in figure 4.6. (This signal is
measured with a 100x probe.)
- 21 -
1.B
B.75
C/)
f- B. 5
~
o
:>
B.25
-2BB.Bns -lBB.Bns 8.Bs 18B.Bns lBB.Bns 3BB.Bns 4 e ~ . B " s
TIME
Figure 4.6. Measured collector-emitter voltage Vee (100 VIV); (turn on).
As expected the voltage decreases rapidly, because the IGBT is conducting. The oscil-
lations are caused by parasitical inductances and capacitances. This is also to be seen
in the figures of the gate-emitter voltage.
The Vee calculated by PSPICE at turn-on is given in figure 4.7. We see that this
voltage decreases lineair. The fall-time of the simulated and the measured voltage
(see figure 4.6) are in the same order: te (measured) =:: 50 ns, t
f
(simulated) =:: 30 ns.
- 22 -
__
, ,
, ,
lOOV +------,
+
80V+
,
,
,
,
,
,
,
60V+
,
,
,
,
I
,
,
40V+
,
,
,
,
,
,
,
,
I
,
.;.
,
,
,
,
+
,
,
,
,
,
20
V
;- +
,
500"s
'lOOns 300ns 200ns
OV
Ons lOOns
c v(3)
Figure 4.7. Simulated C()llector-emitter voltage Vee; (tum on).
Figure 4.8 gives the measured gate-emitter voltage. This voltage is determined by
charging the gate capacitances as shown in figure 2.3.

I.e
Vol
!:i
o
:> e.s
e. el-----..L.------------------------
-1. Sus
The simulated Vge. shown in figure 4.9, shows a little difference. The waveform is the
same, but the timebase is different, about lOx. Probably the gate capacitance is bigger
- 23 -
then we assumed. We can't tell whether the overlapping capacitances are bigger or
the Cox is bigger, because we have no detailed infonnation about the lay-out of the
IGBT. So we leave this difference out of consideration for the moment.
1 6 V ~ - - - - - - - - - - - - - + - - - - - - - - - - - - - - + - - - - - - - - - - - - - + - - - - - - - - - - - - - ~ - - - - - - - - - - - - - ~
, ,
, ,
12v t
t
,
,
,
8V+ +
,
,
,
,
,
,
,
,
,
4V+
+
-ov - - - - - - + - - - - - - - - - - - - - - + - - - - - - - - - - - - - + - - - - - - - - - - - - - ~ - - - - - - - - - - - - - ~
Ons lOOns 200ns 300ns 400ns SOOns
o v(4)
Figure 4.9. Simulated gate-emitter voltage Vge; (turn on).
We also give the gate current I
g
(see figure 4.10). It is in accordance with expectati-
ons. Because I
g
is not measured, we can't comment on this picture any further.
- 24 -

,
,
,
,
,
+
OmA+---'
,
,
,
,
,
,
,
40mA+
,
,
,
.
I
,
,
,
,
,
,
: '
,
,
,
,
80mA t t
, ,
, ,
, ,
,

Ons lOOns 200ns 300ns 'lOOns SOOns
I (vmgl
Figure 4.10. Simulated gate current I
g
; (turn on).
Next we consider the turning-off behaviour of the IGBT, which gives the more
interresting figures. The collector current is measured as follows (see figure 4.11):
(The current is measured by a current probe.)

8.75
8.5
8.25
8.8s
-8.25
'--_-'--_...I...-_...I...-_...L-_...L-_...L-_-L-_-L-_.....J...._......J-_--.J.._---l._----.l_-.l__--.J
-5.8us
TIME
Figure 4.11. Measured collector current Ie (4 A/V); (turn off).
- 25 -
In this case the current is forced to zero by the transistor. The inductance of the load
and the parasitical capacitances are causing an oscillation in the main circuit. This
causes a negative voltage over the transistor. Because the IGBT can't take negative
voltages, a break-down mechanism of junction J2 (diode D2) will cause a negative
current peak. That this oscillation occurs is clearly to see in figure 4.13. But first we
will look at the simulated collector current.
4 OQ + - - - - -- - - +- - - - - - --+- -- - - - - - -+ - - - - - -- - +- - - - - - - - -+ - - - - - - - - +- - - - -- - - - ... - - --
o
,
t
,
,
,
,
+
,
,
,
+
1 OAt
o OAt
,
o
,
,
,
,
o
,
-lOA + - - - - - - - - + - - - - - - - -+- - - - - - - - -+ - - - - - - - - +- - - - - - - - -+ - - - - - - - - + - - - - - - - -+- - - ....;.
Ous 2us 4us flus Bus lOus 12us 14us
c 1 ( v m ~ ;
Figure 4.12. Simulated collector current Ie; (turn off).
If we compare this with the measured results, we see that this simulation shows good
agreement, except for the decreasing oscillation. We also see that the negative current
peak and the timescale of both phenomena are approximitly the same. I couldn't
trace the origin of the oscillation. The measured results show a bigger decrease of the
oscillation, this is also good to see in the next figures of the Vcc.(The collector-emitter
voltage is measured with a 100x probe.)
- 26 -
18.8
8. 8
Figure 4.13. Measured collector-emitter voltage Vce (100 VIV); (turn off).
2 OKYl' - - - - - - - - -+- - - - - - - - - +- - - - - - - - - -+- - - - - - - - --+ - - - - - - - - -+- - - - - - - - - +- - - - - - - - - -t
, ,
1 6KY +
,
,
1 2KY.L
,
,
,
o 8KY +
,
,
o 4KY+
o OKY
,
,
,
+
,
,
,
-+.
,
,
,
,

,
,
.+
,
,

,
t
,
,
-0
Ous Sus 10us 15us 20us 25us . 30us 35us
o v(3)
TIme
Figure 4.14. Simulated collector-emitter voltage Vee; (turn off).
Inthis figures we see the voltage peak due to the inductance of the load circuit. We
also see that the negative voltage is limited by the reverse break-down mechanism
(D2). The faster decay of the oscillation in the measured results may indicate a large
resistance in the IGBT.
- 27 -
As one can see, the overvoltage can reach very high values and can therefore be very
dangerous for the IGBT.
The last measurement is the gate-emitter voltage when the IGBT is turned off. (This
signal is measured with a lOx probe.)
1.B
8.5
8. BI------t+--------------------------j
8.Bs 25.8us 58. Bus 75.8us
TIME
Figure 4.15. Measured gate-emitter voltage Vge (10 VIV); (tum off).
This figure showes, besides the high frequency oscillations, the discharging current of
the gate capacitances.
- 28 -
l6V;- - -+------ -- -----+- ------- -----+ ---- -- ----- -+- ---- ---- ----+- --- ---------t-
, I :
12V+
+
,
,
,
.;.
. ,
+
8V+
,
,
,
,
,
,
~ v +
,
,
,
,
,
,
,
OV+
,
,
,
,
,
-
4V
t +
,
, :
-8v ~ - - ~ .. --- .. ------+- .... ----------+------- + ~ - - - ........ ~
Ous 20us 40uS 60us . 80us lOOus
v(4)
Figure 4.16. Simulated gate-emitter voltage VIc; (turn off).
The comparison of the V e's shows again good correspondance between the experi-
mental and simulated resu'ts, they have the same waveform and timescale. The Vie is
forced to zero by the function generator. Again we see the oscillation in the simulated
results. (See figure 4.16.)
At last we give the simulated gate current II (see figure 4.17). Because we have no
measurements of Ig' we can't make any conclusions about this signal.
- 29 -
80mQ + - +- - - - - - - -+. - - .... - ... - -+ - - - +- .... - .. - . - - ...... - - - .. - ... -+
, ,
'!OmA+
OmQ+
-40mQt
-80mQ t
,
,
,
+
t
,
o
,
,
,
,
t
,
,
-120ml=l+--+---------------+----+------- .. +----.-.--- .. ~
Ous 20us '!Cus 60us 80us' lOOus
1 (vmg)
Figure 4.17. Simulated gate current I g ~ (tum off).
At the end of the chapter, I want to' make a few remarks about the test and simulati-
on conditions:
The measurement results are recorded with an Nicolet 4094 oscilloscope and
processed \\oith VUPOINT, a digital data processing program.
The model by which the simulations were made, was adjusted during various
testruns.
The runtime for PSPICE was for the IGBT tum-off file was about 30 to 45
minutes and for the IGBT turn-on file about 15 to 20 minutes.
I used PSPICE version 4.02 and the program was ran on an AT with coproces-
sor emulator.
- 30 -
CHAPfER5
Conclusions.
In chapter 4 we have seen that the model gives results, which are in fair qualitative
agreement with the measured data. Because I had no detailed information about the
IGBT, it was difficult to make a more precise model.
Based on the comparison of simulation and measured results, we can conclude the
following:
The gate structure has to be reconsidered. We assumed that: 1) the space
charge in the oxide was equal to zero; 2) that the gate was rectangular; 3) that
the gate has no leak-resistance. This reconsideration is needed, because of the
difference between the simulated and measured figures.
Probably the thick n- and p-Iayer (collector side) have some resistance. This
may affect the oscillation in the simulations.
The depletion capacitances are voltage dependent in reality, so they have to be
changed in our model. The voltage dependency goes also for other capacitan-
ces and resistors, which are connected with semi-conductor material.
The model parameters have to be recalculated with the exact values of the
device structure and the dopingprofiles.
The thick p-Iayer probably contains recombination centres. This must be
implemented in the model.
The faster decay of the oscillation at the measured results, may indicate a
larger resistor in the IGBT. This resistance is probably due to the thick p- and
n-Iayer at the collector side of the IGBT.
- 31 -
LITERATURE
PSPICE 4.02 Manual; Microsim Corperation, Irvine, California, January 1989.
P. Antognetti and G. Massobrio; Semiconductor Device Modeling with SPICE;
New York, McGraw-Hill Book Company, 1988.
S.M. Sze; Semiconductor Devices, Physics and Technology; New York, Wiley
& Sons, 1985.
S.W.H. de Haan; Vermogenselektronica B; Dept. Electrical Engineering,
Eindhoven Univ. of Technology, febr. 1991.
R. Bayerer et al.; Insulated Gate Bipolar Transistor; 1
2
Elektrotechniek/Elek-
tronica, no. 10, oct. 1988.
BJ. Baliga; The Insulated Gate Transistor - A New Switching Power Device;
IEEE Ind. Appl. Soc. Meet., 1983, p. 794 - 803.
AR. Hefner and D.L Blackburn; An Analytical Model for the Steady-State
and the Transient Characteristics of the Power Insulated Gate Bipolar Transis-
tor; Solid State Electronics, Vol. 31, No.10 (1988), p. 1513 - 1532.
AR. Hefner, jr; Analytical Modeling of the Device-Circuit Interactions for the
Insulated Gate Bipolar Transistor (IGBT); Conf. Rec. IEEE Ind. Appl. Soc.
Meet., 1988, p. 606 - 614.
AR. Hefner; An Improved Understanding for the Transient Operation of the
Power Insulated Gate Bipolar Transistor; IEEE Power Electr. Spec. Conf.,
1989, part 1, p. 303 - 313.
B.W. Williams; Determination of Power Semiconductor Model Parameter
Values from Structure Data; Solid-state Electronics, Vol. 25, No.5 (1982), p.
395 - 410.
C.H. Xu and D. Schroder; Modeling and Simulation of Power MOSFETs and
Power Diodes; IEEE Power Electr. Spec. Conf. 1988, part 1, p. 76 - 83.
- 32-
APPENDIX A
IGBT data sheet.
.=0
_I
Power MOSIGTs
IXGP, IXGH, IXGM N-Channel
Conductivity Modulated Insulated Gate Transistors
PRELIMINARY INFORMATION
FEATURES
High current capabihty-10 to 30 Amps (continuous)
Low on-state conduction losses
MOS gate turn onloff drive simplicity
Extended 150
0
C safe operating area
Improved high temperature stability
Low input capacitance
Optimized for 60 Hz to 20 kHz switching
Very f ~ t tum-on, 200 ns typical
DESCRIPTION
MOSIGTs are a new class of power semiconductors that com-
bine the advantages of MOS gated drive simplicity with the cur-
rent handling capability of bipolar devices.
The basic cell design and gate characteristics of the MOSIGT are
very Similar to Power MOSFETs The dnve circuitry required to
control up to 30 Amps and 500 to 1000 Volts is basically the same
as a Power MOSFET with 3500 pf of input capacitance.
During tum-on of the MOSIGT, minority carrier injection into the
N- base region modulates the body on-resistance to a leve/1 0 to
20 times lower than an equivalent sized MOSFET resulting in a
proportIOnate 5 to 10 times Increase In current handling capabil-
ity. MinOrity carrier recombination during turn-off results in a (t
f
)
fall time of 0.5-1.0 IJ.S which is similar to bipolar devices.
Therelore, the MOSIGT is more suitable in low to medium fre-
quency high current power switching applications ranging from
60 Hz to 20 kHz and where low conduction losses are essential.
The IXGP, IXGH and IXGM family of high voltage MOSIGTs are
members of an advanced series of N-Channel Power MOS prod-
ucts which use HOMOS,. , 8 proprietary vertical OMOS technol-
ogy developed by IXYS.
HOMOS,. is a very planar, high density process which in-
corporates new techniques to improve operating characteristics
and stability at high voltages. This technology, combined with a
unique polysilicon gate cell structure significantly improves the
MOSIGT peak current at 150C to 2.5-3.0 times the continuous
rating. This advantage makes the MOSIGT ideal for many indus-
trial and commercial applications in power conversion and motor
control.
PRODUCT FAMILY
1
0
10
(1)A
STO
(CONT) (CONT)
Part Number(1)
Vos
at 25C at 90C VDS (ON) It VDS fON) It Page
i
50A 25A. 3.5V 1.5",s 2.7V 4.0fLS IXGH25N100,IXGM25N100 7
1000V 40A 20A 3.5V 1.011S 2.7V 3.01s IXGH20N100, IXGM20N100 8
i
20A 10A 35V 10",s 27V 3.0fLS IXGP10N100,IXGM10N100 9
50A 25A 3.5V 1.5",s 27V 4.0",s IXGH25N90. IXGM25N90 7
900V 40A 20A 3.5V 1.0fLS 2.7V 3.0",s IXGH20N90. IXGM20N90 8
20A 10A 3.5V 1.0",s 2.7V 3.0",s IXGP10N90, IXGM10N90 9
50A 25A 35V 1.5J.l.s 2.7V 4.0",s IXGH25NBO. IXGM25NBD 7
800V 40A 20A 3.5V 1.0",s 2.7V 3.0fLS IXGH20N80. IXGM20N80 8
20A 10A 35V 1.0",s 2.5V 3.0"'5
IXGP10N80. IXGM10NBO 9
50A 30A 30V O.B",s 2.5V 3.0fLS IXGH30N60, IXGM30N60 10
600V 40A 20A 30V 0.6",5 2.5V 2.0",s IXGH20N60, IXGM20N60 11
20A 10A 3.0V 0.6"'5
2.5V 2.0",s IXGP10N60. IXGM10N60 12
50A 30A 30V 0.8",5 2.5V 3.0",5 IXGH30N50. IXGM30N50 10
500V 40A 20A 30V 0.6",5 2.5V 2.0fLS IXGH20N50. IXGM20N50 11
20A 10A 3.0V 0.6",s 25V 2.0fLS IXGP10N50,IXGM10N50 12
(1) Note To specify the high speed 'K verSIon add an "A" suffiX to part number (see page 2 part number
description) .
IXGH SERIES
T0-247
(T0-3P)
IXGM SERIES
T0-204
(T0-3)
TQ.220 AS
PACKAGE OUTUNES AND PINOUTS
TQ.247 TO204 AE
IllN ,. GATE
2. DRAIN
3. SOURCE
l'IN ,. GATE
2. llIlAlN
3. 80UIlCf
11
. -- 54G R
H \.'" 1 L I i
V /
2. SOURCE U
CASE-DRAIN
DIm. Millim_ Inct>es
Min. Ma. Min. 101.
A 1423 1651 560 650
B 966 1056 380 420
C 356 482 140 190
0 064 089 025 035
F 354 408 139 161
G 229 279 090 110
H
- 635
-
250
J 051 76 020 030
I( 1270 1473 500
L 1 15 1 77 045 070
N 41'.3 533 190 210
Q 254 342 135
Fl 204 249 080 115
S 064 139 025 055
T 585 685 230 270
V 1 15
-
045
-
Dim.
A
B
c
o
F
G
H
J
J,
K
l
N
Q
R
MIllimeter
Min. Ma.
4.8 5.2
1.7 2.7
3.1 3.9
208 21.2
5.8 6.2
15.7 159
- 4.5
1.97 2.01
2.97 301
1 1.4
5.25 5.65
198 20.2
2.2 24
.4 .8
3.1 3.3
Inc,,"
Min. Ma.
.187 .203
.067 106
.121 .152
.811 .827
.226 242
.612620
.on078
.116 .119
039 .055
.207 .222
.n2 .n8
.086 .094
.016 .031
.121 .129
DIm.
B
c
o
E
F
G
H
K
a
R
u
Millo_
Min. Me.
- 3937
- 1971
658 681
'40 165
30 15 BSC
1074 11 05
546 esc
1668 17 12
11201198
3.86 411
2484 2527
419 556
Inctl.
Min. Ma.
- 155
- 776
259 268
.58 .062
055 065
1187 BSC
423 435
.215 esc
657 674
441 472
152 162
978 995
165 203
I
I
\
PART NUMBER DESCRIPTION
L.- Tum-Off Switching Speed
Blank = Standard Fall Time (t,)
A = High Speed (reduced
lalll.me. t,)
L..- Vos Breakdown
60 = 600 Volts
80= 800 Volts
100= 1000 Volts
GH 30 N 60
-r- -- -- -,- -- T
L Qptlonal Hi-rei Screening
(see pg. 14 lor test flow)
Blank = Standard
/J.JAN
IJTX.JANTX
IJTXV JANTXV
1
0
Current Rating -------------'
10= 10 Amps @ 9O'C
20 = 20 Amps @ 90'C
30 = 30 Amps @ 90'C
IX
IXYS T
Power MOS
MOSIGT PecQge Type ------'
GM = Metal Can TO204 (TO-3)
GP=TO-220
GH = TO-247 (TO3P)
L.--------Channel Polarity
N=N Channel
P=P Channel
Note: Valid combinations are only those referenced in the IXYS price book or product selector guide. Consult your locallXYS sales office to
confirm availability of specific combinations or new types.
2
MOSIGT CHARACTERISTICS
INTRODUCTION
The MOSIGT combines the best characteristics of power
MOSFET and bipolar devices in a single monolithic chip.
The simplified equivalent circuit for an N-channel MOSIGT
is a Darlington connection of an N-channeJ MOSFET and a
PNP bipolar transistor as illustrated in Figure 1a. The verti-
cal structure of the MOSIGT as shown in a cross-section
view in Figure 1b further describes the operation of the
device. The MOSIGT is turned on by applying a positive
voltage to the gate of the MOSFET which in tum supplies
base current to the PNP transistor formed in the vertical
structure between the P+ substrate. n-epitaxial base region
and P-well.
The bipolar output characteristics offer ten times improve-
ment in on-state voltage drop (VOS(ON)), which significantly
reduces conduction losses when compared to an equiva-
lent size MOSFET. The MOS gated input characteristics
allow the MOSIGT to be,lfoltage driven similar to MOSFETs
which reduces the complexity and cost of drive circuit
design. Since the MOSIGT utilizes minority carrier injection
to improve current density, its turn-off behavior is a combi-
nation of MOSFET and bipolar characteristics. The turn-off
time tends to be intermediate between MOSFET and bi-
polar devices of similar size. .
FORWARD AND REVERSE
OFF-STATE BLOCKING
The MOSIGT will block applied forward voltage up to the
onset of avalanche at its breakdown voltage. IXYS specifies
a guaranteed maximum voltage (BVoss). which is some-
what less than the actual breakdown and specified at a
leakage current of 2501J.A.
Unlike the MOSFET, the MOSIGT does not conduct in the
reverse direction, and actually has a small reverse blocking
capability in the range of 5 to 10 volts. Because the reverse
junction in the MOSIGT is not passivated, IXYS does not
guarantee this reverse blocking capability and recommends
that it not be depended upon to block reverse voltages.
Since the MOSIGT does not have an internal anti-parallel
diode, a free-wheeling rectifier must be added externally In
those applications which require reverse currents imposed
by the load. With the absence of the internal parasitic diode,
MOSIGTs do not suffer from simultaneous reverse conduc-
tion problems in the free-wheeling mode which can occur in
MOSFETs.
GATE
02
NIDulter)
SOURCE
N-(ep')
p.
DRAIN
GATE
MINORITY CARRIER
INJECTION
DRAIN
SOURCE
(a) POWER MOSIGT
EOUIVALENT
CIRCUIT
(b) CROSS SECTION OF
A MOSIGT
Figure 1. Basic MOSIGT Operation and Device Symbol
3
(e) MOSIGT
SYMBOL
Figure 2. Typical MOSIGT Output Characteristics
o 2 3 4 5 6 7 8 9 10
Vos (VOLTS)
Figure 3. Typical VDS(ON) Yersus Temperature
IXGH20N60
I
' 0 = 2OA-
-
I
~
~
10 =lOA
-r--
i'-.
.......
.........
~
'"
~
10 = 1.0A
...........
r---......
"
,
\..
150 50 75 100 125
JUNCTION TEMPERATURE (OC)
25
IXG
1
H20N60
I ~ ~
T
c
= 25'C
~ ~ ~
II II II
" " "
~ 0 ~ 0 ~ 0
,/1/
VGS =8V
'I /
I
rj /
Vas - 7V_
to--
'I
I I
'/
r/v
Vas =6V
fit'"
~
V VGS =5V
~
~ 1.0
>
o
W
N
~ 0.9
::E
a:
o
z
0.8
1.1
20
18
16
_ 15
~ 14
! 12
.9 10
8
6
4
2
DRIVING MOSIGTs
The MOSIGT has input characteristics similar to a power
MOSFET; a voltage drive with a capacitive input impedance
and a threshold voltage (VGS(lhl)' which is between 2.5 to
50 volts. Typical output charactenstics. shown in Figure 2,
illustrate the behavior of the devices. Turning the MOSIGT
on and off is virtually identical to driving a power MOSFET.
An advantage of the MOSIGT over MOSFETs for similarly
current rated devices is its input capacitance, which is sig-
nificantly less than the MOSFET. Also, the ratio of gate-
drain capacitance to gate-source capacitance is lower by at
least a factor of 3, which further eases the gate drive
requirements.
When a MOS-gated power device switches, the rapid fall
(at tum-on) and rise (at turn-off) of the drain-source voltage
injects current into the gate circuit through the gate-to-drain
capacitance C
rss
' The gate drive circuit must present a low
enough impedance. especially during turn-on where dVlls/dt
can be very large, to keep the induced gate Voltage tran-
sient within reasonable bounds. The potentially large dlct"dt
present during turn-on can induce a transient voltage in the
source connection. The gate-drive circuit must be located
very close to the actual source lead of the power device,
and the impedance of the source return path to ground
must be kept low. Source connection lengths on the order of
several inches may cause unacceptable gate-source volt-
age transients.
Turn-off of a MOSIGT is less sensitive to stray circuit induc-
tance due to the lower levels of dV/dt and dlidt. However, a
very high gate voltage slew rate (dVgs/dt) during turn-off can
create internal displacement currents that reduce the turn-
off Safe Operating Area.
,IXYS recommends that a gate drive voltage of 12 to 15 volts
pe used to drive the MOSIGT for optimum operating perfor-
mance. IXYS' MOSIGT on-state and switching characteris-
ics are specified with a VGS of 15 volts and are guaranteed
t 25C and at elevated temperatures.
NSTATE CHARACTERISTICS
uring conduction. the MOSIGT exhibits two distinct
egions of operation similar to the behavior of a bipolar
ransistor; the saturation region and the linear region. It is
mportant to note that for the MOSIGT, these regions are
efined in the same manner as a bipolar transistor and
pposite the definitions for a MOSFET. These regions are
lIustrated in Figure 2.
'n the saturation region. the on-state voltage (VOS(ON), is a
unction of drain current, gate dnve voltage (VGs), and tem-
,erature. IXYS guarantees a maximum VOSiO
N
) in the
>aturation region at the device's rated continuous current
'D). with a VGS gate dnve of 15 \/Otis and T
J
at 25C.
II. distinct advantage of the MOSIGT is its significantly
ligher current handling capability and reduced temperature
:oefficient over the entire temperature range. As shown in
=igure 3, VOS(ON) increases only 8% from 25C to 150C
unction temperature. At small drain currents. the tempera-
ure coeffiCient of VOS(ON) is slightly negative, similar to a
lipolar device.
n the linear region, the MOSIGT characteristics are stable
lnd linear over a very broad range of voltages and currents.
"he MOSIGT is well suited for a wide variety of high power
near amplifiers and regulators.
4
PEAK CURRENT RATING AND DESATURATION
The peak current rating of the MOSIGT (10M), is the maxi-
mum current at which the device is guaranteed to operate
without failing or losing tum-off control of the device so long
as the junction temperature is maintained below 150C.
IXYS' MOSIGTs also exhibit a desaturation feature
the peak current rating when VGS is 15 volts or less. When
an external circuit fault tries to force the MOSIGT current to
exceed the peak current or what can be supported by the
applied VGS (see Figure 2. output characteristics), the
device comes out of saturation. Once desaturation occurs,
the device must be turned off as quickly as possible in order
not to exceed the maximum power dissipation of the device.
SWITCHING CHARACTERISTICS
During turn-on, the MOSIGT sWItching periormance is
dominated by the MOS gate structure. When the gate drive
voltage is brought above the threshold voltage, the MOS-
FET structure is enhanced and very quickly starts to con-
duct (see Figures 1a & 1b). The MOSFET drain current
becomes the base current of the bipolar PNP structure,
Which turns on in the order of 50 nsec. As a result, the
MOSIGT turn-on switching speed is very fast, similar to
power MOSFETs of equal input capacitance (C1SS)'
There are three distinct time intervals that comprise the
total turn-off time of MOSIGTs, as shown in Figure 4.
First is the turn-off delay time which is dominated
by the time required for the gate drive circuit to pull VGS
from 15 volts down to just above the level at which the dram
current begins to decrease.
The second interval is the initial fall time (t,,), which is the
time required for the gate drive circuit to remove the charge
injected into the gate by the gate-to-drain capacitance as
VOS increases during turn-off. The tt, period is defined as
the time it takes for 10 to drop from 90% of full current down
to approximately the 20% level. In IXYS MOSIGTs, tt1
ranges between 100 to 200 nsec and is influenced by gate
drive design and RGS drive impedance.
The third interval. designated t'2, is controlled by minority
carrier recombination in the bipolar PNP structure. The rate
at which minority carriers in the base region recombine can
significantly influence t'2 from 0.51-'-s to 2.0J.Ls depending on
the IXYS MOSIGT device type. (standard or "A" version).
Unlike bipolar devices, tt2 cannot be influenced by the gate
drive circuit because the base region of the PNP bipolar
structure is not available eX1ernally to pull minority carriers
out through a reverse bias base drive scheme The only
approach to reducing tt2 is through minority carrier life time
control which is a function of device design and process
technology.
20V
STANDARD AND "A" (HIGH SPEED) VERSIONS
IXYS has developed a proprietary process which has signif-
icantly reduced tt2 and allows the MOSIGT to be optimized
for either low frequency 5kHz) or high frequency (10 to
20kHz) switching applications. The IXYS standard MOSIGT
offers switching speeds in the range of 2 to 4lJ.s and
features a maximum VOS(ON) of 2.5 to 2.7 volts at rated
current for minimizing conduction losses in switching appli-
cations below 5kHz.
For higher speed switching applications. up to 20kHz. IXYS
offers a high performance version specified by adding an
MA" suffix to the part number (i.e., IXGH20NSOA) with maxi-
mum inductive load fall times in the 0.51-'-s to 1.0J.LS range at
125C junction temperature. The tradeoff to achieve the
faster switching turn-off in the "A" version is VOS(ON1. which
is approximately 25% higher than IXYS' standard MOSIGT.
Ir
-------+-
I
I
I
I
I
I I
I I
I I
I I
I I
10",
I I I
I I I
II I
'0
I I
I J-----'!--4
10V
Figure 4. MOSIGT SWitching Waveforms
5
.r-.
I
Figure 5. Clamped Inductive Test Circuit
Vary E,
OUT -=- E
,
to Obtain
ReqUired 10
HANDLING PRECAUTIONS
Because MOSIGTs utilize Metal-Oxide-Semiconductor
process technology, care must be taken to ensure that VGS
never exceeds BVGSS or permanent damage to the device
may result. Many circuits can cause transients that may
compromise the MOSIGT in this manner. In applications
prone to potential transient conditions, an external zener or
transient suppressor is recommended.
Due to its extremely high input impedance, the MOSIGT
like the power MOSFET, is sensitive to electrostatic dis-
charge. While the input capacitance of these devices is
relatively large, it is still possible for the human body to
store enough charge to destroy a MOSIGT on contact.
Reasonable precautions in handling, packaging and storing
these devices should be observed. This includes, but is not
limited to, use of .anti-static workstations at any point requir-
ing the handling of these devices.
Figure 1a) which under very high re-applied dVidt condi-
tions during turn-off, will induce a lateral displacement cur-
rent which can force the bipolar structure to conduct,
resulting in loss of control and potential device failure.
IXYS recommends that care should be taken to limit the
re-applied dVos/dt to typically less than 2000 VIIJ.S in most
inductive load applications. This can be accomplished in
two ways; external snubbers can be used to limit re-applied
dVos/dt which is a common approach used in most high
speed power switching applications, or the series gate
resistance (RG) of the drive circuit (see Figure 6, switching
time test circuit) can be increased to a value which reduces
the turn-off switching speed of the device thereby limiting
dVos/dt. The latter approach controlling RG is often more
economical when switching speed requirements are lower
L
0.050
DUT
Ec =0.8 BVos
s
E, = 0.5 BVoss

Vary t
p
to
Obtain Required Peak 10
20
Figure 7. 'TYPicaIIXGH20N60 Tum-off Operating Area
IXGH20N60 I I I
- Clamped InduClive Load
L = I I I
...... T
J
= 150'C
dVosdl =-

.....

' ..


700 600
300 400 500
Vos (VOLTS)
200
10
40
50
Figure 6. Resistive Load Switching Time Test Circuit
_ 0.05!l
SAFE OPERATING AREA
The Forward Biased Safe Operating Area (FBSOA) for the
MOSIGT during tum-on and steady-state conductIon peri-
ods is thermally limited. Like the power MOSFET, the
MOSIGT does not exhibit the second breakdown phenome-
non common to bipolar devices. Care should be taken,
however, not to exceed the maximum power dissipation
and 150C junction temperature of the device under all con-
ditions for guaranteed reliable operation.
The MOSIGT is also subject to a different safe operating
area during turn-off, especially under inductive load condi-
tions. A typical turn-off SOA curve is shown in Figure 7 for
IXYS' 20 amp MOSIGT. Similar to MOSFETs, the MOSIGT
has a parasitic bipolar structure (shown in the dotted area of
6
/
IXGH25N80, 90, 100
IXGM25N80, 90, 100
25 AMPS, 800-1000 VOLTS
MAXIMUM RATINGS
IXGH25N80 IXGH25N90 IXGH25N100
Parameter 8ym. IXGM25N80 IXGM25N90 IXGM25N100 Unit
Drain-Source Voltage (1)
Voss
BOO 900 1000 V
dc
Drain-Gate Voltage (RGS = 1.0Mfl) (1)
VOGR
800 900 1000 V
dc
Gate-Source Voltage
VGS
:: 30 :: 30 :: 30 V
dC
Drain Current Continuous Tc = 25C 10 50 50 50
Actc
Tc c 90C 25 25 25
Drain Current Peak (3)
10M
100 100 100
Actc
Total Power Dissipation @ 25C
Po 200 W
Power Dissipation Deraling > 25C 1.67 W"'C
Operating and Storage Junction Temperature TJ & T
5t9
-65 to +150 C
Thermal ReSistance
RthJC
0.6 crw
ELECTRICAL CHARACTERISTICS TC = 25C unless otherwise specified
Parameter Type Min. Typ. Max. Units Test Conditions
BVoss
Drain-Source Breakdown Voltage 25NBO. BOA 800 - -
V VGS = OV
25N90.90A 900 - -
V 10 = 250,.,A
25N1oo. 100A 1000
- -
V
VGS(thl
Gate Threshold Voltage ALL 2.5 - 5.0 V VOS = VGS. 10 = 250,.,A
IGSS
Gate-Source Leakage ALL - - 100 nA VGS K ::30V
-
loss
Zero Gate Voltage Drain Current
- -
200 ,.,A VOS = Max. Raling x 0.8. VGS = OV
ALL
-
- 1000 ,.,A VOS = Max. Rating x 0.8. VGs= OV. Tc = 125
c
C
VOS (ON) Drain-Source On Voltage 25N80. 90. 100 - - 2.7 V VGS = 15V. 10 = 25A
25N80A. 90A
100A - - 3.5 V
G,s
Forward Transconductance (2) ALL 8.0
- -
S Vos= 10V. 10 = 12.5A
I C,ss
Input Capacitance ALL - - 3500 pF VGS = OV. Vos = 25V. f = 1.0 MHz
Coss
Output Capacitance ALL - - 250 pF
C
rss
Reverse Transfer Capacitance ALL
- - 50 pF
SWITCHING CHARACTERISTICS
RESISTIVE LOAD
!dCon)
Turn-On Delay Time ALL - -
100 ns Resistive Load, TJ = 125
c
c:
t
r
Current Rise Time ALL
- -
200 ns 10 = 25A. VOS= Rated \loss x 0.8
!dCOff)
Tum-Qtl Delay Time ALL - - 1.0
IJS
VGS= 15V
tf
Current Fall Time 25NBO. 90. 100
-
- 3.0
IJS
RGS = 100fl
25NBOA, 9OA,
100A - -
1.0
IJS
INDUCTIVE LOAD
!dCOff)
Tum-Qtl Delay Time ALL - -
1.0
IJS
Inductive Load, TJ = 125
c
C
tf Current Fall Time 25N80, 90, 100
- -
4.0
IJS
L = 100 IlH, 10 "'. 25A
25N80A, 9OA,
- -
1.5
IJS
VOS (Clamp) = Rated Voss x 0.8
100A VGS = 15V, RGS = 100fl
(ll T
J
C 2S'C to lS0'C
(2) Pulse Test: Pulse width .. 300ms. duly cycle'" 2%
(3) Repetitive Rating: Pulse Width limned by max Junction temperature
7
APPENDIX B
PSPICE inputfile static analysis IGBT.
IGBT ANALYSIS
VA 10 0
VMA 103
VG500
VMG 50 5
RG 4 5 1000HM
Xl 3 4 0 MODELIGBT
.SUBCKT MODELIGBT 1 2 3
*#1: COLLECTOR #2:GATE #3: EMITTER
*TESTMODEL ONTWIKKELD DOOR CAMIEL VERHOEVE
R1341UOHM
R2 6 3 1UOHM
D145 DMOD1
D215 DMOD2
Q145 1 QMODI
Q25 4 3 QMOD2
Ml 523 6 MMODI W= lOMM
C1 23 150PF
C2 25 30PF
CJE1 1 5 3.5NF
CJC1 4 5 O.3NF
CJE234 O.lNF
.MODEL DMOD1 D(BV =2500)
.MODEL DMOD2 D(BV=20,IS=1.0E-30)
.MODEL QMODI PNP(BF= 1,IS= 1.4E9,TF= 1US)
.MODEL QMOD2 NPN
.MODEL MMOD1 NMOS(VTO=5V,KP=0.5)
.ENDS MODELIGBT
.DC VA 0 10 0.1
.STEP VG UST 0 5.2 53 5.4 5.5 5.6 10 15
.PROBE I(VMA)
.TEMP 27
.END
PSPICE inputfile IGBT (turn on).
IGBT ANALYSIS
VA 10 0 l00VOLT
VMA 10 1
VG 50 0 PWL(O 0 50N 0 65N 15 IODU 15)
VMG SO 5
lL 12 450UH
RL 2 3 26.80HM
RG 4 5 l000HM
Xl 3 4 0 MODELIGBT
.SUBCKT MODEUGBT 1 2 3
*#1: COLLECTOR #2:GATE #3: EMITTER
*TESTMODEL ONTWIKKELD DOOR CAMIEL VERHOEVE
R1341UOHM
R2 6 3 lUOHM
D145 DMODI
D215 DMOD2
Ql 45 1 QMODI
Q25 4 3 QMOD2
Ml 523 6 MMODI W= 10MM
C1 23 150PF
C2 25 30PF
CJEl 1 5 3.5NF
CJCl 4 5 0.3NF
CJE2340.1NF
.MODEL DMODl D(BV=2500)
.MODEL DMOD2 D(BV=20,IS=1.0E-30)
.MODEL QMODI PNP(BF= 1,IS= 1.4E-9,TF= IUS)
.MODEL QMOD2 NPN
.MODEL MMODI NMOS(VTO=5V,KP=0.5)
.ENDS MODEUGBT
.TRAN 1U tOOD
.PROBE I(VMA) I(VMG) V(3) V(4)
.TEMP 27
.END
PSPICE inputfile IGBT (turn off).
IGBT ANALYSIS
VA 100 100VOLT
VMA 10 1
VG 50 0 PWL(O 15 50N 15 65N 0 lODU 0)
VMG 505
LL 1245000
RL 2 3 26.80HM
RG 4 5 1000HM
Xl 3 4 0 MODELIGBT
.SUBCKT MODEUGBT 1 2 3
*#1: COLLECfOR #2:GATE #3: EMITfER
*TESTMODEL ONTWIKKELD DOOR CAMIEL VERHOEVE
R1341UOHM
R2 63 1UOHM
D145 DMODI
D2 15 DMOD2
0145 10MODI
025430MOD2
M1 5236 MMODI W=lOMM
Cl 23 150PF
C2 25 30PF
CJE1 1 5 3.5NF
CJC1 4 5 0.3NF
CJE234 O.INF
.MODEL DMODI D(BV=2500)
.MODEL DMOD2 D(BV=20,IS=1.0E-30)
.MODEL OMOD1 PNP(BF= l,IS= 1.4E-9,TF= IUS)
.MODEL OMOD2 NPN
.MODEL MMODI NMOS(VTO=5V,KP=0.5)
.ENDS MODELIGBT
.TRAN IU 100U
.NODESET V(3) =0
.PROBE I(VMA) I(VMG) V(3) V(4)
.TEMP 27
.END