A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation For Sensing in CMOS Imagers
A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation For Sensing in CMOS Imagers
A 1-Bit Analog-To-Digital Converter Using Delta Sigma Modulation For Sensing in CMOS Imagers
00 Of" ""'---f-----""'--f--
1
,., , , ,,'
,'. . . . .
" 't'" ., ...... j[ ..... t'"\+!.\.:
=, : ', :,:
00' , --.'
. . . . .
-50 , 0 ; .. _ .... :, --_. --- --- .:, .......... ,: - : .. --- ....... :
60S a '10 a ' I S 0 '20 0 '25 0 610 0
1'1& ..... .1.21 . ' .,., mplde SdtlillC
LooklnSAI Indl\'.dual pulses of figure 3.20 in fi gure ).21 we can see thai there 1I
mcomplete 5dlhnJ i.e, the currenl In the bit hoc: docs DOl go 10 zero ... hen phiZ goes high.
This is we to clock fecdlhmugh. l.o ... mng!he cloek freqJ>ellCy o(the CI!CUII WIll rcdllCC.
the incomplete ICtlhng of the Ci rcUit as seen In the simulation of figu!e 3.22. li ere the
time period iJ lOris.
34
"'
tliD 0,-- -_ ..... ....... -- -' .. - ....... -.
. ........ -
,
,
,
, ______ 300.0, ..... -- --f- f ----f _ ----_ .. t
-_._-_ ... -:
CUltt1li through
the bit line
00 . 0 : ... -
--_ .. _- "
100
,
..... ....... -_ ........ __ .. -. __ ...... .
, ' '
, , ,
, ' '
, ' '
, ' ,
\ f""""': """ "" ,:
1
, ,
_ ........ '
60506100
6lS 0
-_ ........ . -- -_ .. ...... .
&20 0
oS
625 0
Figure 3.21. Lo .... ering Clock Frequency to reduce Incumpl ttc Settling
- _ ..
6313 0
"
Figure 3.23. DSM Input Circuit
Figure 3.23 shoWl! the DSM input circui l (2\ consisti ng of NMOS source
followers and the: feedback circuit. The MOSFITs MI and M2 1m' II1lKk: vt'ry wide so
thai it 11M ViS very dose \0 Vthn. If the signal from the oompanuor 1l0C!! high the
resistor (SCR) in the reference signal feedback path is enabled. If the r e f e T ~ signal is
greater than the desired signal we want to me35ure, Ihm the CIIITCTI\ in the reference path
will be greater than the current in the desired signal path (sioce Vgs of Ml is greater than
Vgs of M2). The MOSFET M4 (charge oontrolling switch) in !be desired signal path is
al .... ays enabled. The eapacioor on the: node Vsig l is charged .... ith the d i f f e ~ in the
CWTCnl.S ITdlsig.
The PMOS current mIrror can ideally source the same cUlTCnl through each side
and .. mn Vn:f >Vsig MI can sink more cum:nt due to it's higheT gale \'oltage than M4
36
resulting in chasEing the capac:ilOr on the node Vsigl 10 II higher voltage the Q signal
from the comparator goes low IhWl Hlcreasing the charge on node Vren.
Wbto swi1ch M4 closes., the amounl of charge dumped on 10 !he capacitor in the desn'ed
When swilCb M3 closes. the amount of charge dumped on 10 the eapatu.or in the:
ngun: 3.24 shows the si mulation showmg voltages on the nodes Vren and Vsigl. which
Ideally 1rnCir: each other due \0 the f<tbad:.
,
"
Voltage V
1
,
"
. "
" "
"
Vrefl
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