RT3624BE

Preliminary RT3624BE
Dual Channel PWM Controller for IMVP9.1 CPU Core Power

Supply
General Description Features
 Intel IMVP9.1 Compliant
The RT3624BE is a synchronous buck controller which
 4/3/2/1 Phase (CORE VR) + 2/1 Phase (AXG VR)
supports 2 output rails and can fully meet Intel IMVP9.1
PWM Controller
requirements. The RT3624BE adopts G-NAVPTM
 G-NAVPTM (Green Native Adaptive Voltage
(Green Native AVP) which is Richtek’s proprietary
Positioning) Topology
topology derived from finite DC gain of EA amplifier
 0.5% DAC Accuracy
with current mode control, making it easy to set the
 Differential Remote Voltage Sensing
droop to meet all Intel CPU requirements of AVP
 Built-in ADC for Platform Programming and
(Adaptive Voltage Positioning). Based on the
Reporting
G-NAVPTM topology, the RT3624BE features a new
 Accurate Current Balance
generation of quick response mechanism (Adaptive
 Diode Emulation Mode at Light Load Condition
Quick Response, AQR) to optimize AVP performance
 Fast Transient Response-Adaptive Quick
during load transient and reduce output capacitors. The
Response (AQR)
RT3624BE integrates a high accuracy ADC for platform
 VR Ready Indicator
and function settings, such as ICCMAX, switching
 OVP,OCP, UVP with Flag
frequency, over-current threshold or AQR trigger level.
 Switching Frequency Range Setting
The RT3624BE provides VR Ready and thermal
 DVID Enhancement
indicators. It also features complete fault protection
 Acoustic Noise Suppression
functions including over-voltage (OV), under-voltage
 Zero Load-line
(UV), over-current (OC) and under-voltage lockout
 Rail Disable
(UVLO).
 Support Phase Doubler RT9637 for CORE rail Up
Applications to 6-Phase Operation (optional)
 IMVP9.1 Intel CORE/AXG Supply  Support SPS Application (optional)
 Desktop and Notebook Computer  Soldering Good Detection
 AVP Step-Down Converter  RT3624BE : Support Address 00 and 01
 Small 52-Lead WQFN Package
Simplified Application Circuit

RT3624BE RT3624BE
To PCH VR_READY PWM1 RT9610C MOSFET VR_READY PWM1 Dr.MOS
To PCH
PWM2 RT9610C MOSFET VCORE

VR_HOT PWM2 Dr.MOS VCORE
VR_HOT
VCLK PWM3 RT9610C MOSFET
To CPU VCLK
VDIO PWM3 Dr.MOS
To CPU
PWM4 RT9610C MOSFET VDIO
ALERT
PWM4 Dr.MOS
ALERT
PWMA1 RT9610C MOSFET
To Driver DRVEN
VAXG
PWMA1 Dr.MOS
PWMA2 RT9610C MOSFET
To Dr.MOS DRVEN_F
PWMA2 Dr.MOS VAXG
Copyright © 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation
DS3624BE-P03 February 2021 www.richtek.com
1
RT3624BE Preliminary
Ordering Information Pin Configuration
RT3624BE (TOP VIEW)
Package Type
QW : WQFN-52L 6x6 (W-Type)
DRVEN_F
VIN/VSYS
DBLR_PS
ANS_EN
Lead Plating System
PWMA1
PWMA2
DRVEN
PWM3
PWM4
PWM2
PWM1
VRON
VCC
G : Green (Halogen Free and Pb Free)
Note : 52 51 50 49 48 47 46 45 44 43 42 41 40
ISEN3P 1 39 ISENN_AUX
Richtek products are : ISEN3N 2 38 ISENP_AUX
ISEN4N 3 37 ISENA1N
 RoHS compliant and compatible with the current ISEN4P 4 36 ISENA1P
ISEN2P 5 35 ISENA2P
requirements of IPC/JEDEC J-STD-020.
ISEN2N 6 34 ISENA2N
 Suitable for use in SnPb or Pb-free soldering ISEN1N 7 GND 33 FBA

ISEN1P 8 32 COMPA
processes.. FB 9 31 VSENA
COMP 10
53
30 RGNDA
VSEN 11 29 PSYS
Marking Information RGND 12 28 IMON_AUX
VREF_SPS 13 27 SET4
RT3624BEGQW : Product Number 14 15 16 17 18 19 20 21 22 23 24 25 26
RT3624BE YMDNN : Date Code
VR_READY
VCLK
VDIO
ALERT
VR_HOT
IMON
VREF
IMONA
TSEN
TSENA
SET1
SET2
SET3
GQW
YMDNN
WQFN-52L 6x6
www.richtek.com DS3624BE-P03 February 2021
2
Functional Pin Description
Pin No. Pin Name Pin Function
8, 5, 1, 4 ISEN[1:4]P Positive inputs to current-sense amplifier for Phase 1 to 4 of VR CORE rail.
Negative inputs to current-sense amplifier for Phase 1 to 4 of VR CORE
7, 6, 2, 3 ISEN[1:4]N
rail.
Negative input of the error amplifier. This pin is for CORE rail VR output
9 FB
voltage feedback to controller.
10 COMP CORE rail VR compensation. This pin is an error amplifier output pin.
CORE rail VR voltage sense input. This pin is connected to the terminal of
11 VSEN
CORE rail VR output voltage.
Return ground for CORE rail VR. This pin is the negative node of the
12 RGND
differential remote voltage sensing.
Fixed 1.3V output reference voltage. This voltage is used to offset the
13 VREF_SPS smart power stage. Between this pin and GND must be placed an exact
0.22µF decoupling capacitor.
14 VR_READY VR ready indicator.
15 VCLK Synchronous clock from the CPU.
16 VDIO VR and CPU data transmission interface.
17 ALERT SVID alert. (Active low)
18 VR_HOT Thermal monitor output. (Active low)

CORE rail VR current monitor output. This pin outputs a voltage
19 IMON
proportional to the output current.
Fixed 0.6V output reference voltage. This voltage is used to offset the
output voltage of all IMON pins. While controller shut down or set all rail in
20 VREF
PS4, voltage source shuts down. An exact 0.47µF decoupling capacitor
and a 3.9Ω resistor must be place between this pin and GND.
AXG rail VR current monitor output. This pin outputs a voltage proportional
21 IMONA
to the output current.
Thermal sense input for CORE rail VR and function for current gain (Ai)
22 TSEN
and adaptive quick response trigger level for CORE rail VR
Thermal sense input for AXG rail VR and function for current gain (Ai) and
23 TSENA
adaptive quick response trigger level for AXG rail VR.
Function setting for ICCMAX and VBOOT of CORE rail and ICCMAX of
24 SET1 AXG rail. Connect the SET1 pin and SET3 pin to 5V and pull the VRON
high. If the soldering is good, both rail outputs are non-zero VBOOT.
Function setting for VBOOT of AXG rail and on-time width setting
25 SET2 (switching frequency) of CORE rail, selectable VID table, zero load line and
ICCMAX of AUX rail.
Function setting for undershoot suppression, DVID fast slew rate, DVID
26 SET3
voltage compensation and VR_HOT assertion during DVID current limit.
Function setting for phase number with RT9637 of CORE rail, on-time
27 SET4 width setting (switching frequency) of AXG rail and anti-overshoot trigger
level.
AUX rail VR current monitor output. This pin outputs a voltage proportional
28 IMON_AUX
to the output current.
3
Pin No. Pin Name Pin Function
System input power monitor. Place the PSYS resistor as close to the IC as
possible. The input power domain (SVID Address 0x0Dh) rail can be
disabled by pulling the voltage at the PSYS pin > (VCC – 0.5V). RT3624BE
29 PSYS
will reject any commands to the input power domain rail. If the platform
doesn't support PSYS function, It is recommended to connect PSYS pin to
GND to avoid affecting system performance.
Return ground for AXG rail VR. This pin is the negative node of the
30 RGNDA
differential remote voltage sensing.
AXG rail VR voltage sense input. This pin is connected to the terminal of
31 VSENA
AXG rail VR output voltage.
32 COMPA AXG rail VR compensation. This pin is an error amplifier output pin.
Negative input of the error amplifier. This pin is for AXG rail VR output
33 FBA
voltage feedback to controller.
37, 34 ISENA[1:2]N Negative inputs to current-sense amplifier for Phase 1 to 2 of VR AXG rail.
36, 35 ISENA[1:2]P Positive inputs to current-sense amplifier for Phase 1 to 2 of VR AXG rail.
38 ISENP_AUX Positive input to current-sense amplifier of VR AUX rail.
39 ISENN_AUX Negative input to current-sense amplifier of VR AUX rail.
External driver mode control. As received PS4 command, this pin will be
high state. This pin can work with RT9637 on 1 PWM drive 2 power stage.
40 DBLR_PS As PS0 command is received, this pin will be low state. As PS1 command
is received, this pin will be floating state. As PS2/3 command is received,
this pin will be high state.
External driver mode control. As PS4 command is received, this pin will be
41 DRVEN
low state. The output high level is VCC.
External driver mode control. As PS4 command is received, this pin will be
42 DRVEN_F
floating state. The output high level is VCC.
44, 43 PWMA[1:2] PWM outputs for AXG rail VR. The tri-state window = 1.6V to 2.2V.
45, 46, 48, 47 PWM[1:4] PWM outputs for CORE rail VR. The tri-state window = 1.6V to 2.2V.
Acoustic Noise Suppression function setting. When the pin is pulled to
49 ANS_EN
VCC, this function can be enabled. This pin is not allowed to be floating.
Controller power supply. Connect this pin to 5V and place a RC filter, R =

50 VCC 2.2Ω and C = 4.7µF. The decoupling capacitor should be placed as close
to PWM controller as possible. The recommended size of RVCC is 0603.
51 VRON VR enable control input.
52 VIN/VSYS VIN/VSYS input pin. Connect a low pass filter to this pin to set on-time.
53 Ground. The Exposed Pad must be soldered to a large PCB and
GND
(Exposed Pad) connected to GND for maximum power dissipation.
4
Functional Block Diagram
VR_READY
VR_HOT
VSENA
TSENA
ALERT
VRON
VSEN
PSYS
TSEN
VCLK
SET1
SET2
SET3
SET4
VDIO
VCC
IMONAVG
IMONAAVG
IMON_AUXAVG
UVLO GND
MUX
ADC
SVID Interface
Configuration Registers PIN Function
Control Logic DBLR_PS
VID Controlx Setting Code
Loop Control/ DRVEN
Protection Logic
DRVEN_F
ANS_EN
Loop logic
control
VID VIN/VSYS
VID Control
DAC
ERROR
AMP PWM
RGND Offset Loop logic control
+ CMP
Cancellation + PWM1
FB -
+ - TON
COMP ZCDx PWM2
GEN/
VCBx Driver
ISEN1P + Gm Interface PWM3
ISEN1N - IIMON1 kTON[2:0]
+ PWM4
ICB1
IZD1 -
Ai[1:0] Ring-back
ISEN2P + Gm Control RAMP
ISEN2N - IIMON2
ICB2
IZD2 VSEN Zero
AQR/
+ AQR_TH[2:0] To TONGEN IZDx Current ZCDx
ANTIOVS
ISEN3P + Gm 0.6V/3.2V Detection
- ANTIOVS_TH[1:0]
ISEN3N - IIMON3
ICB3
IZD3 VSEN OVP/
IOCx UVP/ To Protection Logic Current
ICBx VCBx
IMON OCP Balance
ISEN4P + Gm
ISEN4N - IIMON4
ICB4
IZD4
IMON
VREF IMONAVG
PER CSGM Filter
IMON
VIN/VSYS
VIDA Control VIDA
DAC
ERROR
AMP PWM
RGNDA Offset Loop logic control
+ CMP
Cancellation +
FBA -
+ - TON PWMA1
COMPA ZCDAx GEN/
Driver PWMA2
ISENA1P + Gm VCBAx
Interface
ISENA1N - IIMONA1 kTON_A[2:0]
+
ICBA1
IZDA1 -
VREF
Ai_A[1:0] Ring-back
ISENA2P + Gm Control RAMP
ISENA2N - IIMONA2
ANTIOVS_TH_A[1:0]
ICBA2
AQR/
IZDA2 AQR_TH_A[2:0] To TONGEN
ANTIOVS Zero
IMON VSENA
IMONA IMONAAVG IZDAx Current ZCDAx
PER CSGM Filter Detection
VSENA OVP/
IOCAx UVP/ To Protection Logic
IMONA OCP Current
ICBAx VCBAx
ISENP_AUX + Gm Balance
ISENN_AUX -
IMON
IMON_AUX IMON_AUXAVG
PER CSGM Filter
+
VREF_SPS 1.3V
-
5
Operation
the sensed voltage that is inverted and amplified signal
G-NAVPTM Control Mode
of output voltage. While current loading is increasing,
The RT3624BE adopts G-NAVPTM (Green Native AVP)
referring to Figure 1, COMP basic G-NAVPTM behavior
which is Richtek’s proprietary topology. It is derived
waveforms. The COMP rises due to output voltage
from current mode constant on-time control with finite
droop. Then rising COMP forces PWM turn on earlier
DC gain of error amplifier and DC offset cancellation.
and closely. While inductor current reaches loading
The topology can achieve easy load-line design and
current, COMP enters another steady state of higher
provide high DC accuracy and fast transient response.
voltage and the corresponding output voltage is in the
When sensed current signal reaches sensed voltage
steady state of lower voltage. The load-line, output
signal, the RT3624BE generates a PWM pulse to
voltage drooping by an amount which is proportional to
achieve loop modulation. Figure 1 shows the basic
loading current, is achieved.
G-NAVPTM behavior waveforms. The COMP signal is
Steady State Load Transient
Loading Current ΔIcc
VOUT
VID
ΔIcc x RLL
Sensed Current Signal
COMP
PWM
Figure 1. G-NAVPTM Behavior Waveform
SET4, TSEN, TSENA, PSYS, IMONAVG, IMONAAVG

SVID Interface/Control Logic/Configuration
and IMON_AUXAVG. The ADC converts these analog
Registers
signals to digital codes for reporting or function
SVID Interface receives or transmits SVID signal with
settings.
CPU. Control Logic executes command (Read/Write
registers, setVID, setPS) and sends related signals to UVLO
control VR. Configuration Registers include function The UVLO detects the VCC voltage. As VCC exceeds
setting registers and CPU required registers. threshold, controller issues POR = high and waits
VRON. After both POR and VRON are ready, then
IMON Filter
controller is enabled.
IMON Filter is used to average current signal by an
analog low-pass filter. It outputs IMONAVG to the MUX Loop Control/Protection Logic
of ADC for current reporting. It controls power-on/off sequence, protections, power
state transition, and PWM sequence.
MUX and ADC
The MUX supports the inputs of SET1, SET2, SET3,
6
DAC Current Balance
The DAC generates a reference VID voltage according Per-phase current sense signal is compared with
to the VID code sent by Control Logic. According to sensed average current. The comparison result will
setVID command, Control Logic dynamically changes adjust each phase PWM width to optimize current and
VID voltage to target with required slew rate. thermal balance.
ERROR AMP Zero Current Detection

The ERROR AMP inverts and amplifies the difference Detect whether each phase current crosses zero
between output voltage and VID with externally setting current. The result is used for DEM power saving and
finite DC gain. The output signal is COMP for PWM overshoot reduction (Anti-overshoot Function).
trigger.
AQR/ANTIOVS
PER CSGM The AQR is a new generation of quick response
The PER CSGM senses per-phase inductor current. mechanism (Adaptive Quick Response, AQR) which
The outputs are used for loop response, Current detects loading rising edge and allows all PWM to turn
Balance, Zero Current Detection, current reporting and on. The PWM pulse width triggered by AQR is adaptive
over-current protection. to loading level. The AQR trigger level can be set by
PINSETTING. ANTIOVS can help overshoot reduction
SUM CSGM
which detects loading falling edge and forces all PWM
The SUM CSGM senses total inductor current with in tri-state until the zero current is detected.
RIMON gain adjustment. SUM CSGM output current
ratio can also be set by PIN-SETTING(Ai[1:0]). It helps OCP
wider application range of DCR and load line. SUM The RT3624BE has two over-current protection
CSGM output is used for PWM trigger. mechanisms, sum OCP and OC limit.
RAMP OVP
The RAMP helps loop stability and transient response. The over-voltage protection threshold is linked to VID,
please refer to classification table and waveform in
PWM CMP
Table 17, Figure 23 and Figure 24.
The PWM comparator compares COMP signal and
sum current signal based on RAMP to trigger PWM. UVP
When the output voltage is lower than VID-650mV with
Offset Cancellation
3µs filter time, UVP will be triggered and all PWM will
The offset cancellation is based on VID, COMP voltage be in tri-state to turn off high-side power MOSFETs.
and current signal from SUM CSGM to control output
voltage accuracy.
7
Absolute Maximum Ratings (Note 1)
 VIN/VSYS to GND ---------------------------------------------------------------------------------------------------- −0.3V to 28V
 VCC to GND - ---------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
 RGND to GND --------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
 Other Pins --------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
 Power Dissipation, PD @ TA = 25°C
WQFN-52L 6x6 -------------------------------------------------------------------------------------------------------- 3.77W
 Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA -------------------------------------------------------------------------------------------------- 26.5°C/W
WQFN-52L 6x6, θJC -------------------------------------------------------------------------------------------------- 6.5°C/
 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260°C
 Junction Temperature ------------------------------------------------------------------------------------------------ 150°C
 Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

 VIN/VSYS to GND ---------------------------------------------------------------------------------------------------- 4.5V to 24V
 Supply Input Voltage, VCC ----------------------------------------------------------------------------------------- 4.5V to 5.5V
 Junction Temperature Range -------------------------------------------------------------------------------------- −10°C to 105°C
Electrical Characteristics
(VCC = 5V, typical values are referenced to TJ = 25°C, Min and Max values are referenced to TJ from −10°C to 105°C, unless
other noted)
Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input
Supply Voltage VCC 4.5 5 5.5 V
Supply Current IVCC VRON = H, not switching -- 14 -- mA
Supply Current at PS4 IVCC_PS4 VRON = H, not switching -- 85 -- µA
Shutdown Current ISHDN VRON = L -- -- 15 µA
EA Amplifier
DC Gain ADC RL = 47kΩ 70 -- -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 10 -- MHz
CLOAD = 10pF (Gain = −4, Rf
Slew Rate SREA -- 5 -- V/µs
= 47kΩ, VOUT = 0.5V to 3V)
Output Voltage Range VCOMP RL = 47kΩ 0.3 -- 3.6 V
Maximum Source/Sink
IOUTEA VCOMP = 2V -- 5 -- mA
Current
Current Sensing Amplifier (CORE/AXG/AUX)
Impedance at Positive Input RISENxP 1 -- -- MΩ
8
Differential voltage range of
DCR sense. (VCSIN=
CS Input Voltage VCSIN −10 -- 80 mV
Inductor current x
DCR x DCR divider)
Internal current mirror gain of
Current Sense Gain Error AMIRROR per phase current sense 0.97 1 1.03 A/A
IIMON / ICS,PERx
TON Setting
VIN = 19V, VID = 0.9V,

On-Time Setting tON -- 93 -- ns
kTON = 1.36
VID = 1V under PS1
Minimum Off-Time tOFF -- 130 300 ns
condition
Minimum On-Time tON(MIN) -- 50 -- ns
Protections
VUVLO,rise Rising edge 4.1 -- 4.45 V
Under-Voltage Lockout
VUVLO Falling edge 3.9 -- 4.2 V
Threshold
∆VUVLO Rising edge hysteresis 100 170 250 mV
Respect to VID voltage, VID VID VID
Over-Voltage Protection mV
VOV VID >1V +320 +350 +380
Threshold
VID ≤1V 1.3 1.35 1.4 V
Under-Voltage Protection
VUV Respect to VID voltage −680 −650 −620 mV
Threshold
VRON and VR_READY
VRON Logic-High VIH 0.7 -- --

Threshold Logic-Low VIL -- -- 0.3 V
Leakage Current of VRON −1 -- 1 µA
VR_READY Pull Low Voltage VVR_READY IVR_READY = 10mA -- -- 0.13 V
Serial VID and VR_HOT
VCLK, VDIO Logic-High VIH 0.65 -- --

V
Input Voltage
Logic-Low VIL -- -- 0.45
Leakage Current of VCLK and
ILEAK_IN −1 -- 1 µA
VDIO
VVDIO IVDIO = 10mA -- -- 0.13
Pull Low Voltage VALERT IALERT = 10mA -- -- 0.13 V
VVR_HOT IVR_HOT = 10mA -- -- 0.13
Leakage Current of ALERT ,
ILEAK_OUT −1 -- 1 µA
VR_HOT
ANS_EN
ANS_EN VCC −
Logic-High VIH -- -- V
Input 0.5
Voltage Logic-Low VIL -- -- 1 V
9
VREF
VREF Voltage VVREF Normal operation 0.59 0.6 0.61 V
VREF SPS Voltage VVREF_SPS Normal operation 1.2 1.3 1.4 V
ADC
VIMON − VREF = 0.8V @
ICCMAX >=80A
CORE dVIMON_ICCMAX -- 255 -- Decimal
ICCMAX >=40A
ICCMAX <40A
Digital IMON VIMONA − VREF = 0.4V @
Set ICCMAX >=40A
AXG dVIMONA_ICCMAX -- 255 -- Decimal
VIMONA − VREF = 0.2V @
ICCMAX <40A
dVIMON_AUX_IC
AUX VIMON_AUX-VREF=1.6V -- 255 -- Decimal
CMAX
PSYS Maximum Input Voltage PSYS VPSYS = 1.6V -- 255 -- Decimal
VSYS Maximum Input Voltage VSYS VIN/VSYS=24V -- 255 -- Decimal
Average Period of IMON tIMON -- 150 -- µs
Average Period of TSEN tTSEN -- 600 -- µs
TSEN Voltage Threshold to

Within the range, VR_HOT
Pull Low VR_HOT VTSEN_ VR_HOT_L 1.105 1.112 1.119 V
= L.
(Asserts VR_HOT )
TSEN Voltage Threshold to
Within the range, VR_HOT
Pull High VR_HOT VTSEN_ VR_HOT_H 1.147 1.154 1.161 V
=H
(De-Asserts VR_HOT )
TSEN Rises to Pull Low
VTSEN_Status_H ALERT =Low 1.147 1.154 1.161 V
ALERT
TSEN Down to Pull Low
VTSEN_Status_L ALERT =Low 1.196 1.201 1.208 V
ALERT
ITSEN
TSEN Source Current ITSEN VTSEN = 1.6V 79.2 80 80.8 µA
Power DoCORE Disable VCC
VPSYS -- -- V
Voltage − 0.5
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high
effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured
at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
10
Typical Application Circuit
VIN
5V
C17 C18
VCC BOOT
RT3624BE C16 Q1
1µF 0.1µF
UGATE
29 L1 VAUX_OUT
PSYS PHASE
Q2
R36 R37 C19 LOAD
C1 R1 EN LGATE
Optional EN RT6543
0.1µF
R38 R39
38
ISENP_AUX
R2 39 RNTC5
5V 50 VCC ISENN_AUX
C20
2.2 Ω C2 0.1µF
4.7µF
R3 VIN
24 SET1
R4 5V R40 C22
+
25 C23 C24
SET2 VCC BOOT
VREF C21 2.2Ω 0.1µF Q3
R5
26 SET3 1µF PGND UGATE
Optional L2
R6 27 44 PHASE
PWMA1 PWM Q4 R41
SET4 R42 R43 C26
DRVEN EN LGATE
RT9610C C25
R7 R8 R9 R10 0.1µF
R44 VSSAXG_SENSE
ISENA1P 36 VCCAXG_SENSE
37 R45 Optional
ISENA1N R53
680 Ω C27
R52 100Ω
R11 52 0.1µF
VIN VIN/VSYS 100Ω
VIN Optional
2.2 Ω C3 VAXG_OUT
0.47µF 5V R46 C29
+
C30 C31 C35 C37
C36
+
20 VCC BOOT LOAD
VREF VREF C28 2.2Ω 0.1µF Q5
1µF PGND UGATE
R13 Optional L3
R12 R15 PHASE
3.9Ω R14 RNTC1 19 IMON PWMA2 43 PWM Q6 R47
C33
LGATE R48 R49
DRVEN EN
R16 RT9610C C32
R18 0.1µF
C4 21
0.47µF R17 RNTC2 IMONA R50
ISENA2P 35
R19 R20 R51 Optional
28
IMON_AUX ISENA2N 34
680 Ω C34
0.1µF
VCCST 3.3V
VIN
R21 R22 R23 R24 R25 5V R54 C39

+
C40 C41
NC 100Ω 45.3 Ω 75 Ω 10k VCC BOOT
C38 2.2Ω 0.1µF Q7
14
VR_READY 1µF PGND UGATE
18 VR_HOT Optional L4
PHASE
15 VCLK PWM1 45 PWM Q8 R55
C43
16 VDIO LGATE R56 R57
To CPU
DRVEN EN
17 ALERT RT9610C C42
0.1µF
51 R58
Enable VRON 8
ISEN1P
11 VSEN R59 Optional
ISEN1N 7
C5 C6 C44
680 Ω
0.1µF
R26 R27 VIN
VCC_SENSE Optional 10 COMP
C7 9 5V R60 C46
+
FB C47 C48
C8 VCC BOOT
Optional C45 2.2Ω 0.1µF Q9
Optional 12 RGND 1µF PGND UGATE
VSS_SENSE Optional L5
C9 PHASE
PWM2 46 PWM Q10 R61
C50
LGATE R62 R63
DRVEN EN
31 RT9610C C49
VSENA 0.1µF
C10 C11
R64 VSS_SENSE
ISEN2P 5
R28 R29 VCC_SENSE
Optional 32 R65 Optional
VCCAXG_SENSE COMPA ISEN2N 6
C12 33 680 Ω C51 R79
FBA R78
C13 0.1µF 100Ω
Optional VIN 100Ω
Optional 30 Optional
VSSAXG_SENSE RGNDA VCORE_OUT
C14 5V R66 C53
+
C54 C55
VCC C66 C67 C68
+
BOOT
C52 2.2Ω 0.1µF Q11 LOAD
1µF PGND UGATE
Optional L6
R30 R32
22 TSEN PHASE
VREF
RNTC3 PWM3 48 PWM Q12 R67
C57
R31 LGATE R68 R69
DRVEN EN
RT9610C C56
0.1µF
R33 R35 R70
23 TSENA ISEN3P 1
VREF
RNTC4 R71
R34 2 Optional
ISEN3N
680 Ω C58
0.1µF
VIN
5V 49
ANS_EN 5V R72 C60
+
C61 C62
0V VCC BOOT
C59 2.2Ω 0.1µF Q13
1µF PGND UGATE
41 Optional L7
DRVEN DRVEN PHASE
PWM4 47 PWM Q14 R73
C64
LGATE R74 R75
DRVEN EN
42 RT9610C C63
DRVEN_F 0.1µF
R76
ISEN4P 4
40 R77
DBLR_PS 3 Optional
ISEN4N
680 Ω C65
13 0.1µF
VREF_SPS 53 (Exposed Pad)
C15 GND
0.22µF
11
Application Information
The RT3624BE includes two voltage rails: a 4/3/2/1 MOSFET off. When VCC > 4.45, RT3624BE issues
phase synchronous buck controller, the CORE VR, and POR=high and waits for VRON signal. After POR=high
a 2/1 phase synchronous buck controller, the AXG VR, and VRON > 0.7V, controller powers on (Chip Enable =
designed to meet Intel IMVP9.1 compatible CPUs H) and starts VR internal settings, which include
specification with a serial SVID control interface. The internal circuit offset correction and function settings
controller uses an ADC to implement all kinds of (PIN-SETTING). Users can set multi-functions through
settings to save total pin number for easy use and SETx, TSEN and TSENA pins. Figure 2 shows the
increasing PCB space utilization. The RT3624BE is typical timing of controller power-on. The pull-high
used in desktop computers or notebook computers. power of VRON pin is recommended as 1.05V, the
Power-ON Sequence same power as SVID interface. That can ensure SVID
In order to confirm sufficient power supply for proper power is ready while VRON = H. Driver power (PVCC)
operation, the VR triggers UVLO if VCC pin drops is strongly suggested to be ready after VCC. This can
below 4.2V (max). UVLO protection shuts down prevent current flow back to VCC from PVCC through
controller and forces high-side MOSFET and low-side PWMx pin or DRVEN pin.
VCC
PVCC
VRON
Chip Enable
(VRON=H and VCC>4.45V)
VR Initial Setting Mode Internal Setting
VR_READY
VSEN
Figure 2. Typical Timing of Controller Power-ON.
Maximum Active phases Number Setting ISEN4N to VCC programs a 3-phase operation, while
The number of active phases is determined by ISENxN pulling ISEN3N to VCC programs a 2-phase operation.
voltages. The detection is only active and latched at The unused ISENxP pins are recommended to connect
Chip Enable rising edge (VRON = H and VCC > 4.45V). to VCC and the unused PWM pins can be floating.
While voltage at ISENxN > (VCC − 0.5V), maximum Figure 3 is a 3-phase operation example.
active phase number is (x-1). For example, pulling
12
VIN
RT3624BE 5V R66 C53
+
C54 C55
VCC BOOT
C52 2.2Ω 0.1µF Q11
1µF PGND UGATE
Optional L6
PHASE
PWM3 48 PWM Q12 R67
C57
LGATE R68 R69
DRVEN EN
RT9610C C56
0.1µF
R70
ISEN3P 1
R2 R71 Optional
50 2
5V VCC ISEN3N
2.2 Ω 680 Ω C58
C2
4.7µF PWM4 47 0.1µF
ISEN4P 4 R77
3
ISEN4N 10k
Figure 3. 3-Phases Operation Setting
platform setting and BOM optimization. These

Rail Disable
parameters can be set through SETx and TSEN pins.
Pulling ISEN1N to VCC programs CORE rail disable. The RT3624BE adopts two-step PIN-SETTING
The unused ISENxP pins are recommended to connect mechanism to maximize IC pin utilization. Figure 4
to VCC and the unused PWMx pins can be floating. illustrates this operating mechanism for SETx.
Pulling ISENA1N to VCC programs AXG rail disable.
The unused ISENAxP pins are recommended to
The Vdivider and Vcurrent can be represented as
connect to VCC and the unused PWMAx pins can be
follows:
floating. Pulling the PSYS pin to (VCC – 0.5V)
R2
programs input power domain rail disable. RT3624BE Vdivider = × 3.2V
R1 + R2
will reject any commands to the input power domain rail.
R2 R1× R2
The unused ISENP_AUX pin and ISENN_AUX pin are Vcurrent = × 3.2V + 80uA ×
R1 + R2 R1 + R2
recommended to connect to VCC.
80μA
Acoustic Noise Suppression VREF =

3.2V
The RT3624BE supports acoustic noise suppression
function for reducing acoustic noise induced by SETx R1
piezoelectric effect from MLCC. As output voltage Divider-Register
ADC SETx
transition, especially in dynamic VID, the vibrating SETx
IXR-Register R2
MLCC produces acoustic noise if the vibrating
frequency falls into audible band and the noise level is
related to the output voltage transition amplitude ∆V. Figure 4. Operating Mechanism for SETx
Therefore, the RT3624BE adopts acoustic noise
suppression function which is enabled by pulling ANS
Divider-Register and IXR-Register set specified
pin to VCC to reduce ∆V when SetVID down and
functions. For example, Divider-Register of SET1 sets
SetVID Decay down in DEM mode.
VBOOT and ICCMAX of CORE rail; IXR-Register of
PIN-SETTING Mechanism SET1 sets AXG rail ICCMAX. All setting functions are
The RT3624BE provides multiple parameters for summarized in Table 1.
13
Table 1. Summary of Pin Setting Functions
Function Setting Symbol Description
VBOOT[4]=0, 0V
Divider Register [4] Setting VBOOT of CORE rail VBOOT[4]
VBOOT[4]=1, non-zero
SET1 According to Platform, set CORE VR

Divider Register[3:0] CORE VR ICCMAX ICCMAX[3:0]
corrsponding ICCMAX.
According to Platform, set AXG VR
IXR Register[4:1] AXG VR ICCMAX ICCMAX_A[4:1]
VBOOT_A[4]=0, 0V
Divider Register[4] Setting VBOOT olf AXG rail VBOOT_A[4]
VBOOT_A[4]=1, non-zero
VIDT[3]=0, VID1(0V~1.52V)
Divider Register[3] Selectable VID table VIDT[3]
VIDT[3]=1, VID2(0V~2.74V)
CORE VR TON width setting According to required frequency, select
SET2 Divider Register[2:0] kTON[2:0]
(Switching frequency) adaptive kTON parameter
According to Platform, set AUX VR
IXR Register[4:2] AUX VR ICCMAX ICCMAX_AUX[4:2]
Enable zero load-line for 0LL[1]=0: Disable zero load line
IXR Register[1] 0LL[1]
CORE and AXG VR 0LL[1]=1: Enable zero load line
To improve undershoot by applying a
CORE VR undershoot
Divider Register[4:3] UDS[4:3] positive offset at loading edge. Set
suppression
trigger level.
DVID fast_SR[2][0] = 00, 1/2*Fast_P
Divider Register[2] DVID Fast slew rate DVID fast_SR[2]
DVID fast_SR[2][0] = 10, Fast_P
DVID fast_SR[2][0 ]= 11, Fast_S
DVID_LIFT[1] = 0: 10uA
CORE VR DVID
Divider Register[1] DVID_LIFT[1] DVID_LIFT[1] = 1: 20uA
voltage-compensation level
current source sink from FB pin
SET3 DVID fast_SR[2][0] = 01, 3/4*Fast_P
Divider Register[0] DVID Fast slew rate DVID fast_SR[0]
DVID fast_SR[2][0] = 10, Fast_P
DVID fast_SR[2][0 ]= 11, Fast_S
To improve undershoot by applying a
AXG VR undershoot
IXR Register[4:3] UDS_A[4:3] positive offset at loading edge. Set
suppression
trigger level.
VR_HOT assertion during VR_HOT _DVID[2] = 0,Enable
IXR Register[2] VR_HOT _DVID[2]
DVID current limit VR_HOT _DVID[2] = 1,Disable
DVID_LIFT_A[1] = 0: 10uA
AXG VR DVID
IXR Register[1] DVID_LIFT_A[1] DVID_LIFT_A[1] = 1: 20uA
voltage-compesation level
current source sink from FB pin
DBLR[4:3] = 00 : Enable, Phase=8
DBLR[4:3] = 01 : Disable, Phase=1~4,
Divider Register[4:3] CORE VR Phase Extension DBLR[4:3]
DBLR[4:3] = 10 : Enable, Phase=5,
DBLR[4:3] = 11 : Enable, Phase=6,
AXG VR TON width setting According to required frequency, select
SET4 Divider Register[2:0] kTON_A[2:0]
(switching frequency) adaptive kTON_A parameter
CORE VR Anti-overshoot ANTIOVS for reduction of overshoot at
IXR Register[4:3] ANTIOVS_TH[4:3]
trigger level loading falling edge. Set trigger level.
AXG VR Anti-overshoot ANTIOVS for reduction of overshoot at
IXR Register[2:1] ANTIOVS_TH_A[2:1]
trigger level loading falling edge. Set trigger level.
14
Function Setting Symbol Description
Divider Register[4:3] CORE VR Current Gain Ai[4:3] Current gain setting
TSEN CORE VR Adaptive Quick AQR for loop response speed-up of
Divider Register[2:1] AQR_TH[2:1]
Response(AQR) trigger level loading rising edge. Set trigger level.
Divider Register[4:3] AXG VR Current Gain Ai_A[4:3] Current gain setting
TSENA AXG VR Adaptive Quick AQR for loop response speed-up of
Divider Register[2:1] AQR_TH_A[2:1]
Response(AQR) trigger level loading rising edge. Set trigger level.
Referring to PIN-SETTING tables, Table 2 to 11, users Richtek provides a Microsoft Excel-based design tool to
can search corresponding Vdivider or VIXR according to calculate the desired PIN-SETTING resisters.
the desired function setting combinations. Then SETx TSEN and TSENA pins also have function settings
external resistors can be calculated as follows: except for thermal monitoring function. They only utilize
divider part of PIN-SETTING mechanism. The
3.2V × VIXR
R1 =
80µ A × Vdivider functions of TSEN and TSENA include current gain and
quick response triggle level. The detailed operation is
R1× Vdivider
R2 = described in Thermal Monitoring and Indicator section.
3.2V − Vdivider
15
Table 2. SET1 Pin Setting for VBOOT and ICCMAX
Vdivider_SET1 ICCMAX(A)
VBOOT
(mV) 8 phase 6 phase 5 Phase 4 Phase 3 Phase 2 Phase 1 Phase
25 232 170 134 85 60 35 10
75 238 176 140 90 64 38 12
125 244 182 146 95 68 41 14
175 250 188 152 100 72 44 16
225 256 194 158 105 76 47 18
275 262 200 164 110 80 50 20
325 268 206 170 115 84 53 22
375 274 212 176 120 88 56 24
0V
425 280 218 182 125 92 59 26
475 286 224 188 130 96 62 28
525 292 230 194 135 100 65 30
575 298 236 200 140 104 68 32
625 304 242 206 145 108 71 34
675 310 248 212 150 112 74 36
725 316 254 218 155 116 77 38
775 322 260 224 160 120 80 40
825 232 170 134 85 60 35 10
875 238 176 140 90 64 38 12
925 244 182 146 95 68 41 14
975 250 188 152 100 72 44 16
1025 256 194 158 105 76 47 18
1075 262 200 164 110 80 50 20
1125 268 206 170 115 84 53 22
1175 274 212 176 120 88 56 24
non-zero
1225 280 218 182 125 92 59 26
1275 286 224 188 130 96 62 28
1325 292 230 194 135 100 65 30
1375 298 236 200 140 104 68 32
1425 304 242 206 145 108 71 34
1475 310 248 212 150 112 74 36
1525 316 254 218 155 116 77 38
1575 322 260 224 160 120 80 40
16
Table 3. SET1 Pin Setting for ICCMAX_A
ICCMAX_A (A)
VIXR_SET1 (mV)
2 Phase 1 Phase
50 35 10
150 38 12
250 41 14
350 44 16
450 47 18
550 50 20
650 53 22
750 56 24
850 59 26
950 62 28
1050 65 30
1150 68 32
1250 71 34
1350 74 36
1450 77 38
1550 80 40
17
Table 4. SET2 Pin Setting for VBOOT_A, VIDT and kTON
Vdivider_SET2 (mV) VBOOT_A VIDT kTON

25 0.64
75 0.82
125 1
175 1.18
VID1
225 1.36
275 1.55
325 1.73
375 2.27
0V
425 0.64
475 0.82
525 1
575 1.18
VID2
625 1.36
675 1.55
725 1.73
775 2.27
825 0.64
875 0.82
925 1
975 1.18
VID1
1025 1.36
1075 1.55
1125 1.73
1175 2.27
non-zero
1225 0.64
1275 0.82
1325 1
1375 1.18
VID2
1425 1.36
1475 1.55
1525 1.73
1575 2.27
18
Table 5. SET2 Pin Setting for ICCMAX_AUX and 0LL
VIXR_SET2 (mV) ICCMAX_AUX(A) 0LL
50 Disable
10
150 Enable
250 Disable
15
350 Enable
450 Disable
20
550 Enable
650 Disable
25
750 Enable
850 Disable
30
950 Enable
1050 Disable
35
1150 Enable
1250 Disable
40
1350 Enable
1450 Disable
55
1550 Enable
19
Table 6. SET3 Pin Setting for UDS, DVID_LIFT and DVID fast_SR
UDS
Vdivider_SET3 (mV) DVID_LIFT DVID fast_SR
PS0 PS1
25 1/2*Fast_P
10uA
75 3/4*Fast_P
125 1/2*Fast_P
20uA
175 3/4*Fast_P
Disable Disable
225 Fast_P
10uA
275 Fast_S
325 Fast_P
20uA
375 Fast_S
425 1/2*Fast_P
10uA
475 3/4*Fast_P
525 1/2*Fast_P
20uA
575 3/4*Fast_P
200 125
625 Fast_P
10uA
675 Fast_S
725 Fast_P
20uA
775 Fast_S
825 1/2*Fast_P
10uA
875 3/4*Fast_P
925 1/2*Fast_P
20uA
975 3/4*Fast_P
200 175
1025 Fast_P
10uA
1075 Fast_S
1125 Fast_P
20uA
1175 Fast_S
1225 1/2*Fast_P
10uA
1275 3/4*Fast_P
1325 1/2*Fast_P
20uA
1375 3/4*Fast_P
250 150
1425 Fast_P
10uA
1475 Fast_S
1525 Fast_P
20uA
1575 Fast_S
20
Table 7. SET3 Pin Setting for UDS_A, VR_HOT _DVID and DVID_LIFT_ A
VIXR_SET3 UDS_A
VR_HOT _DVID DVID_LIFT_A
(mV) PS0 PS1
50 10uA
Enable
150 20uA
Disable Disable
250 10uA
Disable
350 20uA
450 10uA
Enable
550 20uA
200 125
650 10uA
Disable
750 20uA
850 10uA
Enable
950 20uA
200 175
1050 10uA
Disable
1150 20uA
1250 10uA
Enable
1350 20uA
250 150
1450 10uA
Disable
1550 20uA
21
Table 8. SET4 Pin Setting for DBLR and kTON_A
Vdivider_SET4 (mV) DBLR kTON_A
25 0.64
75 0.82
125 1
175 Eable DBLR 1.18
225 8phase 1.36
275 1.55
325 1.73
375 2.27
425 0.64
475 0.82
525 1
575 1.18
Disable DBLR
625 1.36
675 1.55
725 1.73
775 2.27
825 0.64
875 0.82
925 1
975 Enable DBLR 1.18
1025 5 phase 1.36
1075 1.55
1125 1.73
1175 2.27
1225 0.64
1275 0.82
1325 1
1375 Enable DBLR 1.18
1425 6 phase 1.36
1475 1.55
1525 1.73
1575 2.27
22
Table 9. SET4 Pin Setting for ANTIOVS_TH and ANTIOVS_TH_A
VIXR_SET4 (mV) ANTIOVS_TH ANTIOVS_TH_A
50 90mV
150 150mV
90mV
250 210mV
350 Disable
450 90mV
550 150mV
150mV
650 210mV
750 Disable
850 90mV
950 150mV
210mV
1050 210mV
1150 Disable
1250 90mV
1350 150mV
Disable
1450 210mV
1550 Disable
23
Table 10. TSEN Pin Setting for Ai and AQR_TH
VTSEN (mV) Ai AQR_TH

50 720
150 880
250 1040
350 1200
0.25
450 1360
550 1520
650 1680
750 Disable
850 720
950 880
1050 1040
1150 1200
0.5
1250 1360
1350 1520
1450 1680
1550 Disable
1650 720
1750 880
1850 1040
1950 1200
0.75
2050 1360
2150 1520
2250 1680
2350 Disable
2450 720
2550 880
2650 1040
2750 1200
1
2850 1360
2950 1520
3050 1680
3150 Disable
24
Table 11. TSENA Pin Setting for Ai_A and AQR_TH_A
VTSENA (mV) Ai_A AQR_TH_A

50 720
150 880
250 1040
350 1200
0.25
450 1360
550 1520
650 1680
750 Disable
850 720
950 880
1050 1040
1150 1200
0.5
1250 1360
1350 1520
1450 1680
1550 Disable
1650 720
1750 880
1850 1040
1950 1200
0.75
2050 1360
2150 1520
2250 1680
2350 Disable
2450 720
2550 880
2650 1040
2750 1200
1
2850 1360
2950 1520
3050 1680
3150 Disable
25
Thermal Monitoring and Indicator 80μA
TSEN pin processes two functions of PIN-SETTING

VREF =
(function setting) and thermal monitoring. After power 3.2V
R3
on, TSEN has three operation modes: PIN-SETTING, PIN-SETTING
Register RNTC R1
Pre-thermal Sense and Thermal Sense Mode. The Pre-Thermal TSEN
ADC
corresponding function blocks of the three modes are Register
R2
shown in Figure 5. In PIN-SETTING Mode, TSEN pin Thermal Register
VDDIO
voltage = 3.2V x R2 / (R1+R2) with VREF = 3.2V and is
coded by ADC and stored in PIN-SETTING register. In -
VR_HOT#
Pre-Thermal Sense Mode, TSEN pin voltage = 0.6V x +
0.6V
Thermal Sense Mode
R2 / (R1+R2) with VREF = 0.6V and is coded and
stored in Pre-Thermal Register. This part helps
Thermal Sense Mode calculation. In Thermal Sense
Mode, TSEN pin voltage = 0.6V x R2 / (R1+R2) + 80uA Figure 5. Multi-Function Pin Setting Mechanism for
x [(R1//R2)+R3] with VREF = 0.6V and is coded. The TSEN
result will subtract Pre-Thermal Register code and
stored in Thermal Register (The corresponding TSEN System Input Power Monitoring (PSYS)
voltage = 80µA x [(R1//R2)+R3] that’s defined as The RT3624BE provides PSYS function to monitor total
Thermal Voltage. R3 is the NTC thermistor network to platform system power and report to the CPU via SVID
sense temperature.) NTC thermistor is recommended interface. The PSYS function can be illustrated as in
to be placed near the MOSFET, the hottest area in the Figure 6. PSYS meter measures system input current
PCB. Higher temperature causes smaller R3 and lower and outputs a proportional current signal IPSYS. RPSYS
TSEN. According to NTC thermistor temperature curve, is designed for the PSYS voltage = 1.6V with maximum
design Thermal Voltage v.s Temperature with proper IPSYS for 100% system input power. 1.6V is a
R3 network to meet Intel temperature zone. 100°C full-scale analog signal for FFh digitized code.
Thermal Voltage = 80µA x [(R1//R2)+R3(100°C)] =
Input Power
PSYS ʺMeterʺ
1.105V must be required. Controller processes the Source
TSEN pin voltage to report temperature zone register.
Analog Current Signal
While the TSEN pin voltage is less than 1.105V, the IPSYS (Indicates system total
RT3624BE power)
VR_HOT will be pulled low to indicate thermal alert.
CPU SVID PSYS VPSYS
The signal is an open-drain signal. Thermal Register
RPSYS
data is updated every 75µs and average interval is
600µs. The resistance accuracy of TSEN network is
Figure 6. PSYS Function Block Diagram
recommended to be less than 1% error.
System Input Voltage Monitoring (VSYS)

The RT3624BE provides optional VSYS function to
monitor system input voltage. The threshold can be set
through SVID interface and FFh digitized code
indicates for 24V input voltage (24V/255 pre code).If
input voltage is lower than critical threshold, controller
will assert VR_HOT .
26
Zero Load-line controller will temporarily change VID target to
The RT3624BE also can support enable zero load-line short-term voltage target. Short-term voltage target is
function. When zero load-line function is enabled, the related to transient loading current ∆ICC and can be
output voltage is determined only by VID and does not represented as the following:
vary with the loading current like load-line system Short_Term_Voltage_Target=VID-∆ICC ×RLL
behavior. The RT3624BE adopts AC-droop to
The setting method of R LL is the same as loadline
effectively suppress load transient ring back and
system. The short-term voltage target reverts to VID
control overshoot for zero load-line application. Figure
target slowly after a period of time. The short-term
7 shows the condition without AC-droop control. The
voltage target can help inductor current not to exceed
output voltage without AC-droop control has extra ring
loading current too much and then the ring back ∆V2
back ∆V2 due to C area charge. Figure 8 shows the
can be suppressed. The overshoot amplitude is
condition with AC-droop control. While loading occurs,
reduced to only ∆V3.
B C
Inductor
A current

D
ΔV3
ΔV2
Output Voltage
VID Target
ΔV1
Figure 7. Zero Load-line without AC-droop Control
27
Inductor
current
Inductor
A current
D
Load
Output Voltage ΔV3
ΔV1 VID Target
Short-term voltage target
Figure 8. Zero Load-line with AC-droop Control
VCSIN ILx ×DCR

Per Phase Current Sense ICS,PERx = =
680Ω 680Ω
To achieve higher efficiency, the RT3624BE adopts
inductor DCR current sensing to get each phase
current signal, as illustrated in Figure 9. An external RX2 is optional for preventing VCSIN from exceeding
low-pass filter RX1 and CX reconstruct the current current sense amplifier input range. The time constant
L
signal. The low-pass filter time constant RX1 ×CX of (RX1//RX2) x CX should match X .
DCR
L
should match time constant X of Inductance and VCSIN ILx ×DCR RX2
DCR
DCR. It’s fine to fine tune RX1 and CX for transient ICS,PERx = = ×
680Ω 680Ω RX1 +RX2
performance and current reporting. If RC network time
L
constant matches inductor time constant X , an ideal The current signal ICS,PERx is mirrored for loadline
DCR
load transient waveform can be designed. If RC control/current reporting, current balance and zero
network time constant is larger than inductor time current. The mirrored current to IMON pin is one time of
L
constant X , VCORE waveform has a sluggish droop ICS,PER,
DCR
during load transient. If RC network is smaller than
L (IIMON =AMIRROR ×ICS,PERx , AMIRROR =1)
inductor time constant X , VCORE waveform sags to
DCR
create an undershooting to fail the specification and The current sense lines must be routed as differential
mis-trigger over-current protections (sum OCP). Figure pair from the inductor to the controller on the same
11 shows the output waveforms according to the RC layer.
network time constant. The AUX current sense is demonstrated in Figure 10.
The RX1 is highly recommended as two 0603 size In this design, the RCS is equal to 1kΩ and the
resistors in series to enhance the Iout reporting mirror-gain is 1.25 time of ICS,PER.
accuracy. CX is suggested to be 0.1µF X7R/0603 for (IIMON =AMIRROR ×ICS,PERx , AMIRROR =1.25)
low de-rating value of high frequency.
28
ILx VCORE
LX DCR
VOUT
Lx ∆IOUT x RLL
R x × Cx =
RX1 CX DCR x
+ VCSIN -
RX2
ISENxP ∆IOUT
+ Option
Gm VIMON
- ISENxN RCSx=680ohm
IIMONx Ideal load transient waveform
ICBx ICS,PERx
IZDx
IOCx
Figure 9. Inductor DCR Current Sensing Method for

VOUT Lx
R x × Cx < ∆IOUT x RLL
CORE/AXG DCR x
ILx VAUX ∆IOUT

LX VIMON
DCR
RX1 Undershoot created in VOUT
CX
+ VCSIN -
RX2
ISENP_AUX
Gm
+
- ISENN_AUX Option
VOUT
Lx ∆IOUT x RLL
IMON_AUX R x × Cx >
DCR x
Figure 10. Inductor DCR Current Sensing Method for

∆IOUT
AUX VIMON
Sluggish droop
Figure 11. All Kinds of RC Network Time Constant
Total Current Sense/ICCMAX Setting/Current

Monitoring
To compensate DCR positive temperature coefficient,
conventional current sense method needs an NTC
resistor for per phase current loop. The RT3624BE
adopts a patented total current sense method that
requires only one NTC resistor for thermal
compensation. The NTC resistor is designed within
IMON resistor network on IMON pin. It is suggested to
be placed near the inductor of the first phase. Figure 12
shows the configuration. All phase current signals are
gathered to IMON pin and converted to a voltage signal
VIMON by RIMON, EQ based on VREF pin. The VREF pin
provides 0.6V voltage source (as presented as VVREF)
while normal operation. The relationship between
VIMON and inductor current ILx is:
29
DCR For AXG rail,
VIMON -VVREF =(IL1 +IL2 +…)× ×R
680Ω IMON,EQ VICCMAX =0.4V, when ICCMAX≥40A
VIMON -VVREF is proportional to output current. VICCMAX =0.2V, when 40A>ICCMAX

VIMON -VVREF is used for output current reporting and
loadline loop-control and Sum over-current protection. For AUX,
For the former, VIMON -VVREF is averaged by analog VICCMAX =1.6V for all ICCMAX setting
low-pass filter and then outputs to 8-bit ADC. The
digitized reporting value is scaled such that FFh =
ICCMAX. The RIMON, EQ should be designed that The behavior is masked during DVID. For load-line
loop control, VIMON − VVREF is scaled by a percentage
VIMON -VVREF =VICCMAX while
(IL1 +IL2 +…)=ICCMAXCORE =CORE ICC_MAX register of Ai, that can be selected by Ai[1:0] of PIN-SETTING.
The detailed application is described in the load-line
value, where VICCMAX setting for each rail is shown
setting section.
below :
For CORE rail,
VICCMAX =0.8V, when ICCMAX>80A
VICCMAX =0.4V, when 80A≥ICCMAX≥40A
VICCMAX =0.2V, when 40A>ICCMAX
VCORE
IL1
L DCR
R C
VIMON ISEN1P
+
Gm
IMON - ISEN1N RCS1=680ohm
IIMON1 ICS,PER1
IL2
L DCR
R C
RIMON,EQ
ISEN2P
RNTC +
Gm
- RCS2=680ohm
ISEN2N
IIMON2 ICS,PER2
IL3
VREF L DCR
VVREF R C
ISEN3P
+
Gm
- ISEN3N RCS3=680ohm
IIMON3 ICS,PER3
IL4
L DCR
R C
ISEN4P
+
Gm
- ISEN4N RCS4=680ohm
IIMON4 ICS,PER4
+
- 0.6V
Figure 12. Total Current Sense Method

30
Load-line Setting (RLL) is described as below :
An output voltage load-line (Adaptive Voltage Current Loop Gain DCR Ai 3
RLL = = ×R × ×
Positioning) is specified in CPU VR for power saving Voltage Loop Gain 680Ω IMON,EQ REA2 2
REA1
and output capacitance reduction. The characteristic of REA2
Ai is current gain. R is ERROR AMP gain and
load-line is that the output voltage decreases by an EA1
suggested to be greater than 2 for better transient
amount proportional to the increasing loading current, R
response. RLL can be programmed by Ai and EA2. Ai
i.e. the slope between output voltage and loading REA1
can be selected by PIN-SETTING of Ai[1:0] as listed in
current (RLL) is shown in Figure 13. Figure 14 shows
Table 12.
how the voltage and current loop parameters of
RT3624BE to achieve load-line. The detailed equation
VCORE
VID
Loadline=-RLL
RLL x ICCMAX
Loading
Current
ICCMAX
Figure 13. Load-Line (Droop)
Voltage Loop
VCORE
REA2 PWM
CMP TON
-
REA1 +
+ GEN/
ERROR - Driver
VID Interface
AMP
IL1~IL4
DCR Lx
Rx Ai
+
-
Cx
ISENxP
+ Gm RIMON,EQ
ISENxN
-
IMON RNTC VREF
(sum of ICS,PERx)
Current Loop
Figure 14. Voltage Loop and Current Loop for Loadline
Table 12. PIN-SETTING of Ai

Ai[1:0] Current Gain Setting
00 0.25
01 0.50
10 0.75
11 1.00
31
Dynamic VID (DVID) Compensation different scale of DVID SR, IDVID_LIFT is internally
During DVID transition, an extra current is required to adjusted. Compensating magnitude can also be
charge output capacitors for increasing voltage. The adjusted by REA1 . While DAC just arrives target
charging current approximates to the product of the ( ALERT issue timing), inductor current is still high and
DVID slew rate and output capacitance. For droop needs a time to settle down to the DC loading current.
system, the extra charging current induces extra In the settling time, the falling down current keeps to
voltage droop so that the output voltage cannot reach charge output capacitor (The magnitude is related with
target within the specified time. The extra voltage drop inductor, capacitance and VID). Thus, DVID
approximates to DVID Slew Rate x Output Capacitance compensation can be less than DVID Slew Rate x
x RLL (RLL is the loadline slope, Ω) This phenomenon is Output Capacitance (Capacitance degeneration should
called droop effect. How charging current affects loop be considered). While output capacitance is so large
is illustrated in Figure 15. The RT3624BE provides one that DVID compensation cannot cover, adding a
DVID compensation function as shown in Figure 16. An resistor and capacitor from FB to GND also can provide
internal current IDVID_LIFT is sinking internally from FB similar function. The ERROR AMP compensation
pin to generate DVID compensation, IDVID_LIFT ×REA1 . (resistance and capacitance network among VSEN, FB
IDVID_LIFT for fast DVID SR can be set from SET3 and COMP) also affects DVID behavior. The final
PIN-SETTING of DVID_LIFT[1], 10µA and 20µA. For setting should be based on actual measurement.
Charging
Inductor Current Current
for DVID
Droop Effect
VSEN
VID
Figure 15. Droop Effect in VID Transition

DCR Lx
VIN
Q1 Cx Rx CO1 CO2
Q2
Gate
Driver RESR
Charging
Inductor Current Current
Current for DVID
Sense C2
REA2 C1
TON
- REA1+
Improved VSEN
GEN/ - VID
-
Driver + EA DVID Compensation
Interface PWM +
CMP VID IDVID_LIFT
Optional for extra large

ouput capacitance
Figure 16. DVID Compensation
32
Compensator Design Switching Frequency Setting
The compensator of the RT3624BE doesn't need a The RT3624BE topology G-NAVPTM (Green Native
complex type II or type III compensator to optimize AVP) is one kind of current-mode constant on-time
control loop performance. It can adopt a simple type I control. It generates an adaptive TON (PWM) with input
compensator (one pole, one zero) in the G-NAVPTM voltage (VIN) for better line regulation. The TON is also
topology to fine tune ACLL performance. The one pole adaptive to VID voltage to achieve constant frequency
and one zero compensator is shown in Figure 17. For concept. The constant frequency will let switching
IMVP9.1 ACLL specification, it is recommended to thermal easier to estimate. The RT3624BE provides a
adjust compensator according to load transient ring parameter setting of kTON to design TON width. kTON is
back level. Default compensator values are referred to set by PIN-SETTING of kTON[2:0]. The related setting
the design tool. table is listed in Table 13.
C2
The equations of TON are listed as below :
VID ≥ 0.93V
REA2 C1
VID
REA1 Ton=2.206u× +14ns
- VSEN kTon ∙(VIN)
COMP EA FB
+
VID VID < 0.93V

Figure 17. Type I Compensator 1
Ton=2.05158u× +14ns
k TON ∙(VIN)
Differential Remote Sense Setting
The VR provides differential remote-sense inputs to
eliminate the effects of voltage drops along the PC Table 13. PIN-SETTING of kTON
kTON[2:0] kTON
board traces, CPU internal power routes and socket
contacts. The CPU contains on-die sense pins, 000 0.64
VCC_SENSE and VSS_SENSE. The related connection is 001 0.82
shown in Figure 18. The VID voltage (DAC) is referred 010 1
to RGND to provide accurate voltage at remote CPU 011 1.18
side. While CPU is not mounted on the system, two
100 1.36
resistors of typical 100Ω are required to provide output
101 1.55
voltage feedback.
110 1.73
C1 VSEN
111 2.27
FB REA1 100
-
EA CPU VCC_SENSE
+
+ COUT
CPU
VID -
RGND CPU VSS_SENSE
100
Figure 18. Remote Sensing Circuit
33
The switching frequency can be derived from TON as shown as below. The losses in the CORE power stage and
driver characteristics are considered.
ICC RON LS,max
VID+ N
×(DCR+ nLS
-N×RLL )
Freq= RON LS,max R ONHS,max RON LS,max
ICC ICC
�VIN + ×� - �� ×�TON-TD +TON, VAR �+ × ×TD
N nLS nHS N nLS
VID: VID voltage

VIN: input voltage
ICC: loading current
N: total phase number
RON HS,max : maximum equivalent high-side RDS(ON)
nHS : number of high-side MOSFETs
RONLS,max : maximum equivalent low-side RDS(ON)
nLS : number of low-side MOSFETs.
TD: summation of the high-side MOSFET delay time and rising time
TON, VAR : on-time variation value
DCR: inductor DCR
RLL : loadline setting (Ω).
34
Adaptive Quick Response (AQR) Anti-overshoot (ANTI-OVS)
The RT3624BE adopts Adaptive Quick Response The RT3624BE provides anti-overshoot function to
(AQR) to optimize transient response. The mechanism depress output voltage overshoot. Controller detects
concept is illustrated in Figure 19. Controller detects overshoot by signals related to output voltage. The
output voltage drop slew rate. While the slew rate overshoot trigger level can be adjusted by
exceeds the AQR threshold, all PWM will turn on an PIN-SETTING as listed in Table 15. The CORE
53.3% constant on time. The RT3624BE provides detecting signal comes from COMP. However, COMP
various AQR threshold through PIN-SETTING of varies with compensation. Initial trigger level setting is
AQR_TH. The following equation can initially decide based on the following equation :
the AQR starting trigger threshold. Note that the 4 REA2 4
threshold should be larger than steady-state output ∆COMP× =∆VSEN× × >
3 REA1 3
voltage ripple falling slew rate and also the overshoot
falling slew rate to avoid miss trigger AQR. Antiovershoot Threshold of ANTIOVS_TH[1:0]
The final setting should be according to actual Error
AQR Starting Trigger Threshold = − 4µ × dVSEN
dt AMP compensator design and measurement.
While overshoot exceeds the setting trigger level, all
VBIAS Vdiff
Output voltage PWM_AQR
PWMs keep in tri-state until the zero current is detected
or VSEN back to normal level. Turning off LGs forces
AQR Threshold
positive current flow through body diode to cause diode
VBIAS forward voltage. The extra forward voltage can speed
Output voltage
up inductor current discharge and decrease overshoot.
Iout Table 15. PIN-SETTING of Anti-Overshoot

Threshold
Anti-overshoot
ANTIOVS_TH[1:0]
Vdiff
AQR Threshold Threshold (mV)
00 90
PWM_AQR
01 150
Figure 19. Adaptive Quick Response Mechanism 10 210
11 Disable
Table 14. PIN-SETTING of AQR_TH
AQR Starting Trigger Threshold
AQR_TH[2:0]
(mV)
000 720
001 880
010 1040
011 1200
100 1360
101 1520
110 1680
111 Disable
35
ACLL Performance Enhancement VRAMP will increase when the VCOMP intersects the
The RT3624BE provides another optional function to positive offset. In order to send out another on-time
improve undershoot by applying a positive offset at earlier to improve undershoot. In PS1, except for the
loading edge. Controller detects the COMP signal and
positive offset, an additional 10mV is applied to the
compares it with steady state. While VCOMP variation
exceeds a threshold, an additional positive offset will DAC and one pulse of PWM is also forced to turn on
apply to the output voltage. The threshold can be set while the function is triggered. The positive offset is
through PINSETTING and separately for PS0 and PS1 released gradually with about hundred micro-second.
as listed in Table 16. The smaller index indicates the Figure 20 and Figure 21 show undershoot suppression
easier detection being triggered. The positive offset is
behavior in PS0 and PS1. For different platform, the
related to the compensation.
optimized setting is different. The final setting must be
The ACLL performance enhancement threshold can
based on actual measurement
VEA2
approximate to 60mV/ . In PS0, the slew rate of
VEA1
Table 16. PIN-SETTING of Undershoot Suppression

UDS[1:0] PS0 (Index) PS1 (Index)
00 Disable Disable
01 200 125
10 200 175
11 250 150
Load
Trigger UD
PWM
w/o UD
PWM
w/ UD
Figure 20. Undershoot Suppression Behavior in Multi Phase.
36
Load
Trigger UD
PWM
PWM
Figure 21. Undershoot Suppression Behavior in Single Phase
Over-Current Protection (OCP)

The RT3624BE has sum OCP mechanisms, the threshold of sum OCP for PS0 is defined as
RCS 1
ISUMOC ,PS0 =KSOCP ×VIMONICCMAX × ×
DCR RIMON,EQ
1 RCS 1
ISUMOC ,PS1,2,3 = ×K ×VIMON × ×
phase number SOCP ICCMAX
DCR RIMON,EQ
ICCMAX<40, KSOCP=1.6
ICCMAX>=40, KSOCP=1.3
DCR
While RIMON,EQ is designed exactly for VIMONICCMAX =ICCMAX register value× 680Ω ×RIMON,EQ ,
ICCMAX register value=ICCMAX, and VIMONICCMAX =0.2V, 0.4V or 0.8V according to ICCMAX.
Sum OCP threshold can be simplified as ISUM_OC,PS0 =KSOCP ×ICCMAX and
1
ISUM_OC,PS1,2,3 = ×K ×ICCMAX. Note that the modification of ICCMAX register value cannot change
phase number SOCP
sum OCP threshold.
While inductor current above sum OCP threshold lasts 40µs or 0.5µs during the first DVID up plus 80µs, controller
de-asserts VR_READY and latches PWM in tri-state to turn off high-side and low-side power MOSFETs. Sum OCP
is masked during DVID period and 80μs after VID settles except for the first DVID up plus 80µs. It's also masked
while VID = 0V condition.
37
Mask sum OCP
VID 80μs
Sum OCP threshold
Inductor Current
Inductor current>Sum OCP threshold

40μs 40μs
Sum OCP trigger
VR_READY
Figure 22. SUM OC Protection Mechanism
Over-Voltage Protection (OVP) 23 and Figure 24. When OVP is triggered with 0.5µs
The OVP threshold is linked with VID. The filter time, controller de-asserts VR_READY and forces
classification table is illustrated in Table 17. While VID all PWMs low to turn on low-side power MOSFETs.
= 0V, in case of VR internal setting mode or DACOFF PWM remains low until the output voltage is pulled
or PS4, OVP is masked. When VID ramps up from VID down below 2.1V for DVID from 0V and VID for other
= 0V till the first PWM after VID settles, OVP threshold conditions. After 60µs from OVP trigger, VID starts to
is 2.45V to allow not-fully-discharged VSEN. Otherwise, ramp down to 0V with slow slew rate. During the period,
the OVP threshold is relative to VID and equals to PWM is not allowed to turn on. Controller controls
VID+350mV with minimum limit = 1.35V. While VID ≤ PWM to be low or tri-state to pull down the output
1.0V, the OVP threshold is limited at 1.35V. voltage along with VID.
The OV protection mechanism is illustrated in Figure
38
Table 17. Summary of Over Voltage Protection
Protection Protection
VID Condition OVP Threshold Example Protection Action
Flag Reset
VID=0
(EN=L or VR internal
OVP is masked
setting mode or
DACOFF or PS4)
VR_READY latched
DVID up period from low. Actively pulls
0V to 1st PWM pulse 2.45V. the output voltage to
after VID settles below 2.1V, then
ramp down to 0V
VID = 1.2V,
VCC/VRON
OVP threshold = VREF=1V
VID+350mV if VID Toggle
DVID period from 1.55V.
>1.0V, 1.35V if VID
non-zero VID VID = 0.9V,
≤1.0V VR_READY latched
OVP threshold =
low. Actively pulls
1.35V.
the output voltage to
VID = 1.2V,
below VID, then
OVP threshold =
VID+350mV if VID ramp down to 0V
1.55V.
VID≠0 >1.0V, 1.35V if VID
VID = 0.9V,
≤1.0V
OVP threshold =
1.35V.
2.45V
OVP Threshold
2.1V
VSEN
0V
VR_READY
VID Down (Slow Slew rate)

Indicator 60μs
PWM
Figure 23. Over-Voltage Protection Mechanism for DVID up from 0V
39
OVP Threshold
350mV +- 50mV
VSEN
0V
VR_READY
VID Down (Slow Slew rate)

60μs
Indicator
PWM
Figure 24. Over-Voltage Protection Mechanism
Under-Voltage Protection MOSFETs. UVP is masked during DVID period and

When the output voltage is lower than VID-650mV with 80µs after VID settles. The mechanism is illustrated in
3µs filter time, UVP is triggered and all PWM are in Figure 25.
tri-state to turn off high-side and low-side power
VSEN
VID
650mV
UVP Threshold
PWM
VR_READY
Figure 25. Under-Voltage Mechanism
All protections are reset only by VCC/VRON toggle. rate. For user friendly, RT3624BE provides protection
UVP and OCP protections are listed in Table 18. Note flag to promptly determine which kind of protections is
that the real filter time also depends on the magnitude triggered. As protection happens, VREF will be forced
of detected signal. The signal magnitude will affect to 1V/1.5V/2V for OVP/UVP/SUM_OCP, respectively.
analog comparator’s overdrive voltage and output slew
40
Table 18. Summary of UVP and OCP Protection
DVID
Protection Protection Protection Protection
Protection Threshold mask
Type Flag Action Reset
time
Sum OCP RINT. 1

ISUM_OC,PS0 =KSOCP ×VIMONICCMAX × × VREF=2V
for PS0 DCR RIMON,EQ PWM
VCC/
tri-state, DVID+
Sum OCP 1 RINT. 1 VRON
ISUM_OC,PS0 = ×VIMON × × VREF=2V VR_READY 80us
for non PS0 Toggle
K ICCMAX DCR RIMON,EQ latched low
UVP VID-650mV VREF=1.5V
Thermal Considerations PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for a

The junction temperature should never exceed the WQFN-52L 6x6 package.
absolute maximum junction temperature TJ(MAX), listed The maximum power dissipation depends on the
under Absolute Maximum Ratings, to avoid permanent operating ambient temperature for the fixed TJ(MAX)
damage to the device. The maximum allowable power and the thermal resistance, θJA. The derating curves in
dissipation depends on the thermal resistance of the IC Figure 26 allows the designer to see the effect of rising
package, the PCB layout, the rate of surrounding ambient temperature on the maximum power
airflow, and the difference between the junction and dissipation.
ambient temperatures. The maximum power
5.0
dissipation can be calculated using the following
Maximum Power Dissipation (W)1
Four-Layer PCB
4.5
formula :
4.0
PD(MAX) = (TJ(MAX) − TA) / θJA 3.5
where TJ(MAX) is the maximum junction temperature, 3.0
TA is the ambient temperature, and θJA is the 2.5
junction-to-ambient thermal resistance. 2.0

1.5
For continuous operation, the maximum operating
1.0
junction temperature indicated under Recommended
0.5
Operating Conditions is 125°C. The junction-to-
0.0
ambient thermal resistance, θJA, is highly package 0 25 50 75 100 125
dependent. For a WQFN-52L 6x6 package, the thermal Ambient Temperature (°C)
resistance, θJA, is 26.5°C/W on a standard JEDEC
51-7 high effective-thermal-conductivity four-layer test Figure 26. Derating Curve of Maximum Power
board. The maximum power dissipation at TA = 25°C Dissipation
can be calculated as below :
41
Outline Dimension
Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 5.950 6.050 0.234 0.238
D2 4.650 4.750 0.183 0.187
E 5.950 6.050 0.234 0.238
E2 4.650 4.750 0.183 0.187
e 0.400 0.016
L 0.350 0.450 0.014 0.018
L1 0.300 0.400 0.012 0.016
W-Type 52L QFN 6x6 Package
42
Footprint Information
Number of Footprint Dimension (mm)

Package Tolerance
Pin P Ax Ay Bx By C*52 C1*8 D Sx Sy
V/W/U/XQFN6*6-52 52 0.40 6.80 6.80 5.10 5.10 0.85 0.65 0.20 4.70 4.70 ±0.05
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
43
Datasheet Revision History
Version Date Item Description
P00 2020/4/8 First Edition
Pin Configuration
P01 2020/8/3 Modify
General Description
Features
Functional Block Diagram
P02 2020/11/23 Modify
Operation
Absolute Maximum Ratings
Electrical Characteristics
Typical Application Circuit
P03 2021/2/1 Functional Pin Description Modify
44

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Preliminary RT3624BE

Dual Channel PWM Controller for IMVP9.1 CPU Core Power

Simplified Application Circuit

PWM2 RT9610C MOSFET VCORE

 Suitable for use in SnPb or Pb-free soldering ISEN1N 7 GND 33 FBA

RT3624BE YMDNN : Date Code

17 ALERT SVID alert. (Active low)

18 VR_HOT Thermal monitor output. (Active low)

Controller power supply. Connect this pin to 5V and place a RC filter, R =

Loading Current ΔIcc

Sensed Current Signal

Figure 1. G-NAVPTM Behavior Waveform

SET4, TSEN, TSENA, PSYS, IMONAVG, IMONAAVG

ERROR AMP Zero Current Detection

Recommended Operating Conditions (Note 4)

Parameter Symbol Test Conditions Min Typ Max Unit

VIN = 19V, VID = 0.9V,

VRON Logic-High VIH 0.7 -- --

VCLK, VDIO Logic-High VIH 0.65 -- --

PSYS Maximum Input Voltage PSYS VPSYS = 1.6V -- 255 -- Decimal

VSYS Maximum Input Voltage VSYS VIN/VSYS=24V -- 255 -- Decimal

Average Period of IMON tIMON -- 150 -- µs

Average Period of TSEN tTSEN -- 600 -- µs

TSEN Voltage Threshold to

R21 R22 R23 R24 R25 5V R54 C39

VR Initial Setting Mode Internal Setting

Figure 2. Typical Timing of Controller Power-ON.

Figure 3. 3-Phases Operation Setting

platform setting and BOM optimization. These

Acoustic Noise Suppression VREF =

SET1 According to Platform, set CORE VR

Vdivider_SET2 (mV) VBOOT_A VIDT kTON

VTSEN (mV) Ai AQR_TH

VTSENA (mV) Ai_A AQR_TH_A

TSEN pin processes two functions of PIN-SETTING

System Input Voltage Monitoring (VSYS)

Loading Current ΔIcc

Figure 7. Zero Load-line without AC-droop Control

Output Voltage ΔV3

ΔV1 VID Target

Short-term voltage target

Figure 8. Zero Load-line with AC-droop Control

VCSIN ILx ×DCR

Figure 9. Inductor DCR Current Sensing Method for

ILx VAUX ∆IOUT

Figure 10. Inductor DCR Current Sensing Method for

Figure 11. All Kinds of RC Network Time Constant

Total Current Sense/ICCMAX Setting/Current

VIMON -VVREF is proportional to output current. VICCMAX =0.2V, when 40A>ICCMAX

Figure 12. Total Current Sense Method

Figure 13. Load-Line (Droop)

Figure 14. Voltage Loop and Current Loop for Loadline

Table 12. PIN-SETTING of Ai

Figure 15. Droop Effect in VID Transition

Optional for extra large

Figure 16. DVID Compensation

VID VID < 0.93V

Figure 18. Remote Sensing Circuit

VID: VID voltage

Iout Table 15. PIN-SETTING of Anti-Overshoot