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313303 - Digital Techniques (Sem III)

As per MSBTE’s K Scheme
CO / CM / IF

UNIT 4 Sequential logic circuits Marks : 18

Sr.
Questions Year Marks
No.
1 Draw logic diagram of T flip-flop and give its truth table W- 2
18

2 Define modulus of a counter. Write the numbers of flip flops required for Mod-6 W- 2
counter. 18

 Modulus of counter is defined as number of states/clock the countercountes.

 The numbers of flip flops required for Mod-6 counter is 3.
3 State function of preset and clear in flip flop. W- 2
18
 In the flip flop, when the power is switched on, the state of the circuits
uncertain i.e. may be Q = 1 or Q = 0.
 Hence, the function of preset is to set a flip flop i.e. Q = 1and the function
ofclear is to clear a flip flop i.e. Q = 0.

4 Describe the working of JK flip-flop with its truth table and logic diagram W- 4
18

W- 4
19
5 Draw and explain working of 4 bit serial Input parallel Output shift register. W- 4
18
 Basic Data Movement Through A Shift Register

6 Design a 4 bit synchronous counter and draw its logic diagram W- 6

18
7 Give block schematic of decade counter IC 7490. Design Mod-7 counter using this IC W- 6
18

W- 6
22

S-23 6
8 Draw symbol and write truth table of D and T Flip Flop. W- 2
19
9 Write down number of flip flops are required to count 16 clock pulses. W- 2
19
No of states= no.of clock pulses = 16

2n =m
n = no.of flip flops requried
m= no.of states
2n = 16
n=4
4 flip flops are required to count 16 clock pulse.

10 Describe the working of JK flip flop with truth table and logic diagram W- 4
19
logic Diagram:

Working:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
 that prevents the illegal or invalid output condition that can occur when both inputs S and
R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q.
This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1”
and R = “1” state to be used to produce a “toggle action” as the two inputs are now
interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status
Of Q through the lower NĀND gate. If the circuit is “RESET” the K input is inhibited by
the “0” status of Q through the upper NAND gate. As Q and Q are always different we can
use them to control the input. When both
inputs J and K are equal to logic “1”, the JK flip flop toggles

11 Describe the working of 4 bit SISO (serial in serial out) Shift Register with diagram W- 4
and waveform if input is 01101. 19

Diagram:(use SR or JK or D type flip flop)

W- 4
22

Working:
The DATA leaves the shift register one bit at a time in a serial pattern, hence the
name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the
serial output (SO) which is taken from the output of the right hand flip-flop and the
sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-
in serial-out shift register, Output of FFA is Q4,FFB Q3,FFC Q2 and FFD is Q1

Waveform:(Input is 01101)
12 Describe the working of ring counter using D flip flop with diagram and waveforms. W- 4
19
Diagram:

Waveforms:
 Working:
The ring counter is a cascaded connection of flip flops, in which the output of last flip flop
is connected to input of first flip flop. In ring counter if the output of any stage is 1, then its
reminder is 0. The Ring counters transfers the same output throughout the circuit.
That means if the output of the first flip flop is 1, then this is transferred to its next stage i.e.
2nd flip flop. By transferring the output to its next stage, the output of first flip flop
becomes 0. And this process continues for all the stages of a ring counter. If we use n flip
flops in the ring counter, the „1‟ is circulated for every n clock cycles

13 Design a 4bit ripple counter using JK flip flop, with truth table and waveforms. W- 6
19
Circuit Diagram:

Truth Table:
 Timing Diagram / Waveforms:

14 Design a 3 bit synchronous counter using JK FlipFlop W- 6

19
1) Step1:
Construct JK state table with corresponding excitation table:
Output State Transitions

Present Next
State
state Q2 Flip-flop inputs
Q2 Q1 Q0
Q1 Q0 J2 K2 J1 K1 J0 K0

000 001 0X 0X 1X

001 010 0X 1X X1
 010 011 0X X0 1X

011 100 1X X1 X1

100 101 X0 0X 1X

101 110 X0 1X X1

110 111 X0 X0 1X

111 000 X1 X1 X1

State Table and Corresponding Excitation Table (d=don't care)

Step 2:
Build Karnaugh Map or Kmap for each JK inputs:

Step3:
Draw the complete design as below:
15 Compare between synchronous and asynchronous counter (any two points). S-19 2

16 Describe the operation of R-5 flip-flop using NAND gates only. S-19 4

Description/explanation-

When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective of the
values of S and R. That means R’= S’ = 1.Hence the outputs of basic SR/F/F i.e. Q n+1 and
̅𝑄𝑄
̅ ̅+
1̅ will not change. Thus if clock = 0, then there is no change in the output of the
 Clocked SR flip-flop.

Case I : S = R = 0, clock = 1: No change

If S=R=0 then outputs of NAND gate 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since R' and S' are the inputs of the basic S – R flip-
flop using NAND gates. There will be no change in the state of outputs.

Case II : S =1, R = 0, clock = 1: Set

Now S=0, R=1 and a positive going edge is applied to the clock
Output of NĀND 3 i.e. R’ = 0 and output of NĀND 4 i.e. S’ = 1.
Hence output of SR flip-flop is Q n+1 = 1 and 𝑄̅ ̅+
̅𝑄 1̅ = 0.
This is the set condition.

Case III : S =0, R = 1, clock = 1: Reset

Now S=0, R=1 and a positive edge is applied to the clock input.
Since S=0, output of NAND – 3 i.e. R´= 1. And as R’ = 1 and clock = 1 the output of NAND-4
̅
̅ ̅̅+
i.e. S´ = 0. Hence output of SR flip-flop is Q n+1 = 0 and ̅𝑄𝑄 1̅= 1.
This is the reset condition.

Case IV : S =1, R = 1, clock = 1: Undefined/ forbidden

As S=1, R=1 and clock = 1, the outputs

̅̅ of NAND gates 3 and 4 both are 0 i.e. S' = R'=0. So
̅
both the outputs Q n+1 = 1 and 𝑄𝑄+̅ ̅ ̅
1
Hence output is Undefined/ forbidden.

17 State the applications of shift register. S-19 4

1] Shift register is used as Parallel to serial converter, which converts the parallel
data into serial data. It is utilized at the transmitter section after Analog to Digital
 Converter (ADC) block.

2] Shift register is used as Serial to parallel converter, which converts the serial
data into parallel data. It is utilized at the receiver section before Digital to Analog
Converter (DAC) block.

3] Shift register along with some additional gate(s) generate the sequence of zeros
and ones. Hence, it is used as sequence generator.

Shift registers are also used as counters. There are two types of counters based on the type
of output from right most D flip-flop is connected to the serial input. Those are Ring counter
and Johnson Ring counter.

18 Describe the working of J-K flip- flop and state the race around condition. S-19 4

The clock signal is applied to CLK input.

IF CLK =0 than F/F is disabled and O/P Q and 𝑄̅do not change

If CLK= 1 and J=K=O then the output Q and 𝑄̅will not change their state.
If J=0 and K= 1 then JK flip flop will reset and Q= 0 & 𝑄̅
=1 If J=1 and K=0 then output will be set and Q=1 & 𝑄̅
=0
 If J= K=1 then Q & 𝑄̅ outputs are inverted and FF will toggle
Race Around condition:
Race around condition occurs in J K Flip-flop only when J=K=1 and clock/enable is high
(logic 1) as shown below-

In JK Flip-flop when J=K=1 and when clock goes high, output should toggle (change to
opposite state), but due to multiple feedback, output changes/toggles many times till
the clock/enable is high.
Thus toggling takes place more than once, called as racing or race around condition
 .

19 Describe the working of 4 bit universal shift register S-19 6

S-22 6

S-24 6

20 Design a mod-6 Asynchronous counter with truth-table and logic. S-19 6

MOD 6 asynchronous counter will require 3 flip flops and will count from 000 to 101. Rest
of the states are invalid. To design the combinational circuit of valid states, following truth
table and K-map is drawn:

From the above truth table, we draw the K-maps and get the expression for the MOD 6
asynchronous counter.

Fig: K-map for above truth table

Thus reset logic is OR of complemented forms of QC and QB. This will be given to the reset
inputs of the counter so that as soon as count 110 reaches, the counter will reset. Thus the
counter will count from 000 to 101. The implementation of the designed MOD 6
asynchronous counter is shown below:
21 Draw symbol and write the truthtable for T-flipflop. W- 2
22

22 Describe the working of SR flipflop with its truth table and logic diagram. W- 4
22
23 Describe working of Master-slave JK flipflop with truth table and logic diagram. W- 4
22
24 Explain 3 bit asynchronous counter with output waveforms. W- 6
22
25 Give the block schematic of decade counter IC 7490. Design mod-7 counter using IC W- 6
22
26 List triggering methods used for triggering flip flops. S-22 2

27 Define shift register and list its types S-22 2

28 Write truth table of D type flip-flop. S-22 2

29 Design MOD-12 ripple counter. Write its truth table with waveform S-22 6
30 Explain the role of counters in digital circuits and design Mod -> counter using IC W- 8
7490. 23
31 Draw and explain 4-bit universal shift register. Also explain the necessity of register W- 8
in digital circuits. 23
32 Define counter. S-23 2

33 Draw the symbol of D flip-flop and write its truth table. S-23 2
34 List the basic types of shift register. S-23 2

35 Draw 4 bit twisted ring counter and explain working with truth table and waveforms S-23 4
36 Draw the block diagram of digital comparator IC 7485 and explain with the help of S-23 4
truth table.
37 Design nod-6 counter using IC 7490 and explain its design with working. S-23 6
38 Design synchronous decade counter using D flip-flop. S-23 6
39 Write the one application of SR-FF and mention its one drawback S-24 2

Application of SR-FF:
1) It is used in memory storage devices to store data temporarily such as registers
and registers are used in counters, microprocessors and digital signalprocessors.
Drawback of SR-FF:
1) When the inputs of SR-FF are S=0, R=0 or S=1, R=1, the outputs are eitherinvalid or do
not change due to race condition.

40 Draw excitation table of T FF S-24 2

Excitation table of T FF:

Output Q Input
Present state Next state (Qn+1) Tn
(Qn)
 0 0 0
0 1 1
1 0 1
1 1 0
41 Name four types of shift register S-24 2

Types of shift register:

1) Serial Input Serial Output (SISO)
2) Serial Input Parallel Output (SIPO)
3) Parallel Input Serial Output (PISO)
4) Parallel Input Parallel Output (PIPO)
5) Bidirectional Shift Register
6) Universal Shift Register

42 Design the IC7490 as mod- B counter and describe its operation. S-24 4

Design IC7490 as mod-8

A mod-8 counter will count the first step from 0 to 7 and reset at ninth step.For

remaining all step, output Y = 0

K-Map
Expression of Y

Operation

A mod-8 counter is a circuit that counts from 0 to 7 and then resets to 0. It can be built
using a variety of different integrated circuits (ICs), but one common choice is the IC
7490.

The IC 7490 is a decade counter, which means that it can count from 0 to 9. However, it can
be configured to work as a mod-8 counter by connecting two of its reset pins together.
When this is done, the counter will count from 0 to 7 and then reset to 0.
 Here is an example of how to build a mod-8 counter using the IC 7490:
Connect pins 2 and 3 of the IC 7490 together.
Connect pin 4 of the IC 7490 to VCC. Connect pin 5 of
the IC 7490 to ground. Connect pin 6 of the IC 7490 to
a clock signal.
Connect pins 11, 10, 9, and 8 of the IC 7490 to four LEDs.

43 Describe the working of clocked SR flip-flop with preset and clear. S-24 4

Fig. : Clocked SR Flip Flop

Working of clocked SR flip-flop with preset and clear:

In the flip-flop when the power is switched ON, the state of the circuit is uncertain. It may
come to set (Q=1) or reset (Q=0) state.
In many applications it is desired to Initially set or reset the flip-flop l.e. the initial state of
the flip-flop is to be assigned. This is accomplished by using preset (Pr) and clear (Cr)
Inputs.
These inputs may be applied at any time between clock pulses and are not in
synchronism with the clock. An S-R flip-flop with preset and clear is shown in Fig. If Pr =
Cr = 1, then both the circuit operates in accordance with the truth table of S- R flip-flop
given in table.
If Pr = 0 and Cr = 1, the output of G1 (Q) will certainly be 1. Consequently, all
the three inputs to G2 will be 1 which will make Q = 0. Hencemaking
Pr = 0 sets the flip-flop.
Similarly, if Pr = 1 and Cr = 0 then the flip-flop is reset.
The condition Pr = Cr = 0 must not be used, since this leads to an uncertain state.
Truth Table:

Table: Clocked SR flip-flop with preset and clear

Inputs operation
output
clk Pr Cr performed
 1 1 1 Qn-1 Normal SR FF
x 0 1 1 FF is set
x 1 0 0 FF is reset
44 Design 4 bit ripple counter and draw output waveforms. S-24 6

Since it is 4 bit Ripple up counter , we need to use four Flip Flops .Initially
all the Flip Flops have Zero output QDQCQBQA = 0000
All the Flip Flops are negative edge triggered CLK is applied to the clock input ofFF-A .
Where as Q output of every Flip Flop is applied to the clock input of next Flip Flop.

Truth Table of 4 bit ripple counter:

Clock FF
outputs
QD QC QB QA
Initially 0 0 0 0
1 (↓) 0 0 0 1
2 (↓) 0 0 1 0
3 (↓) 0 0 1 1
4 (↓) 0 1 0 0
5 (↓) 0 1 0 1
6 (↓) 0 1 1 0
7 (↓) 0 1 1 1
8 (↓) 1 0 0 0
9 (↓) 1 0 0 1
10 (↓) 1 0 1 0
11 (↓) 1 0 1 1
12 (↓) 1 1 0 0
 13 (↓) 1 1 0 1
14 (↓) 1 1 1 0
15 (↓) 1 1 1 1
16 (↓) 0 0 0 0

Waveforms:

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