QUIZ QUESTIONS

Advanced VLSI (21EC71) Faculty: Chetan S

Module 1: Introduction to ASICs and CMOS Logic

1. What is the primary difference between full-custom and semi-custom ASICs?

a) Full-custom allows customization of all mask layers, while semi-custom does
not.
b) Semi-custom has higher manufacturing costs.
c) Full-custom uses pre-designed standard cells.
d) Semi-custom is used only for analog circuits.
Answer: a

2. Which type of adder uses a "carry-lookahead" mechanism to improve speed?

a) Ripple Carry Adder
b) Carry Save Adder
c) Carry Select Adder
d) Carry-Lookahead Adder
Answer: d

3. What is the main advantage of CMOS over bipolar technology for mixed analog-
digital ASICs?
a) Higher precision in analog circuits
b) Better availability and integration needs
c) Lower power consumption in analog
d) Less expensive fabrication
Answer: b

4. In standard-cell-based ASICs, the term "megacells" refers to:

a) Flip-flops and latches
b) Small logic gates
c) Pre-designed larger blocks like microprocessors
d) Unused base cells
Answer: c

5. What is a key feature of Programmable Logic Devices (PLDs)?

a) No mask layers are customized
b) Uses analog circuits
c) Fixed functionality post-manufacturing
d) High manufacturing costs
Answer: a

6. In CMOS logic, the p-channel transistor turns on when:

a) The gate receives a logic '1'
b) The gate receives a logic '0'
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
c) The source is grounded
d) None of the above
Answer: b

7. Which power supply voltage represents logic '1' in CMOS circuits?

a) V_CC
b) V_SS
c) V_DD
d) GND
Answer: c

8. What component in CMOS gates ensures low static power consumption?

a) Resistive pull-ups
b) Complementary transistors
c) Dedicated power supplies
d) None of the above
Answer: b

9. The carry output in a 4-bit ripple carry adder depends on:

a) Input data alone
b) Intermediate carries from previous stages
c) Clock pulses
d) Propagation delay
Answer: b

10. What determines the delay in a carry-save adder?

a) Number of bits in inputs
b) Propagation delay in XOR gates
c) Interconnection length
d) Clock frequency
Answer: b

Module 2: Floorplanning, Placement, and Routing

1. What is the primary objective of floorplanning?

a) Minimize chip size and interconnect delay
b) Improve power consumption
c) Optimize clock frequencies
d) Avoid transistor mismatch
Answer: a

2. Which tool is commonly used to define interconnect channels during

floorplanning?
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
a) Netlist optimizer
b) Channel allocation tools
c) Delay estimator
d) Schematic editors
Answer: b

3. What is the purpose of back annotation in global routing?

a) To estimate power dissipation
b) To incorporate post-layout delays into simulation
c) To define power supply pads
d) To perform hierarchical synthesis
Answer: b

4. In placement, the min-cut algorithm is used to:

a) Divide the chip into smaller functional blocks
b) Optimize transistor sizing
c) Define the clock tree
d) Predict interconnect delays
Answer: a

5. What does I/O and power planning involve?

a) Selecting logic gates
b) Arranging pads and distributing power efficiently
c) Optimizing signal timing
d) Ensuring ESD protection only
Answer: b

6. The term "clock skew" refers to:

a) Variation in interconnect capacitance
b) Difference in clock arrival times at different parts of the chip
c) Voltage fluctuations in clock lines
d) None of the above
Answer: b

7. The global routing process ensures:

a) Power distribution
b) Connections between different blocks
c) Channel allocation
d) Both b and c
Answer: d

8. Which step follows floorplanning in the physical design flow?

a) Logic synthesis
b) Placement
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
c) Back annotation
d) DRC
Answer: b

9. Which factor significantly impacts interconnect delay in floorplanning?

a) Transistor size
b) Die size and fanout
c) Power consumption
d) Fabrication cost
Answer: b

10. In routing, a "rat's nest" diagram indicates:

a) Clock skew distribution
b) Initial unoptimized net connections
c) Signal timing violations
d) None of the above
Answer: b

Module 3: Verification and Data Types

1. Which methodology is commonly used for generating test cases in verification?

a) Directed testing
b) Constrained random stimulus
c) Manual debugging
d) Sequential coverage
Answer: b

2. Functional coverage measures:

a) Hardware resources used
b) The extent of functional scenarios tested
c) Fault-tolerant designs
d) Compiler efficiency
Answer: b

3. What is a key benefit of using dynamic arrays in System Verilog?

a) Fixed memory size
b) Runtime size adjustment
c) Simplified timing
d) Easier synthesis
Answer: b

4. Which data type in System Verilog supports linked lists?

a) Fixed arrays
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
b) Associative arrays
c) Dynamic arrays
d) User-defined structures
Answer: d

5. Built-in data types in System Verilog include:

a) Floating-point types
b) Queues
c) Complex numbers
d) Enumerated types
Answer: b

6. What is the primary purpose of a test bench?

a) Implementing hardware components
b) Validating design functionality
c) Generating netlists
d) Synthesizing Verilog code
Answer: b

7. Enumerated data types are primarily used to:

a) Store floating-point values
b) Create meaningful symbolic constants
c) Define memory arrays
d) Optimize clock speeds
Answer: b

8. Constrained random stimulus generation ensures:

a) All possible cases are exhaustively tested
b) Scenarios follow specified constraints
c) Faster verification
d) Reduction in code size
Answer: b

9. Functional coverage includes:

a) Structural coverage
b) Assertion-based coverage
c) Directed test coverage
d) All of the above
Answer: d

10. System Verilog assertions are useful for:

a) Writing test benches
b) Monitoring design behavior
c) Creating synthesis reports
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
d) Clock tree design
Answer: b

Module 4: Procedural Statements and Test Bench

1. Which System Verilog construct separates test bench from design?

a) Tasks
b) Interfaces
c) Assertions
d) Functions
Answer: b

2. Local storage in tasks is useful for:

a) Returning multiple values
b) Avoiding interference between task calls
c) Increasing execution speed
d) Enabling dynamic memory allocation
Answer: b

3. What type of procedural statement allows conditional execution?

a) Blocking assignment
b) Non-blocking assignment
c) if-else statements
d) None of the above
Answer: c

4. A System Verilog void function:

a) Returns integer values
b) Has no return value
c) Is used for synthesis
d) Always returns a signal
Answer: b

5. Stimulus timing refers to:

a) Generating stimuli with specific time intervals
b) Synthesis constraints
c) Handling clock skew
d) Verifying coverage
Answer: a

6. In a layered test bench, the scoreboard is used for:

a) Clock generation
b) Random stimulus generation
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
c) Result comparison with expected outputs
d) Netlist simulation
Answer: c

7. Separating test bench from design ensures:

a) Independent verification
b) Better synthesis
c) Reduced power consumption
d) None of the above
Answer: a

8. System Verilog assertions help in:

a) Synthesizing designs
b) Checking functional correctness during simulation
c) Routing interconnects
d) Timing optimization
Answer: b

9. Interface constructs are used to:

a) Reduce signal connections
b) Enhance simulation speed
c) Automate synthesis
d) Improve routing efficiency
Answer: a

10. Connecting a test bench with design requires:

a) Clock buffers
b) Interfaces
c) Memory arrays
d) None of the above
Answer: b

Module 5: Randomization and Functional Coverage

1. What does System Verilog's randomization feature enable?

a) Exhaustive testing
b) Generation of constrained random inputs
c) Static timing analysis
d) Functional decomposition
Answer: b

2. Which function generates random numbers in System Verilog?

a) rand()
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
b) randomize()
c) randc()
d) randomize_with()
Answer: b

3. Functional coverage is used to:

a) Measure clock delays
b) Track simulation progress
c) Verify testing completeness
d) Generate random test cases
Answer: c

4. Cross coverage involves:

a) Verifying all combinations of variables
b) Measuring code execution
c) Tracking design latency
d) All of the above
Answer: a

5. A covergroup is defined to:

a) Analyze timing performance
b) Measure test coverage metrics
c) Control power consumption
d) Generate clock signals
Answer: b

6. Data sampling in a covergroup ensures:

a) Random values are selected
b) Relevant values are monitored
c) Fault tolerance improves
d) Coverage data is updated
Answer: b

7. Random number generators in System Verilog can be constrained using:

a) if-else conditions
b) Randomization constraints
c) Static analysis tools
d) Synthesis optimizations
Answer: b

8. Triggering a covergroup involves:

a) Initiating a coverage session
b) Sampling specified variable states
c) Collecting coverage metrics
 QUIZ QUESTIONS
Advanced VLSI (21EC71) Faculty: Chetan S
d) All of the above
Answer: d

9. Coverage analysis helps in:

a) Identifying untested scenarios
b) Optimizing simulation time
c) Randomizing inputs
d) Synthesizing test benches
Answer: a

10. Which type of coverage focuses on input stimulus?

a) Code coverage
b) Assertion coverage
c) Functional coverage
d) Behavioral coverage
Answer: c