SRM Institute of Science and Technology

College of Engineering and Technology Mode of Exam

School of Computing OFFLINE
(Common to all Branches)
DEPARTMENT OF COMPUTING TECHNOLOGIES
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu

Academic Year: 2023-24 (ODD)

Test: CLAT3 Date: 8.11.2023

Course Code & Title: 21CSS201T / COA Duration: 100 minutes
Year & Sem: II & III SET A Max. Marks: 50
Course Articulation Matrix:
Course
Learning At the end of this course, learners will PO PO PO PO PO PO PO PO PO PO PO PO
Outcomes be able to: 1 2 3 4 5 6 7 8 9 10 11 12
(CLO)
Analyze concepts of parallelism and - - - - - - -
CO-4 H - - - -
multi-core processors
Classify the memory technologies,
- - - - - - -
CO-5 input-output systems and evaluate the H M - - -
performance of memory system

Part – A
Instructions: Answer all (10 x 1 = 10 Marks)

Q. Question Marks BL CO PO PI
No Code
1. Pipelining increases ____________ of the processor 1 1 4 1.3 1.3.1
a. Throughput
b. Latency
c. Storage
d. Predictivity
2 operand forwarding method does the following to overcome data 1 2 4 1.3 1.3.1
dependencies

a. Introduce NULL instructions

b. Result of the instruction is written to the temporary register
c. Result of one instruction is directly sent to the next instruction for
execution
d. Blocking the execution of instructions
3 For a four-stage pipelining, the initial instruction requires _____ cycle for 1 1 4 1.3 1.3.1
execution completion?
a. 2
b. 4
c. 3
d. 1
4 When the data operands are not available then it is called ___ 1 1 4 1.3 1.3.1
a. Data hazard
b. Structural hazard
c. Control hazard
d. Instruction hazard
5 When the branch is actually not taken the state moves from ST to ____. 1 1 4 1.3 1.3.1
a. SNT
b. LT
c. LNT
d. ST
6 Which type of parallelism involves breaking down a program into 1 1 5 1 2.1.2
smaller tasks that can be executed concurrently?
A. Instruction-level parallelism
B. Data-level parallelism
C. Task-level parallelism
D. Pipeline parallelism
7 What is the primary advantage of MIMD architecture compared to 1 1 5 1 2.1.2
SISD architecture?
A. Lower cost
 B. Simplicity of programming
C. Higher processing power for parallel tasks
D. Energy efficiency
8 Which part of an ARM instruction specifies the operation to be 1 1 5 1 2.1.2
performed?
A. Opcode
B. Data register
C. Memory address
D. Condition code
9 Which part of an ARM-based system typically handles I/O 1 1 5 1 2.1.2
operations and device communication?
a) Memory unit
b) Arithmetic logic unit (ALU)
c) Input unit
d) Peripheral interface or controller
10 What is the primary advantage of the Thumb instruction set in 1 1 5 1 2.1.2
ARM7 architecture?
a. Greater computational power
b. Smaller code size
c. Enhanced multimedia capabilities
d. Improved memory management

Part – B
Instructions: Answer any 4 ( 4 x 4 = 16 Marks)

11 Design a 4-stage instruction pipeline for 3 instructions I1,I2,I3 to be executed. Consider that there are no
dependency between the instructions.

12 Draw and explain the two state diagram for dynamic branch prediction.
• State 1: LT : Branch is likely to be taken
• State 2: LNT : Branch is likely not to be taken
• 1.If the branch is taken,the machine moves to LT. otherwise it remains in state LNT.
• 2.The branch is predicted as taken if the corresponding state machine is in state LT, otherwise it is
predicted as not taken

13 Interpret about out of order execution?

• If an optimizing compiler attempts to reorder instruction to avoid stalling the pipeline when branches or data
dependencies between successive instructions occur, it must ensure that reordering does not cause a change in the
outcome of a computation.
• The dependency introduced by the condition-code flags reduces the flexibility available for the compiler to
reorder instructions.
14 Discuss the five step Sequential execution with example

15 Discuss the concepts involved in ILP and how many unit of time to complete the operations
• Instruction level Parallelism (ILP) is a measure of how many operations can be performed in
parallel at the same time in a computer.

• Parallel instructions are set of instructions that do not depend on each other to be executed.

• ILP allows the compiler and processor to overlap the execution of multiple instructions or
even to change the order in which instructions are executed.

3 operations can be completed in 2 units of time .

PART C
Instructions: Answer all (12 x 2 = 24 Marks)

16. A Arun and Bob are having equal number of apples and it’s count are stored in the register R1 and R2
respectively. Arun collected bob’s apple and store the entire set of apples with him and update its count in R1.
Write the complete set of control sequences for the above operation.
 OR
16. B Illustrate the scenario where instructional hazard occurs and provide the solution for handling the stall created
by conditional branch instruction.
• If Sequence of instruction being executed in two stages pipeline instruction I1 to I3 are stored at consecutive
memory address and instruction I2 is a branch instruction.
• If the branch is taken then the PC value is not known till the end of I2.
• Next third instructions are fetched even though they are not required
• Hence they have to be flushed after branch is taken and new set of instruction have to be fetched from the
branch address

Branch penalty
• The time lost as the result of branch instruction
Reducing the penalty
• The branch penalties can be reduced by proper scheduling using compiler techniques.
• For longer pipeline, the branch penalty may be much higher
• Reducing the branch penalty requires branch target address to be computed earlier in the pipeline
• Instruction fetch unit must have dedicated hardware to identify a branch instruction and compute branch
target address as quickly as possible after an instruction is fetched
Instruction prefetching

17 A. Explain the various types of Parallelism.

Hardware Parallelism
• Processor parallelism
• Memory parallelism
Software Parallelism
 Sequential execution
 Parallel execution
 Instruction level parallelism
 Task-level parallelism
 Data parallelism
 Transaction level parallelism

OR
17 B With the evolution of computing, multi-core processors have become a standard in modern computer
architectures.
a. Define and differentiate between a processor and CPU cores. (4 marks)
The processor is the primary component of a computer that performs most of the
processing inside the computer. It interprets computer program instructions and processes
data. The CPU acts as the brain of the computer. CPU Cores: A core is a component within
 the processor. It can read and execute program instructions independently of the other
cores. Modern processors can have multiple cores (dual-core, quad-core, etc.), allowing
them to read and execute multiple instructions simultaneously, essentially like having
multiple processors in a single chip. Differentiation: The primary difference is that while a
processor refers to the main computational unit that interprets and executes instructions, a
core is a part of this unit, and a processor can have one or more cores. The more cores a
processor has, the more tasks it can handle simultaneously. Explain with relevant diagrams.
b. Discuss the advantages and potential challenges of multi-core processors compared to single-core
processors. (6 marks)
Advantages: Parallel Processing: Multi-core processors can handle multiple tasks
simultaneously, leading to better multitasking and parallel processing capabilities. Energy
Efficiency: Distributing tasks among multiple cores can be more energy-efficient, as each
core can run at a lower speed, reducing heat generation. Performance Boost: For software
designed to take advantage of multi-core architectures, significant performance
improvements can be observed. Challenges: Software Limitations: Not all software is
designed to utilize multiple cores effectively. Some older applications might not benefit
from multi-core processors. Diminishing Returns: As the number of cores increases, the
performance gains can start to diminish unless software and tasks are perfectly
parallelizable. Complexity: Managing multiple cores can introduce complexities in terms of
synchronization, data sharing, and the potential for increased cache misses. Explain with
relevant diagrams.
c. Explain how software developers might need to adapt their programming techniques to fully utilize the
capabilities of multi-core processors. (2 marks)
Software developers need to adopt parallel programming paradigms to leverage multi-core
processors effectively. This involves breaking down tasks into smaller sub-tasks that can be
executed concurrently. Tools and libraries, such as OpenMP and Threading Building Blocks
(TBB), can assist developers in this. Additionally, developers must be aware of potential
pitfalls like race conditions and deadlocks, which can arise when multiple cores access
shared resources.