Perspec System Verifier

SoC verification with portable stimulus

The Cadence® Perspec™ System Verifier is a portable stimulus, system-on-chip (SoC) verification
solution. The Perspec System Verifier improves SoC quality and saves time by reducing
development effort for defining complex SoC-level use cases, amplifying use-case exploration of
state space and timing on fast platforms, creating coverage-driven automation of system use-case
generation, bridging UVM and SoC verification methodology, and shrinking the time required to
reproduce, debug, and fix complex SoC-level bugs.

Requirements for SoC ments for SoC-level verification. To and automcally amplify use cases to
Verification fully address SoC-level verification, a speed test-case creation and leverage
solution must extend from UVM and fast verification engines.
While the bottom-up approach allow for vertical (IP to SoC) reuse and
offered by UVM-constrained random The Perspec System Verifier addresses
horizontal (verification engine porta-
and coverage-driven verification these three key requirements
bility) reuse. And most importantly it
revolutionized IP and unit-level highlighted in Figure 1. By offering an
must provide a way to capture, share,
testing, it doesn’t meet the require- abstract model-based approach, the

Use Case Reuse

Multi-Core Diverse User
I/O and Cache Post-Silicon
Diverse Scopes Hardware Software Verification Software Test Solution Requirements
Coherency (Integration) Architect
Developer Developer Engineer Engineer
Validation
Engineer

Middleware ARMv3 CPU Subsystem Automation

Application-Specific Components
(Graphics, Audio, etc...) (at SoC level)
CPU CPU CPU CPU • Fast platform tests
Sofware-Driven

Resource-Aware Modem typically coded manual

OS and Drivers L2 Cache L2 Cache 3D DSP Boot in C
Activity GFX A/V Processor
• Simulation focused
Coordination Cache Coherent Fabric solutions do not handle
Bare-Metal
Vertical Reuse

system use-cases,
Software software perspective,
Soc Interconnect Fabric acceleration
SoC
(Hardware + Software)

Performance HDMI GPIO UART Portability and Reuse

PCIe®
DDR3 USB 3.0 Ethernet Address needs of
Use Cases Gen 2, 3 SATA Display INTC •

and Tuning Subsystems MIPI® PMU 12C diverse stake holder

3.0 2.0 WLAN MIPI SPI • Reuse across platforms
PHY PHY PHY
PHY PHY LTE JTAG TIMER Connect to UV for IP
UVM

•
IP High-Speed Wired Interface Peripherals Other Peripherals Low-Speed Peripherals and subsystem
verification
• With or without cores
Virtual and Hybrid
Xcelium Palladium Protium Silicon Board in DUT
Low-Power Platform
Use Cases Diverse Verification Engines

Horizontal Reuse

Figure 1: SoC Verification with Portable Stimulus

 Perspec System Verifier

Perspec solution not only enables capture • Widespread knowledge of the C Product Overview
of use cases, but through abstraction language and the availability of C
The Perspec System Verifier is a model-
makes reuse, sharing, and amplification compilers
based, goal-directed SoC verification
of the use cases easy. In order to deliver
• Ever-growing software layers that product developed to meet these
real tests, a solver is required to automate
need to be verified with the hardware challenges. The Perspec usage flow
the creation of concrete use cases either
components (both test software and includes the following steps:
through randomization or if requested
production-level software are likely
through coverage filling. These concrete 1. Capture the SoC actions needed
to be used as part of the verification
use cases can be used to automatically to create a desired use case, if not
process)
generate C tests that can be run natively already captured
and at speed on any of the verification • The challenge to emulate real-life
engines depicted in the figure. 2. Compose the desired use case
scenarios in synthetic testbenches
Today, the verification of electronic 3. Use the Perspec System Verifier to
C tests are typically created manually
systems (SoCs) and subsystems is solve the abstract use case to create
or by basic code generators, and lag
generally achieved using C tests. These concrete use cases or scenarios
far behind the UVM automation that
tests compliment the IP-level verification has become mainstream for hardware 4. The Perspec solution generates C tests
performed with UVM. There are several functional verification. The effort of test for the concrete scenario mapped to
reasons for the use of C tests, including: creation and maintenance, test reuse specific execution platform
that spans subsystems and systems, and
• A need to exercise system use cases 5. Run the tests on the targeted platform
leveraging these tests for future system
from a software programmer’s view
derivatives, are not addressed properly by 6. Debug the test and review coverage
• Enable portability across the Cadence manually creating C tests. results
Xcelium™ Parallel Simulator, Cadence
Furthermore, the overall flow—defining
Palladium® Z1 Platform, and Cadence
goals, automating stimuli creation,
Protium® S1 FPGA-Based Prototyping
launching tests to meet the goals, and
Platform (including post-silicon
collecting the results into a concise and
execution)
intuitive dashboard—are challenges for
productive system validation.

Soc Use
Case

Perspec

UVM/SV Amplified Amplified Amplified

or C Test C Test C Test C Test

Amplified Exploration of
Timing and State-Space

Xcelium Palladium Z1 Protium S1 Post-Silicon

Increased Capacity and

Execution Speed

Figure 2: Abstract Use Case >> Solver >> Concrete Solution

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 Perspec System Verifier

The Perspec solution supports the capture In addition, the coverage for the scenario the Xcelium, Palladium Z1, Protium S1,
of abstract models of system actions and is calculated when generated (gen-time and even post-silicon boards, and can also
resources by using System-Level Notation coverage) and can be compared with be automatically amplified to take full
(SLN) (Step 1). The abstract models actual execution results once tests are advantage of the faster platforms (Step
are visualized using Unified Modeling run (runtime coverage). In Figure 3, the 5). The C tests can also be generated to
Language (UML)-based graphical notation abstract scenario is shown on the left connect to an existing UVM environment
to simplify creation, modification, and use and a concrete solution, a UML activity for constrained random verification of IP
of complex use cases or scenarios (Step 2). diagram, is shown on the right. The solver and interface scenarios using the Xcelium
fills in everything needed to create an simulator.
The Perspec solution includes a constraint
executable scenario. The callouts identify
solver that generates concrete scenarios When the test runs, it generates a log
some of the choices made by the solver.
from user-directed, random-selection, that can be used to debug the test with
or coverage-driven fills of both data and From a concrete scenario, the Perspec Cadence’s Indago™ Debug Analyzer and
control flow from the abstract scenario solution automates the generation of a coverage results can be analyzed in the
and can show both legal and illegal C test that fulfills the scenario, including context of the verification plan using the
concrete scenarios based upon the rules the inter-processor communication and vManager™ Metric-Driven Signoff Platform
defined in the models (Step 3). multi-task scheduling required (Step 4). (Step 6).
The C tests can run natively at speed on

Using GUI, users can create sophisticated Randomize a way to get a video buffer
scenarios including timing, repetition, …

UML-Based
Scenario Scenario Activity Diagram
Specification Specification
(Goals) (Solution) Select random attributes:
• Convertible video format
• Accessible memory location

Solver: check feasibility

and randomize Data and
Control Flow
Lorem ipsum
Randomize video
stream attributes

Randomize a display
that can show the chosen
video format

Distribute available computing resources and sync as needed

Figure 3: Abstract Use Case >> Solver >> Concrete Solution

Connecting It Together processors are operating on different take advantage of use cases developed by
tasks and where you need to verify that domain experts and to create new, more
As shown above, the combination of
the cache coherency is maintained even complex SoC use cases by mixing use
abstract system actions with a constrained
when powering some of the processors cases.
random solver that can randomize both
on and off. Most customers today
control and data offers significant produc- Figure 4 highlights how the Perspec
avoid tackling the development of a
tivity improvement over manual creation solution not only makes it possible to
directed test for this type of complex use
of tests, but the real value is the ability to create the complex use case of mixing
case because of the level of expertise
capture complex SoC-level use cases that power shutdown and coherency, but
required in both coherency and power
would otherwise go unverified and to find as depicted allows other users to take
management and the complexity of the
bugs in the implementation that would advantage of use cases created by domain
software required to create this use case.
go undetected until the problem occurs in experts without needing to become a
Instead, they rely on their production
actual use. domain expert. In addition, the Perspec
software to validate these types of
solution automates the generation of the
To illustrate, let’s consider how to verify a complex use cases as best they can. With
complex C tests for any target platform.
use case where multiple cache coherent the Perspec solution, it is easy to

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 Perspec System Verifier

Scenario Tree View for Scenario Construction Pane for

Constructing/Editing Scenarios Scenario Specification and Editing

Solver output Scenario Node Details

An expanded scenario: Pane for Editing Actions,
constrained random Attributes, Constraints…
data and control flow
PSS Components and
Actions Pane

Scenario Source
Viewer Pane

Solved Scenarios Pane

Display of the Selected

Solved Scenario Instance

Figure 4: Creating SoC-Level Mixed Scenarios

Features • Methodology Library for learning best Coverage metric goals to ensure
practices to properly support reuse completeness
Use-Case Composer GUI and maintainability of the model and
• Supports both generation-time for
• Defines use cases in goal-oriented use-case scenarios
regression planning and runtime
terms using a UML-like GUI editor
Advanced constraint solver coverage
• Allows reviewing and sharing use cases
• Randomizes both system control flow • Collects functional coverage from
and system flows between teams
and data all verification engines including
• For advanced use cases: simulation, acceleration, emulation,
• Automatic memory management and
–– Enables composition of sub-scenarios FPGAs, and post-silicon
planning of legal resource distribution
to create advanced use cases and
• Includes explicit user-defined coverage
flows • Randomizes hard-to-achieve scenarios
goals and implicit exhaustive coverage
–– Scalable solution supports thousands and also spans multiple dimensions
definitions
of actions around them with fill capability
–– Allows definition of reusable flows • Delivers interval utility to enable
• Automatic amplification of use-case
for test construction coverage of hardware and software
state space and timing exploration for
–– Supports operators for random events, latency, and event shmooing
faster verification engines
scenario selection, generation-
• Plan-driven approach enables the
time repetition/filling and run-time Multi-core microkernel
user to select the desired verification
repetition (for long tests).
• Allows runtime synchronization of plan goal and the tool generates an
Libraries multiple heterogeneous cores and optimized set of tests to fill it in
parallel testbench activities
• System Modeling Library with building Checking
blocks for modeling common system • Emulates multi-threading on single
• Enables both runtime and post
components thread cores
simulation checking
• SoC Library for modeling and creating • Dynamic runtime management of
• Allows creation of assertions involving
scenarios to verify sophisticated resources to enable efficient and
both hardware and software events
multi-core CPU subsystems including concise tests
around latency, expected value
cache coherency, DVM, and low-power
• Exports messages from comparison, and end-to-end tests
modes
embedded cores

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 Perspec System Verifier

Model debug capabilities The Perspec solution can generate tests uniform management and analysis of
that drive UVM simulation tests in the the coverage resulting from the C tests
• Interactive GUI debugging of model
VIP for coverage driven verification. The executed. The vManager Metric-Driven
contradictions, UML graphs, solver
Perspec solution can also use the same Signoff Platform can display both the
operation, and C test generation
portable stimulus to generate tests for calculated coverage created at the
• Supports automatic synchronization of acceleration with accelerated Verification IP. time of test generation and the end
C test message log, UML-based graph coverage based upon results from the
nodes, and waveform transactions Related Products test execution. The coverage can also be
merged with HDL, HVL, and assertion-
• Supports adding messages, abstract Indago Debug Platform based coverage. As with debug, the
transactions, and waveforms based on
The Perspec System Verifier’s automated logging of the coverage points in the
events and intervals
C tests are generated to include built-in Perspec System Verifier is embedded in
logging information. This information the C tests and can be post-processed to
Verification Engines show the results from the test.
can be viewed using the Cadence Indago
Debug Platform, which provides post-
Out-of-the-box test generation and Cadence Services and Support
process debug from any platform used
execution support for using Cadence
to execute the tests. In addition, the
verification engines: • Cadence application engineers can
post-process debug uses the same UML
answer your technical questions by
• Xcelium Parallel Logic Simulator activity diagram to provide the same
telephone, email, or Internet—they can
use-case-focused debug perspective that
• Palladium Z1 Enterprise Emulation also provide technical assistance and
the Perspec System Verifier uses to speed
Platform custom training.
creation of use cases.
• Protium S1 FPGA-Based Prototyping • Cadence-certified instructors teach
Perspec supports the ability to include
Platform more than 70 courses and bring
embedded software in the design under
their real-world experience into the
test, and generate tests that drive the
VIP classroom.
API of that layer of software. The Indago
The Cadence Verification IP (VIP) Catalog Embedded Software Debugger provides • More than 25 Internet Learning
can be used for UVM simulation of IP additional, complementary debug support Series (iLS) online courses allow you
interface protocols, as well as accel- such as software variable and register the exibility of training at your own
erated VIP for SoC verification and tracing. computer via the Internet.
system emulation. Many VIP for UVM • Cadence Online Support gives you 24x7
vManager Metric-Driven Signoff
are available with C cores for fast online access to a knowledgebase of
Platform
execution and portability, and come with the latest solutions, technical documen-
the TripleCheck™ tool, which includes Cadence’s vManager Metric-Driven tation, software downloads, and more.
an extensive library of test sequences, Signoff Platform enables a plan-driven
a coverage model for tracking and approach for SoC verification. The user • For more information, please visit
measuring verification progress, and a can select a section in the hierarchical www.cadence.com/support for support
verification plan that mirrors the protocol verification plan and call the Perspec and www.cadence.com/training for
specification. System Verifier to create an optimized training.
subset of tests that will address the
sub-section goals. The Perspec System
Verifier is also integrated to provide

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to create the innovative end products that are transforming the way people live, work, and play. The
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chips to boards to intelligent systems. www.cadence.com
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