ST JOSEPH ENGINEERING COLLEGE, MANGALURU

An Autonomous Institution
Third Semester B.E. Degree (Autonomous) Examinations

USN: Course Code: 21CSE303

Duration: 3 Hrs Maximum Marks: 100

Digital Principles and Design(Integrated)
Note:
1. Part-A is mandatory.
2. Answer any five full questions from Part-B choosing at least one from each module.
3. Missing data may be suitably assumed.
PART-A
Q.No. Question BL CO PO Marks
1 Give Verilog Structural code for the circuit given below 2M

2 What is the Boolean expression for the output of the figure given below. 2M

3 Solve S(A,B,C,D)=∑ m(1,2,3,6,8,9,10,12,13,14) 2M

4 Design Verilog code for 2:1 mux using behavioral model 2M
5 Realize Y=A’B+B’C’+ABC using an 8-to-1multiplexer 2M
6 Show how to convert R’S’ flipflop into an RS flip flop 2M
7 The universal gate is ……………… 2M

NAND gate
OR gate
AND gate
None of the above

8 A device which converts BCD to seven segments is called …….. 2M

Encoder
Decoder
Multiplexer
None of these

9 A decade counter skips ……….. 2M

binary states 1000 to 1111

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Q.No. Question BL CO PO Marks

binary states 0000 to 0011

binary states 1010 to 1111
binary states 1111 to higher

10 BCD input 1000 is fed to a 7 segment display through a BCD to 7 2M

segment decoder/driver. The segments which will lit up are ………….

a, b, d
a, b, c
all
a, b, g, c, d

PART-B
Module-1
1 a) What is positive and Negative logic? List the equivalences in L2 1 PO1 8M
positive and negative logic.
b) Realize the basic gates using NAND gates and prove that, A(A' + L3 1 PO2 4M
C) (A'B + C) (A'BC + C') = 0
c) Consider this function F(A,B)=AB’+AB. Apply the duality L3 1 PO2 4M
Theorem and obtain its Dual.
OR
2 a) Draw the logic circuit for Y=AB’C+ABC. Simplify the equation L3 1 PO2 8M
with Boolean algebra anddraw the simplified logic circuit.
b) Realize the basic gates using NOR gates and Simplify, Y= (A+ B) L3 1 PO2 4M
(A'(B' + C'))' + A'(B + C)
c) Explain De-Morgan first and second theorem L2 1 PO1 4M
Module-2
3 a) Simplify the following using Q-M Method. L3 2 PO2 6M
F(A,B,C,D)= ∑ m(1, 3, 4, 5, 6, 7, 10, 12, 13)+ ∑ d(2, 9, 15)
b) Plot the following function on a K-Map and find the minimum L3 2 PO2 6M
SOP and POS solution.
F(A,B,C,D)= BD’ + B’CD + ABC + ABC’D + B’D’
c) What is a hazard? Explain the different types of hazards with an L3 2 PO1 4M
example?
OR
4 a) Simplify the following using Q-M Method. L3 2 PO2 6M
F(W,X,Y,Z)= ∑ m(0,1, 4, 6, 8,9, 10, 12)+ ∑ d(5, 7, 14)
b) Using the map-entered variable, use 4 variable maps to find all L3 2 PO2 6M
minimum SOP expressionfor the function
G(A,B,C,D,E,F)=m0+m2+m3+m5+m7+m9+m11+m15+d(1,10,13
)
c) Write the Verilog structural code the circuit given below 2 PO2 4M

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Q.No. Question BL CO PO Marks

Module-3
5 a) Implement the following boolean functions using an appropriate L3 3 PO2
PLA 6M
F1(a,b,c)=Σm(0,4,7)
F2(a,b,c)=Σm(4,6)
b) Design Hexadecimal(binary) to ASCII code Converter using L3 3 PO2
suitable ROM. Give the connection Diagram of ROM 6M

c) Implement the following using 3:8 decoder L3 3 PO2

F1 (A, B, C) = Σm(O, 4, 6); F2(A, B, C) = Σm(O, 5); F3(A, B, C) 4M
= Σm(l, 2, 3, 7)
OR
6 a) Realize a full Adder using PAL L3 3 PO2 6M
b) Implement full subtractor using 3 to 8 decoder and NAND gates L3 3 PO2 6M
c) Implement the given Boolean function using 8:1 MUX. L3 3 PO2 4M
Y=f(a,b,c,d) = Σm(0,1,3,5,11,12,13,14)
Module-4
7 a) Explain master slave JK flipflop Operations. L2 4 8M
b) Explain D flipflop with timing diagram L2 4 4M
c) Explain Edge triggered RS Flip flop L2 4 4M

OR
8 a) Construct SR gates latch using NAND gates and derive the L2 4 PO1, 8M
characteristics equation for the same. PO2
b) With necessary diagrams, Explain switch debouncing with an S-R L2 4 PO1 4M
latch.
c) Derive the characteristics of JK flipflop L2 4 PO1 4M
Module-5
9 a) With the help of state diagram and state and transition table and L3 4 PO2, 6M
timing diagram explain sequential parity checker PO1
b) Design a Mod-5 binary counter with its waveform and Truth Table L3 4 PO2 6M
c) Write a note on Johnson tail Counter L2 4 PO1 4M

OR
10 a) With the neat sketch, explain the working principle of SISO(Serial L3 4 PO2 6M

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Q.No. Question BL CO PO Marks

In Serial Out) shift register

b) Analyze the following Moore sequential circuit for an input L4 6 PO2 6M
Sequence X=01101 and draw the timing diagram

c) Write Verilog code for switched tail counter L3 5 PO2 4M

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