MCQ - Embedded Systems

1.
ARM stands for _____________

a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines
2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
3. The ARM processors don’t support Byte addressability.
a) True
b) False
4. The address space in ARM is ___________
a) 224
b) 264
c) 216
d) 232
5. The address system supported by ARM systems is/are ___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
6. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
7. In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
8. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned
9. Each instruction in ARM machines is encoded into __________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
10. The instructions which are used to load or store multiple operands are called as
__________
a) Banked instructions
b) Lump transfer instructions
c) Block transfer instructions
d) DMA instructions
11. The instruction, MLA R0,R1,R2,R3 performs _________
a) R0<-[R1]+[R2]+[R3]
b) R3<-[R0]+[R1]+[R2]
c) R0<-[R1]*[R2]+[R3]
d) R3<-[R0]*[R1]+[R2]
12. The ability to shift or rotate in the same instruction along with other operation is performed
with the help of _________
a) Switching circuit
b) Barrel switcher circuit
c) Integrated Switching circuit
d) Multiplexer circuit
13. _________ instruction is used to get the 1’s complement of the operand.
a) COMP
b) BIC
c) ~CMP
d) MVN
14. The BEQ instructions is used ____________
a) To check the equality condition between the operands and then branch
b) To check if the Operand is greater than the condition value and then branch
c) To check if the flag Z is set to 1 and then causes branch
d) None of the mentioned
15. The condition to check whether the branch should happen or not is given by ____________
a) The lower order 8 bits of the instruction
b) The higher order 4 bits of the instruction
c) The lower order 4 bits of the instruction
d) The higher order 8 bits of the instruction
16. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
17. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
18. In the process of pipelining, which instructions are fetched from the memory by the ARM
processor during the execution of current instruction?
a. Previous
b. Present
c. Next
d. All of the above
19. Abort mode generally enters when _______

a. an attempt access memory fails
b. low priority interrupt is raised
c. ARM processor is on rest
d. undefined instructions are to be handled
19. Which type of non-privileged processor mode is entered due to raising of high priority of
an interrupt?
a. User mode
b. Fast Interrupt Mode (FIQ)
c. Interrupt Mode (IRQ)
d. Supervisor Mode (SVC)
20. While designing an embedded system, which sub-task oriented process allocates the time
steps for various modules that share the similar resources?
a.Simulation and Validation

b. Iteration
c. Hardware-Software Partitioning
d. Scheduling
21. In LPC 2148, which among the following is/are the functions of Mask register?
a. Byte addressability
b. Relocation to ARM local bus for fastest posible I/O timing
c. Treating sets of port bits in the form of group without changing other bits
d. All of the above
22. In the branch instructions of ARM, what does the mnemonic BVC imply?
a. Overflow Set
b. Carry Set
c. Carry Clear
d. Overflow Clear
23. Which types of an embedded systems involve the coding at a simple level in an
embedded ‘C’, without any necessity of RTOS?
a. Small Scale Embedded Systems
b. Medium Scale Embedded Systems
c. Sophisticated Embedded Systems
d. All of the above
24. In DC motor interfacing, which modulation controls the duty cycle of square wave
provided at the output by generating variation in the average DC voltage?
a. Amplitude Modulation
b. Frequency Modulation
c. Pulse Width Modulation
d. Phase Modulation
25. ___ Register is used as the stack pointer.

a) r13
b) r14
c) r15
d) r16
26. ____ register is called the link register.
a) r13
b) r14
c) r15
d) r16
27. Privileged mode allows ___ access .
a) read
b) write
c) both
d) none
28. Non Privileged mode allows ___ access .
a) read
b) write
c) both
d) none
29. In ARM consists of ______ processor mode.
a) 7
b) 5
c) 4
d) 6
30. How many bank registers are available in ARM?
a) 20
b) 25
c) 30
d) 40
31. The SPSR store the ___ mode of CPSR
a) Present
b) previous
c) both
d) none
32. ___ are used to stop specific interrupt.
a) Interrupt mask
b) Interrupt request
c) both
d) none
33. CPSR has ___ interrupt mask bits.
a)2
b) 5
c) 6
d) 4
34. THUMP instruction is related to ___ bit .
a) 32
b) 16
c) 8
d)64
35.ARM7TDMI has a total of ____ General Purpose registers .

a)31
b) 24
c)8
d)16
36. ___is provided to service data transfer or communication channel with low latency.
a)IRQ
b) FIQ
c) SWI
d) None
37) _____ is used to make a call to an operating system.
a)IRQ
b) FIQ
c) SWI
d) None
39) The minimum latency for FIQ or IRQ interrupts is ___ cycle
a) 5
b) 10
c)15
d)20
40) The access time reading or writing a MMR depends on the___
a)AMBA
b)AMCA
c)AMDA
d)AMEA
41.ADC consists of a _____bit successive-approximation converter
a)12
b) 5
c) 16
d)24
42. )____Control Register allows the programmer to enable the ADC peripheral
a)ADCCON
b) ADCCP
c )ADCCN
d) none
43. LPC 2148 pro development board has _________ on chip memory.
a) 500k
b) 625k
c) 512k
d) 425k
44. Which LCD display is present in LPC 2148 Development Board?
a) 8*8 LED
b) 2*32 LCD
c) 2*16 LCD connected peripherally
d) 2*16 LCD on-chip
45. What are t, d, m, I stands for in ARM7TDMI?
a) Timer, Debug, Multiplex, ICE
b) Thumb, Debug, Multiplier, ICE
c) Timer, Debug, Modulation, IS
d) Thumb, Debug, Multiplier, ICE
46. What is the capability of ARMCortex M3 instruction for second?
a) 110 MIPS
b) 150 MIPS
c) 125 MIPS
d) 130 MIPS
47. Howmany registers are there in ARM Cortex M3?
a) 35 register( 28 GPR and 7 SPR)
b) 37 registers(28 GPR and 9 SPR)
c) 37 registers(31 GPR and 6 SPR)
d) 35 register(30 GPR and 5 SPR)
48. What is the instruction set used by ARM Cortex M3?
a) 16-bit instruction set
b) 32-bit instruction set
c) 64-bit instruction set

d) 8-bit instruction set

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1.

ARM stands for _____________

19. Abort mode generally enters when _______

a.Simulation and Validation

25. ___ Register is used as the stack pointer.

35.ARM7TDMI has a total of ____ General Purpose registers .

37) _____ is used to make a call to an operating system.

40) The access time reading or writing a MMR depends on the___

41.ADC consists of a _____bit successive-approximation converter

44. Which LCD display is present in LPC 2148 Development Board?

d) 2*16 LCD on-chip

45. What are t, d, m, I stands for in ARM7TDMI?

a) Timer, Debug, Multiplex, ICE

b) Thumb, Debug, Multiplier, ICE

c) Timer, Debug, Modulation, IS

d) Thumb, Debug, Multiplier, ICE

46. What is the capability of ARMCortex M3 instruction for second?

47. Howmany registers are there in ARM Cortex M3?

a) 35 register( 28 GPR and 7 SPR)

b) 37 registers(28 GPR and 9 SPR)

c) 37 registers(31 GPR and 6 SPR)

d) 35 register(30 GPR and 5 SPR)

48. What is the instruction set used by ARM Cortex M3?

a) 16-bit instruction set

b) 32-bit instruction set

c) 64-bit instruction set

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