SN74ALVCH162827

20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com SCES013H – JULY 1995 – REVISED AUGUST 2004

FEATURES DGG, DGV, OR DL PACKAGE

• Member of the Texas Instruments Widebus™ (TOP VIEW)
Family
• Output Ports Have Equivalent 26-Ω Series 1OE1 1 56 1OE2
Resistors, So No External Resistors Are 1Y1 2 55 1A1
Required 1Y2 3 54 1A2
• Bus Hold on Data Inputs Eliminates the Need GND 4 53 GND
for External Pullup/Pulldown Resistors 1Y3 5 52 1A3
1Y4 6 51 1A4
• Latch-Up Performance Exceeds 250 mA Per
VCC 7 50 VCC
JESD 17
1Y 8 49 1A5
• ESD Protection Exceeds JESD 22 1Y6 9 48 1A6
- 2000-V Human-Body Model (A114-A) 1Y7 10 47 1A7
- 200-V Machine Model (A115-A) GND 11 46 GND
- 1000-V Charged-Device Model (C101) 12
1Y8 45 1A8
1Y9 13 44 1A9
DESCRIPTION/ORDERING INFORMATION 1Y10 14 43 1A10
This 20-bit noninverting buffer/driver is designed for 2Y1 15 42 2A1
1.65-V to 3.6-V VCC operation. 2Y2 16 41 2A2
2Y3 17 40 2A3
The SN74ALVCH162827 is composed of two 10-bit
sections with separate output-enable signals. For GND 18 39 GND
either 10-bit buffer section, the two output-enable 2Y4 19 38 2A4
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must 2Y5 20 37 2A5
both be low for the corresponding Y outputs to be 2Y6 21 36 2A6
active. If either output-enable input is high, the VCC 22 35 VCC
outputs of that 10-bit buffer section are in the 2Y7 23 34 2A7
high-impedance state. 24 33
2Y8 2A8
The outputs, which are designed to sink up to 12 mA, GND 25 32 GND
include equivalent 26-Ω resistors to reduce overshoot 2Y9 26 31 2A9
and undershoot. 2Y10 27 30 2A10
To ensure the high-impedance state during power up 2OE1 28 29 2OE2
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.

ORDERING INFORMATION
TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVCH162827DL
SSOP - DL ALVCH162827
Tape and reel SN74ALVCH162827DLR
-40°C to 85°C
TSSOP - DGG Tape and reel SN74ALVCH162827GR ALVCH162827
TVSOP - DGV Tape and reel SN74ALVCH162827VR VH2827

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES013H – JULY 1995 – REVISED AUGUST 2004

FUNCTION TABLE
(each 10-bit section)
INPUTS OUTPUT
OE1 OE2 A Y
L L L L
L L H H
H X X Z
X H X Z

LOGIC DIAGRAM (POSITIVE LOGIC)

1 28
1OE1 2OE1
56 29
1OE2 2OE2

55 2 42 15
1A1 1Y1 2A1 2Y1

To Nine Other Channels To Nine Other Channels

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range -0.5 4.6 V
VI Input voltage range (2) -0.5 4.6 V
VO Output voltage range (2) (3) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 -50 mA
IOK Output clamp current VO < 0 -50 mA
IO Continuous output current ±50 mA
Continuous current through each VCC or GND ±100 mA
DGG package 64
θJA Package thermal impedance (4) DGV package 48 °C/W
DL package 56
Tstg Storage temperature range -65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

2
 SN74ALVCH162827
20-BIT BUFFER/DRIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES013H – JULY 1995 – REVISED AUGUST 2004

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
VCC Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 1.65 V -2
VCC = 2.3 V -6
IOH High-level output current mA
VCC = 2.7 V -8
VCC = 3 V -12
VCC = 1.65 V 2
VCC = 2.3 V 6
IOL Low-level output current mA
VCC = 2.7 V 8
VCC = 3 V 12
∆t/∆v Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature -40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES013H – JULY 1995 – REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = -100 µA 1.65 V to 3.6 V VCC - 0.2
IOH = -2 mA 1.65 V 1.2
IOH = -4 mA 2.3 V 1.9
VOH 2.3 V 1.7 V
IOH = -6 mA
3V 2.4
IOH = -8 mA 2.7 V 2
IOH = -12 mA 3V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
IOL = 4 mA 2.3 V 0.4
VOL 2.3 V 0.55 V
IOL = 6 mA
3V 0.55
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3V 0.8
II VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V -25
VI = 0.7 V 2.3 V 45
II(hold) VI = 1.7 V 2.3 V -45 µA
VI = 0.8 V 3V 75
VI = 2 V 3V -75
VI = 0 to 3.6 V (2) 3.6 V ±500
IOZ VO = VCC or GND 3.6 V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 40 µA
∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
Control inputs 3.5
Ci VI = VCC or GND 3.3 V pF
Data inputs 6
Co Outputs VO = VCC or GND 3.3 V 7 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.

4
 SN74ALVCH162827
20-BIT BUFFER/DRIVER
www.ti.com
WITH 3-STATE OUTPUTS
SCES013H – JULY 1995 – REVISED AUGUST 2004

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V VCC = 3.3 V
FROM TO VCC = 1.8 V VCC = 2.7 V
PARAMETER ± 0.2 V ± 0.3 V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX
tpd A Y (1) 1 4.4 4.4 1.5 3.8 ns
ten OE Y (1) 1.4 6.3 6.2 1.6 5.1 ns
tdis OE Y (1) 1.7 5.9 5.2 1.8 4.7 ns
tsk(LH) (2) (1) 0.5 0.5 0.5
A Y ns
tsk(HL) (2) (1) 0.5 0.5 0.5

(1) This information was not available at the time of publication.

(2) Parameter specified by design
tsk(LH) = |tPLH(m) - tPLH(n)|
tsk(HL) = |tPHL(m) - tPHL(n)|
where m and n are any arbitrary data bits.

OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP
Outputs enabled (1) 16 18
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz (1)
pF
Outputs disabled 4 6

(1) This information was not available at the time of publication.

5
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS www.ti.com
SCES013H – JULY 1995 – REVISED AUGUST 2004

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tpd Open
CL tPLZ/tPZL VLOAD
RL
(see Note A) tPHZ/tPZH GND

LOAD CIRCUIT

INPUT
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

tw
VI
VI Input VM VM
Timing
VM 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VI Output
Data VI
VM VM Control
Input VM VM
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VLOAD/2
VI Waveform 1
Input VM VM S1 at VLOAD VM VOL + V∆
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VOH
VOH
Waveform 2 VOH − V∆
Output VM VM VM
S1 at GND
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74ALVCH162827DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162827

SN74ALVCH162827DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162827

SN74ALVCH162827GR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162827

SN74ALVCH162827VR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VH2827

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALVCH162827DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
SN74ALVCH162827GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74ALVCH162827VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVCH162827DLR SSOP DL 56 1000 367.0 367.0 55.0
SN74ALVCH162827GR TSSOP DGG 56 2000 367.0 367.0 45.0
SN74ALVCH162827VR TVSOP DGV 56 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74ALVCH162827DL DL SSOP 56 20 473.7 14.24 5110 7.87

Pack Materials-Page 3
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
DGV0056A SCALE 1.500
TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.08 C SEATING
AREA 54X 0.4 PLANE
56
1

2X
11.4
10.8
11.2
NOTE 3

28
29
0.23
4.5 56X
B 0.13
4.3 0.1 C A B
NOTE 4

0.25
(0.15) TYP GAGE PLANE 1.2
1.1
SEE DETAIL A

0.75 0.15
0 -8 0.50 0.05

DETAIL A
A 15

TYPICAL

4220240/B 12/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-194.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGV0056A TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X
SYMM
(1.4)
56X (0.2) (R0.05) TYP
1
56

54X (0.4)

SYMM

28 29

(5.9)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL EDGE
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN
ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220240/B 12/2020
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGV0056A TVSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X
SYMM
(1.4)
56X (0.2) (R0.05) TYP
1
56

54X (0.4)

SYMM

28 29

(5.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

4220240/B 12/2020
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DGG0056A SCALE 1.200
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA 54X 0.5
56
1

14.1 2X
13.9 13.5
NOTE 3

28
29
0.27
6.2 56X 1.2 MAX
B 0.17
6.0
0.08 C A B

(0.15) TYP

0.25
SEE DETAIL A GAGE PLANE

0.15
0 -8 0.75 0.05
0.50

DETAIL A
TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05)
TYP
SYMM

28 29
(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05) TYP
SYMM

28 29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4222167/A 07/2015
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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