18-447

Computer Architecture
Lecture 17: Memory Hierarchy and Caches

Prof. Onur Mutlu

Carnegie Mellon University
Spring 2015, 2/25/2015
Assignment and Exam Reminders
n Lab 4: Due March 6
q Control flow and branch prediction

n Lab 5: Due March 22

q Data cache

n HW 4: March 18
n Exam: March 20

n Finish the labs early

n You have almost a month for Lab 5

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Announcements
n Please turn in your feedback form: Very Important

n No office hours (for me) today

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 IA-64: A “Complicated” VLIW ISA

Recommended reading:
Huck et al., “Introducing the IA-64 Architecture,” IEEE Micro 2000.
EPIC – Intel IA-64 Architecture
n Gets rid of lock-step execution of instructions within a VLIW
instruction
n Idea: More ISA support for static scheduling and parallelization
q Specify dependencies within and between VLIW instructions

(explicitly parallel)

+ No lock-step execution
+ Static reordering of stores and loads + dynamic checking
-- Hardware needs to perform dependency checking (albeit aided by
software)
-- Other disadvantages of VLIW still exist

n Huck et al., “Introducing the IA-64 Architecture,” IEEE Micro, Sep/Oct

2000.
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IA-64 Instructions
n IA-64 “Bundle” (~EPIC Instruction)
q Total of 128 bits
q Contains three IA-64 instructions
q Template bits in each bundle specify dependencies within a
bundle

n IA-64 Instruction
q Fixed-length 41 bits long
q Contains three 7-bit register specifiers
q Contains a 6-bit field for specifying one of the 64 one-bit
predicate registers
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IA-64 Instruction Bundles and Groups
n Groups of instructions can be
executed safely in parallel
q Marked by “stop bits”

n Bundles are for packaging

q Groups can span multiple bundles
n Alleviates recompilation need
somewhat

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Template Bits
n Specify two things
q Stop information: Boundary of independent instructions
q Functional unit information: Where should each instruction be routed

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Three Things That Hinder Static Scheduling
n Dynamic events (static unknowns)

n Branch direction
n Load hit miss status
n Memory address

n Let’s see how IA-64 ISA has support to aid scheduling in

the presence of statically-unknown load-store addresses

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Non-Faulting Loads and Exception Propagation in IA-64
n Idea: Support unsafe code motion
ld.s r1=[a]
inst 1 inst 1
inst 2 unsafe inst 2
…. code ….
motion br
br

…. ld r1=[a] …. chk.s r1 ld r1=[a]

use=r1 use=r1

n ld.s (speculative load) fetches speculatively from memory

i.e. any exception due to ld.s is suppressed
n If ld.s r1 did not cause an exception then chk.s r1 is a NOP, else a
branch is taken (to execute some compensation code)
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Non-Faulting Loads and Exception Propagation in IA-64
n Idea: Support unsafe code motion
q Load and its use ld.s r1=[a]
inst 1
inst 1 inst 2
inst 2 unsafe use=r1
…. code ….
br motion
br br

…. ld r1=[a] …. chk.s use ld r1=[a]

use=r1 use=r1

n Load data can be speculatively consumed (use) prior to check

n “speculation” status is propagated with speculated data
n Any instruction that uses a speculative result also becomes speculative
itself (i.e. suppressed exceptions)
n chk.s checks the entire dataflow sequence for exceptions
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Aggressive ST-LD Reordering in IA-64
n Idea: Reorder LD/STs in the presence of unknown address
inst 1 ld.a r1=[x]
potential
inst 2 inst 1
aliasing
…. inst 2
st [?]
st[?] ….
…. st [?]
ld r1=[x] ….
use=r1 ld.c r1=[x]
use=r1

n ld.a (advanced load) starts the monitoring of any store to the same
address as the advanced load
n If no aliasing has occurred since ld.a, ld.c is a NOP
n If aliasing has occurred, ld.c re-loads from memory
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Aggressive ST-LD Reordering in IA-64
n Idea: Reorder LD/STs in the presence of unknown address
q Load and its use

inst 1 ld.a r1=[x]

potential
inst 2 inst 1
aliasing
…. inst 2
st [?]
st[?] use=r1
…. ….
ld r1=[x] st [?]
use=r1 ….
chk.a X ld r1=[a]
…. use=r1

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What We Covered So Far in 447
n ISA à Single-cycle Microarchitectures

n Multi-cycle and Microprogrammed Microarchitectures

n Pipelining

n Issues in Pipelining: Control & Data Dependence Handling,

State Maintenance and Recovery, …

n Out-of-Order Execution

n Issues in OoO Execution: Load-Store Handling, …

n Alternative Approaches to Instruction Level Parallelism

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Approaches to (Instruction-Level) Concurrency
n Pipelining
n Out-of-order execution
n Dataflow (at the ISA level)
n SIMD Processing (Vector and array processors, GPUs)
n VLIW
n Decoupled Access Execute
n Systolic Arrays

n Static Instruction Scheduling

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Agenda for the Rest of 447
n The memory hierarchy
n Caches, caches, more caches (high locality, high bandwidth)
n Virtualizing the memory hierarchy
n Main memory: DRAM
n Main memory control, scheduling
n Memory latency tolerance techniques
n Non-volatile memory

n Multiprocessors
n Coherence and consistency
n Interconnection networks
n Multi-core issues
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Readings for Today and Next Lecture
n Memory Hierarchy and Caches

n Cache chapters from P&H: 5.1-5.3

n Memory/cache chapters from Hamacher+: 8.1-8.7
n An early cache paper by Maurice Wilkes
q Wilkes, “Slave Memories and Dynamic Storage Allocation,”
IEEE Trans. On Electronic Computers, 1965.

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Memory (Programmer’s View)

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Abstraction: Virtual vs. Physical Memory
n Programmer sees virtual memory
q Can assume the memory is “infinite”
n Reality: Physical memory size is much smaller than what
the programmer assumes
n The system (system software + hardware, cooperatively)
maps virtual memory addresses are to physical memory
q The system automatically manages the physical memory
space transparently to the programmer

+ Programmer does not need to know the physical size of memory

nor manage it à A small physical memory can appear as a huge
one to the programmer à Life is easier for the programmer
-- More complex system software and architecture

A classic example of the programmer/(micro)architect tradeoff

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(Physical) Memory System
n You need a larger level of storage to manage a small
amount of physical memory automatically
à Physical memory has a backing store: disk

n We will first start with the physical memory system

n For now, ignore the virtualàphysical indirection

q As you have been doing in labs

n We will get back to it when the needs of virtual memory

start complicating the design of physical memory…

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Idealism

Pipeline
Instruction (Instruction Data
Supply Supply
execution)

- Zero-cycle latency - No pipeline stalls - Zero-cycle latency

- Infinite capacity -Perfect data flow - Infinite capacity

(reg/memory dependencies)
- Zero cost - Infinite bandwidth
- Zero-cycle interconnect
- Perfect control flow (operand communication) - Zero cost

- Enough functional units

- Zero latency compute

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The Memory Hierarchy
 23

DRAM BANKS
Memory in a Modern System

DRAM INTERFACE
DRAM MEMORY
CORE 1

CORE 3
CONTROLLER

L2 CACHE 1 L2 CACHE 3
L2 CACHE 0 L2 CACHE 2

CORE 2
CORE 0
SHARED L3 CACHE
Ideal Memory
n Zero access time (latency)
n Infinite capacity
n Zero cost
n Infinite bandwidth (to support multiple accesses in parallel)

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The Problem
n Ideal memory’s requirements oppose each other

n Bigger is slower
q Bigger à Takes longer to determine the location

n Faster is more expensive

q Memory technology: SRAM vs. DRAM vs. Disk vs. Tape

n Higher bandwidth is more expensive

q Need more banks, more ports, higher frequency, or faster
technology

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Memory Technology: DRAM
n Dynamic random access memory
n Capacitor charge state indicates stored value
q Whether the capacitor is charged or discharged indicates
storage of 1 or 0
q 1 capacitor
q 1 access transistor

row enable
n Capacitor leaks through the RC path
q DRAM cell loses charge over time

_bitline
q DRAM cell needs to be refreshed

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Memory Technology: SRAM
n Static random access memory
n Two cross coupled inverters store a single bit
q Feedback path enables the stored value to persist in the “cell”
q 4 transistors for storage
q 2 transistors for access

row select

_bitline
bitline

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Memory Bank Organization and Operation
n Read access sequence:

1. Decode row address

& drive word-lines

2. Selected bits drive

bit-lines
• Entire row read

3. Amplify row data

4. Decode column
address & select subset
of row
• Send to output

5. Precharge bit-lines
• For next access

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SRAM (Static Random Access Memory)
Read Sequence
row select 1. address decode
2. drive row select
3. selected bit-cells drive bitlines

_bitline
bitline

(entire row is read together)

4. differential sensing and column select
(data is ready)
5. precharge all bitlines
(for next read or write)
bit-cell array
n+m n 2n 2n row x 2m-col Access latency dominated by steps 2 and 3
Cycling time dominated by steps 2, 3 and 5
(n≈m to minimize
overall latency) - step 2 proportional to 2m
- step 3 and 5 proportional to 2n
m 2m diff pairs
sense amp and mux
1
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DRAM (Dynamic Random Access Memory)
row enable Bits stored as charges on node
capacitance (non-restorative)
bit cell loses charge when read
_bitline

- bit cell loses charge over time

Read Sequence
1~3 same as SRAM
4. a “flip-flopping” sense amp
RAS
bit-cell array amplifies and regenerates the
bitline, data bit is mux’ed out
n 2n 2n row x 2m-col 5. precharge all bitlines
(n≈m to minimize
overall latency) Destructive reads
Charge loss over time
m 2m
sense amp and mux Refresh: A DRAM controller must
1 periodically read each row within
A DRAM die comprises the allowed refresh time (10s of
CAS of multiple such arrays ms) such that charge is restored
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DRAM vs. SRAM
n DRAM
q Slower access (capacitor)
q Higher density (1T 1C cell)
q Lower cost
q Requires refresh (power, performance, circuitry)
q Manufacturing requires putting capacitor and logic together

n SRAM
q Faster access (no capacitor)
q Lower density (6T cell)
q Higher cost
q No need for refresh
q Manufacturing compatible with logic process (no capacitor)
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The Problem
n Bigger is slower
q SRAM, 512 Bytes, sub-nanosec
q SRAM, KByte~MByte, ~nanosec
q DRAM, Gigabyte, ~50 nanosec
q Hard Disk, Terabyte, ~10 millisec

n Faster is more expensive (dollars and chip area)

q SRAM, < 10$ per Megabyte
q DRAM, < 1$ per Megabyte
q Hard Disk < 1$ per Gigabyte
q These sample values scale with time

n Other technologies have their place as well

q Flash memory, PC-RAM, MRAM, RRAM (not mature yet)
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Why Memory Hierarchy?
n We want both fast and large

n But we cannot achieve both with a single level of memory

n Idea: Have multiple levels of storage (progressively bigger

and slower as the levels are farther from the processor)
and ensure most of the data the processor needs is kept in
the fast(er) level(s)

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The Memory Hierarchy

move  what  you  use  here   fast  

small  

With  good  locality  of  

reference,  memory  

cheaper  per  byte  

appears  as  fast  as  

faster  per  byte  

and  as  large  as      

backup  
everything   big  but  slow  
here  
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Memory Hierarchy
n Fundamental tradeoff
q Fast memory: small
q Large memory: slow
n Idea: Memory hierarchy

Hard Disk
Main
CPU Cache Memory
RF (DRAM)

n Latency, cost, size,

bandwidth

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Locality
n One’s recent past is a very good predictor of his/her near
future.

n Temporal Locality: If you just did something, it is very

likely that you will do the same thing again soon
q since you are here today, there is a good chance you will be
here again and again regularly

n Spatial Locality: If you did something, it is very likely you

will do something similar/related (in space)
q every time I find you in this room, you are probably sitting
close to the same people

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Memory Locality
n A “typical” program has a lot of locality in memory
references
q typical programs are composed of “loops”

n Temporal: A program tends to reference the same memory

location many times and all within a small window of time

n Spatial: A program tends to reference a cluster of memory

locations at a time
q most notable examples:
n 1. instruction memory references
n 2. array/data structure references

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Caching Basics: Exploit Temporal Locality
n Idea: Store recently accessed data in automatically
managed fast memory (called cache)
n Anticipation: the data will be accessed again soon

n Temporal locality principle

q Recently accessed data will be again accessed in the near
future
q This is what Maurice Wilkes had in mind:
n Wilkes, “Slave Memories and Dynamic Storage Allocation,” IEEE
Trans. On Electronic Computers, 1965.
n “The use is discussed of a fast core memory of, say 32000 words
as a slave to a slower core memory of, say, one million words in
such a way that in practical cases the effective access time is
nearer that of the fast memory than that of the slow memory.”

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Caching Basics: Exploit Spatial Locality
n Idea: Store addresses adjacent to the recently accessed
one in automatically managed fast memory
q Logically divide memory into equal size blocks
q Fetch to cache the accessed block in its entirety
n Anticipation: nearby data will be accessed soon

n Spatial locality principle

q Nearby data in memory will be accessed in the near future
n E.g., sequential instruction access, array traversal
q This is what IBM 360/85 implemented
n 16 Kbyte cache with 64 byte blocks
n Liptay, “Structural aspects of the System/360 Model 85 II: the
cache,” IBM Systems Journal, 1968.

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The Bookshelf Analogy
n Book in your hand
n Desk
n Bookshelf
n Boxes at home
n Boxes in storage

n Recently-used books tend to stay on desk

q Comp Arch books, books for classes you are currently taking
q Until the desk gets full
n Adjacent books in the shelf needed around the same time
q If I have organized/categorized my books well in the shelf

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Caching in a Pipelined Design
n The cache needs to be tightly integrated into the pipeline
q Ideally, access in 1-cycle so that dependent operations do not
stall
n High frequency pipeline à Cannot make the cache large
q But, we want a large cache AND a pipelined design
n Idea: Cache hierarchy

Main
Level 2 Memory
CPU Level1 Cache (DRAM)
RF Cache

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A Note on Manual vs. Automatic Management
n Manual: Programmer manages data movement across levels
-- too painful for programmers on substantial programs
q “core” vs “drum” memory in the 50’s

q still done in some embedded processors (on-chip scratch pad

SRAM in lieu of a cache)

n Automatic: Hardware manages data movement across levels,

transparently to the programmer
++ programmer’s life is easier
q the average programmer doesn’t need to know about it

n You don’t need to know how big the cache is and how it works to
write a “correct” program! (What if you want a “fast” program?)

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Automatic Management in Memory Hierarchy
n Wilkes, “Slave Memories and Dynamic Storage Allocation,”
IEEE Trans. On Electronic Computers, 1965.

n “By a slave memory I mean one which automatically

accumulates to itself words that come from a slower main
memory, and keeps them available for subsequent use
without it being necessary for the penalty of main memory
access to be incurred again.”
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 A Modern Memory Hierarchy
Register  File  
32  words,  sub-­‐nsec  
  manual/compiler  
Memory     register  spilling  
L1  cache  
AbstracOon   ~32  KB,  ~nsec  
 
 
L2  cache  
512  KB  ~  1MB,  many  nsec   AutomaOc  
  HW  cache  
 
L3  cache,     management  
.....  
 
 
Main  memory  (DRAM),    
GB,  ~100  nsec  
  automaOc  
 
Swap  Disk  
demand    
100  GB,  ~10  msec   paging  
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Hierarchical Latency Analysis
n For a given memory hierarchy level i it has a technology-intrinsic
access time of ti, The perceived access time Ti is longer than ti
n Except for the outer-most hierarchy, when looking for a given
address there is
q a chance (hit-rate hi) you “hit” and access time is ti

q a chance (miss-rate mi) you “miss” and access time ti +Ti+1

q hi + mi = 1

n Thus
Ti = hi·ti + mi·(ti + Ti+1)
Ti = ti + mi ·Ti+1

hi and mi are defined to be the hit-rate

and miss-rate of just the references that missed at Li-1
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Hierarchy Design Considerations
n Recursive latency equation
Ti = ti + mi ·Ti+1
n The goal: achieve desired T1 within allowed cost
n Ti ≈ ti is desirable

n Keep mi low
q increasing capacity Ci lowers mi, but beware of increasing ti
q lower mi by smarter management (replacement::anticipate what you
don’t need, prefetching::anticipate what you will need)

n Keep Ti+1 low

q faster lower hierarchies, but beware of increasing cost
q introduce intermediate hierarchies as a compromise
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Intel Pentium 4 Example
n 90nm P4, 3.6 GHz
n L1 D-cache if m1=0.1, m2=0.1
T1=7.6, T2=36
q C1 = 16K
q t1 = 4 cyc int / 9 cycle fp if m1=0.01, m2=0.01
n L2 D-cache T1=4.2, T2=19.8
q C2 =1024 KB if m1=0.05, m2=0.01
q t2 = 18 cyc int / 18 cyc fp T1=5.00, T2=19.8
n Main memory if m1=0.01, m2=0.50
q t3 = ~ 50ns or 180 cyc T1=5.08, T2=108
n Notice
q best case latency is not 1
q worst case access latencies are into 500+ cycles
Cache Basics and Operation
Cache
n Generically, any structure that “memoizes” frequently used
results to avoid repeating the long-latency operations
required to reproduce the results from scratch, e.g. a web
cache

n Most commonly in the on-die context: an automatically-

managed memory hierarchy based on SRAM
q memoize in SRAM the most frequently accessed DRAM
memory locations to avoid repeatedly paying for the DRAM
access latency

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Caching Basics
n Block (line): Unit of storage in the cache
q Memory is logically divided into cache blocks that map to
locations in the cache

n When data referenced

q HIT: If in cache, use cached data instead of accessing memory
q MISS: If not in cache, bring block into cache
n Maybe have to kick something else out to do it

n Some important cache design decisions

q Placement: where and how to place/find a block in cache?
q Replacement: what data to remove to make room in cache?
q Granularity of management: large, small, uniform blocks?
q Write policy: what do we do about writes?
q Instructions/data: Do we treat them separately?
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Cache Abstraction and Metrics

Address
Tag Store Data Store

(is the address

in the cache?
+ bookkeeping)

Hit/miss? Data

n Cache hit rate = (# hits) / (# hits + # misses) = (# hits) / (# accesses)

n Average memory access time (AMAT)
= ( hit-rate * hit-latency ) + ( miss-rate * miss-latency )
n Aside: Can reducing AMAT reduce performance?
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