Forever For

module clock (); module

waveforms ();
[3: 0] C;
reg clock; leg
i;
initial
begin integes
clock initial begins
=
0;
clock=! dock; C 0;
jouver #5
=

end Jot (i 0; i < 16;i i 1) begin

= +
=

initial
begin #5c ij
=

50$ stop;
#

end
end #5$ stop;
endwodule erch
endwodule

Monitor
wonitor ("Sennatul
$ b %3d
=
eat =%3d, b, $time);

↓I
m.
digiti decimal (baza (0)
b binar
-

--> hexa

Porti logice
⑪ Descriele STRUCTURAL 2. Descriere FUNCTIONALA
module
porti-logice( module
porti-logical
imput a, b, c, imput a, b, c,
output y); output yI;

Wise W; assign y=!(a2b)1c;

hand module
pr(w,a,b); end

or
PC/y, w, C;
end module

a Sow I

C
 Multiplexor
module MUX(
imput imo, in 1, 5,
out);
output
assign out=s? In 1:ino;

endwodute

module (parameter n =
3, N 6)
=

multipaxos -N-to-1(
input [n-1,0] sel,
imput [X-1,0] in,
output y I;
im[sel];
assign y
=

endwodut

module multiplexor -2-to-1 (

imput [1:0] sel,
imput
[3:0] in,
outputleg y);
always & (*)
case (sell

y in[O];
0: =

y= [1];
1: in

y in[e];
2: =

3:
y
=
in [3];
im[o];
default: y
=

endcase
endwodul
 Sumator
module sumatol)

imput [b: o] imo, in 1,

inputcin,
output
[3:0] out,
output cout);

assigns cout, out 3: imo+ instein;

endwodule

Comparator
module comparator (
input
[2:0] a, b,
output leg I, g, h);

atways & (*) begin

if(acb)
98,9,43 3b100;
=

else if (a =
=
b)

95,9,23=3'b010;

elsg, g, h3=3bool;
end
endwodule
 Transcodor
module team scodol
I impet
[3:0] ire,
output (7:0] out,
reg
output[0:o] auod);
anod=4'b1101;
assign
always& (X)
case (im)
4b0000:out= 8'b1100-0000;
↳booor:out:8'b1111_1001;
↳boolo:out:8'b1010-0100;
↳bool:out=8'b1011-0000;
↳'b0100:out=8'b1001-1001;
↳ b0101:out=8'b1001-0010;

<'b0110:out=8'b 1000-0010;
↳' b 0111:out=8b 1111-1000;
↳'b1000:out=8'b1000-0000;
s'b1001:out=8b1001-0000;

default:out=8'b 1911-1911;

endease

endwodute

0 - APRINS
I gb 1 - STiNs

e C
·

h hgfe_deba
d
 Demultiplexor
module DMUX( sel out
imput en, 00 000em
input[2:0] sel,
or oven o
output[7: 0] out);
10 o en oo

assign out:en sel; 11 eno00

endwodule

Decodor
module decodol module decoder
<imput [1:0] in, c input
[1:0] in,
leg [3:o] out);
output output [3:0] out);
always & (*) out: ib im;
case (in)
assign
endwodule
0: out=4'booor;
1:out: 4'b0010;
2: out=4'b0100;
im out
3:out=4'b1000;

default: out=4'b000; 00 0001

endcase Of 0010

endwodue 10 0100
11 1000
 Priority Encoder
module PE (
im out zero
imput [3:0] im,
output reg [1: o] out, oool 00 0

ooX 01 0
output reg zeco);
0IXX 10 0

always & (*)

1XXX 11 O
casex (in) 0000 00 1

↳'b1:
beginn
out=2'bo0;
zero: I'b0;
end

↳'bix: begin
out=2'bor;
zelo=1'bo;
end

4 b1xX: beginn
out=2'b 10;
zero=1'bo;
end

4b1xxX: begin
out: 2'b11;
zero=1'bo;
end

s'bo: begin
out= 2'bo0;
zelo=l'b1;
end
endease
endwodute
 Numarator
module numatol (

imput ck, reset, load, e, u.d,

output reg [2:0] out,
imput [2: 0] dim);

always &
(posedgeck)
casex) reset, load, en3
3'b1xx:out<=0;
3'bolx:out <= dim;
3'bool: (M-d)
if
out <= out+ 1;
else
out<=out-1;

default: out<- out;

endcase
endwodute

Divizor
module divizob(
imput
CK,
outputout);

leg [31:0] numar;

always 8
(posedgeck)
numr<= numar+1;

out: numan [26];

assign
endwodul
 Latch elementar >
L
activ pe 0

S R

module catch (
H U
imput
Ms, mR,
output na, Q);
mand #3 p. (ma,ms,a);
namd #3
Q Q
Pz (Q, m, mQ);
endwodute
S'R QQ Stale
10 0 I SET
01 10 RESET
11 QQ MEMORARE
00 INTERES

Latch cu ceas Ck
S R

module Catch-ck(
imput 5,R, CK, W W
outputna, Q);
wile MS, mR; 3

S R
nand #3
pe (mQ, ns,a);
mand #3
nand #3
P2 (a, mR, ma); ~u
ps(Ms, 5, CK);
mand #3
p4 (mR, R, CK);
endwodule
Q Q
 D
Latch D R
S Ck

module latch_A(
imput D, CK,
output
rega); W W
always 8(*)
if((k 1)
=
=

Q D;
=

else 9 Q; =

~u
endwodute

Q Q

Bistabil
module bistable (
imput D, CK,
output Q);
Wile We, w2;

ail,
not p(w,ck) MASTER
Catch-AS, (
·
D(D),
·
s Q

CKICK),
·
Q(W2)]; CK

Catch-AS2(
·
A(W2),
·

Q(Q),
·
ck (Wi));

endwodule
 Memorie RAM
⑪ module RAM-Sincron (
imput [3:0] Dim,
imput[2:0] Ad,
imput We, CK,
output reg [3:0] Dout);
reg [3:0] meworie [0:7];
always & (posedgeck)
if (we)
meworie[Ade] EDim;- scriese were sinerona

always &
(posedge (k)
Dont <= weworie[Ad];-citire sinceona
endwodut

②wodule RAM asimcon (

imput [3:0] Dim,
imputwe, ck,
impet [2:0] Adl,
output [3:0] Dout);

reg [3:0] meworie [0: 7];

always & (posedgeck)
if (we)
mewoue [Adl] = Dim;
bont:meworie[Ade]; - citize asimcona
assign
endwodule
 Registru deplasare (serie)
module
register - serie

I impet sick,
outputso);
reg [3:0] 9;
always & (posedgeck) begin
q[3] = si;
953]
95235
q[1] = 9[2];
g[0] E g[n];
end

assign so=g[0];
endwodul

module register #(parameter n 4)

=

(impest ck, si,

output
so);
[m-1:0] 2;
leg
always & (posedge (K) begin
qc q 1;
=

q[m-1] = si;
end

assign so
g[0];
=

endwodule