At91 Arm Thumb Microcontrollers AT91C140: Features

Features
• ARM7TDMI® ARM® Thumb® Processor Core

– In-Circuit Emulator, 36 MHz Operation
• Ethernet Bridge
– Dual Ethernet 10/100 Mbps MAC Interface
– 16-Kbyte Frame Buffer
• 1 K-Byte Boot ROM, Embedding a Boot Program
– Enable Application Download from DataFlash®
• External Bus Interface
– On-chip 16-bit SDRAM Controller AT91 ARM®
Thumb®
– 4-Chip Select Static Memory Controller
• Multi-level Priority, Individually Maskable, Vectored Interrupt Controller
• Three 16-bit Timer/Counters
• Two UARTs with Modem Control Lines
Microcontrollers
• Serial Peripheral Interface (SPI)
• Two PIO Controllers, Managing up to 48 General-purpose I/O Pins
• Available in a 208-lead PQFP Package AT91C140
• Power Supplies
– VDDIO 3.3V nominal
– VDDCORE and VDDOSC 1.8V nominal
• -40°C to + 85°C Operating Temperature Range
1. Description
The AT91C140 is a member of the Atmel AT91 16- and 32-bit microcontroller family
based on the ARM7TDMI processor core. This processor has a high performance
32-bit RISC architecture with a high density 16-bit instruction set and very low power
consumption.
In addition, the AT91C140 integrates a double Ethernet 10/100 base-T MAC capable
of operating as an Ethernet bridge, thus making it ideally suited for networking appli-
cations. It supports a wide range of memory devices such as SDRAM, SRAM and
Flash and embeds an extensive array of peripherals.
The device is manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI processor core with an expansive assortment of peripheral
functions and low-power oscillators and PLL on a monolithic chip, the Atmel
AT91C140 is a powerful microcontroller that provides a highly flexible and cost effec-
tive solution to many networking applications.
6069C–ATARM–15-Sep-05
2. Block Diagram
Figure 2-1. AT91C140 Block Diagram
JTAG Debug
Interface ICE
ARM7TDMI Processor
Boot ROM
External Bus
Interface
MII PHY Ethernet

ASB/ASB SDRAMC
Interface 10/100 Mbps
Bridge
MAC Interface
16-bit Data
Memory Bus
SMC
MII PHY Ethernet 32k Bytes
Interface 10/100 Mbps SRAM
MAC Interface
Peripheral Data
Controller
Peripheral Bridge
OSC
System Serial Peripherals
Controller SPI Boot DataFlash
PLL
Interrupt and Advanced USART A Serial Port

Fast Interrupt Interrupt
Controller
USART B Serial Port

I/O Lines PIO Controller A
Timer/Counter 0 PWM Signals
I/O Lines PIO Controller B

2 AT91C140
AT91C140
3. Pinout
Table 3-1. Pinout for 208-lead PQFP Package
Pin Pin Pin Pin
Number Signal Name Number Signal Name Number Signal Name Number Signal Name
1 GND 37 MB_TXD0 73 A15 109 RAS
2 GND 38 MB_TXD1 74 A16 110 CAS
3 VDDIO 39 MB_TXD2 75 A17 111 NC(1)
4 GND 40 GND 76 A18 112 WE
5 NC(1) 41 MB_TXD3 77 A19B/A0 113 DQM0
6 GND 42 MB_TXEN 78 A20/BA1 114 DQM1
7 NTRST 43 MB_TXCLK 79 A21 115 NC(1)
8 MA_COL 44 MB_RXD0 80 D0 116 GND
9 MA_CRS 45 MB_RXD1 81 D1 117 NC(1)
10 MA_TXER 46 MB_RXD2 82 D2 118 VDDCORE
11 MA_TXD0 47 MB_RXD3 83 D3 119 GND
12 MA_TXD1 48 MB_RXER 84 GND 120 VDDOSC
13 MA_TXD2 49 MB_RXCLK 85 D4 121 PLLRC
14 MA_TXD3 50 MB_RXDV 86 VDDIO 122 GND
15 MA_TXEN 51 MB_MDC 87 D5 123 GND

16 VDDIO 52 VDDIO 88 D6 124 XTALOUT
17 MA_TXCLK 53 GND 89 D7 125 XTALIN
18 GND 54 MB_MDIO 90 D8 126 VDDCORE
19 MA_RXD0 55 MB_LINK 91 D9 127 NCE0
20 MA_RXD1 56 A0 92 D10 128 NCE1
21 MA_RXD2 57 A1 93 D11 129 NCE2

22 MA_RXD3 58 A2 94 D12 130 VDDIO
23 MA_RXER 59 A3 95 D13 131 NCE3
24 MA_RXCLK 60 A4 96 D14 132 NWE0
25 GND 61 A5 97 VDDCORE 133 NWE1
26 VDDCORE 62 A6 98 GND 134 NC(1)
27 MA_RXDV 63 A7 99 D15 135 VDDIO
28 MA_MDC 64 A8 100 VDDIO 136 GND
29 MA_MDIO 65 A9 101 GND 137 NC(1)
30 MA_LINK 66 A10 102 VDDIO 138 NWR
31 MB_COL 67 A11 103 NC(1) 139 NSOE
32 MB_CRS 68 A12 104 VDDIO 140 GND
33 GND 69 VDDIO 105 GND 141 VDDCORE
34 VDDCORE 70 GND 106 SDCK 142 VDDIO
35 VDDIO 71 A13 107 SDCS 143 MISO
36 MB_TXER 72 A14 108 SDA10 144 MOSI
3
Table 3-1. Pinout for 208-lead PQFP Package (Continued)
Pin Pin Pin Pin
Number Signal Name Number Signal Name Number Signal Name Number Signal Name
145 SPCK 161 TMS 177 PA5 193 GND
146 PA22 162 TCK 178 PA4 194 PB0
147 VDDIO 163 PA19 179 PA3 195 PB1
148 GND 164 VDDCORE 180 PA2 196 PB2
149 NRST 165 GND 181 PA1 197 PB3
150 FIQ 166 PA12 182 PA0 198 PB4
151 IRQ0 167 GND 183 GND 199 PB5
152 TST 168 VDDIO 184 RXDA 200 PB6
153 GND 169 PA11 185 TXDA 201 PB7
154 VDDCORE 170 PA10 186 NRSTA 202 PB8

(1)
155 NC 171 PA9 187 NCTSA 203 PB9
156 VDDIO 172 PA8 188 NDTRA 204 VDDIO
157 GND 173 PA7 189 NDSRA 205 GND
158 VDDIO 174 PA6 190 NDCDA 206 GND
159 TDO 175 VDDIO 191 RXDB 207 GND

(1)
160 TDI 176 NC 192 TXDB 208 VDDIO
Note: 1. NC leads should be left unconnected.
3.1 Mechanical Overview of the 208-lead PQFP Package

Figure 3-1 below shows the orientation of the 208-lead PQFP package.
For a detailed mechanical description, see ”Mechanical Characteristics and Packaging” on
page 165.
Figure 3-1. 208-lead PQFP Package Orientation (Top View)

156 105
157 104
208
53
1 52
4 AT91C140
AT91C140
4. Peripheral Multiplexing on PIO Lines
The AT91C140 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the
peripheral set.
The PIO Controller A manages 15 I/O lines, PA0 to PA12, PA19 and PA22.
The PIO Controller B manages only 10 I/O lines, PB0 to PB9.
Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O. Multiplexing of the
PIO Controller A is given in Table 4-1 on page 6. Multiplexing of the PIO Controller B is given
in Table 4-2 on page 6.
5
4.1 PIO Controller A Multiplexing
Table 4-1. Multiplexing on PIO Controller A
I/O Line Peripheral
Name Signal Name Description Type
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8 TCLK0 Timer Counter Clock Input 0 Input
PA9 TIOA0 Timer Counter I/O LIne A 0 I/O
PA10 TIOB0 Timer Counter I/O LIne B 0 I/O
PA11 SCKA UART A Serial Clock I/O
PA12 NPCS1 Serial Peripehral Chip Select 1 Output
PA19 ACLKO ARM System Clock Output
PA22 NPCS0 Serial Peripheral Chip Select 0 I/O
4.2 PIO Controller B Multiplexing

Table 4-2. Multiplexing on PIO Controller B
I/O Line Peripheral
Name Signal Name Description Type
PB0 TCLK1 Timer Counter Clock Input 1 Input
PB1 TIOA1 Timer Counter I/O LIne A 1 I/O
PB2 TIOB1 Timer Counter I/O LIne B 1 I/O
PB3
PB4
PB5 NRIA UART A Ring Indicator Input
PB6
PB7
PB8
PB9
6 AT91C140
AT91C140
5. Signal Description
Table 5-1. Signal Description
Block Signal Name Function Type
VDDIO I/O Lines Power Supply
VDDCORE Device Core Power Supply
Power Supplies
VDDOSC PLL and Oscillator Power Supply
GND Ground
A0-A23 Address Bus Output
External Bus Interface
D0-D15 Data Bus Input/Output
SDCK SDRAM Clock Output
DQM0-DQM1 SDRAM Byte Masks Output
SDCS SDRAM Chip Select Output
Synchronous Dynamic SDA10 SDRAM Address Line 10 Output

Memory Controller RAS Row Address Strobes Output
CAS Column Address Strobes Output
WE Write Enable Output
BA0-BA1 Bank Address Line Output
NCE0-NCE3 Chip Selects Output
NWE0-NWE1 Byte Select/Write Enable Output
Static Memory Controller
NSOE Output Enable Output
NWR Memory Block Write Enable Output
PIO Controller A PA0-PA12, PA19, PA22 PIO Controller A I/O Lines Input/Output
PIO Controller B PB0-PB9 PIO Controller B I/O Lines Input/Output
TCLK0-TCLK2 Timer Counter Clock 0 to 2 Input
Timer Counter TIOA0-TIOA2 Timer Counter I/O Line A 0 to 2 Input/Output
TIOB0-TIOA2 Timer Counter I/O Line B 0 to 2 Input/Output
MISO Master In/Slave Out Input/Output
MOSI Master Out/Slave In Input/Output
Serial Peripheral Interface SPCK Serial Clock Input/Output
NPCS0/NSS Peripheral Chip Select 0/Slave Select Input/Output
NPCS1-NPCS3 Peripheral Chip Select 1 to 3 Output
7
Table 5-1. Signal Description (Continued)
RXDA-RXDB Receive Data Input
TXDA-TXDB Transmit Data Output
NRTSA-NRSTB Ready to Send Output
NCTSA-NCTSB Clear to Send Input
UART A and UART B NDTRA-NDTRB Data Terminal Ready Output
NDSRA-NDSRB Data Set Ready Input
NDCDA-NDCDB Data Carrier Detect Input
NRIA-NRIB Ring Indicator Input
SCKA UART Serial Clock I/O
MA_COL MAC A Collision Detect Input
MA_CRS MAC A Carrier Sense Input
MA_TXER MAC A Transmit Error Output
MA_TXD0-MA_TXD3 MAC A Transmit Data Bus Output
MA_TXEN MAC A Transmit Enable Output
MA_TXCLK MAC A Transmit Clock Input
MAC A Interface MA_RXD0-MA_RXD3 MAC A Receive Data Bus Input
MA_RXER MAC A Receive Error Input
MA_RXCLK MAC A Receive Clock Input
MA_RXDV MAC A Receive Data Valid Output
MA_MDC MAC A Management Data Clock Output
MA_MDIO MAC A Management Data Bus Input/Output
MA_LINK MAC A Link Interrupt Input
MB_COL MAC B Collision Detect Input
MB_CRS MAC B Carrier Sense Input
MB_TXER MAC B Transmit Error Output
MB_TXD0-MB_TXD3 MAC B Transmit Data Bus Output
MB_TXEN MAC B Transmit Enable Output
MB_TXCLK MAC B Transmit Clock Input
MAC B Interface MB_RXD0-MB_RXD3 MAC B Receive Data Bus Input
MB_RXER MAC B Receive Error Input
MB_RXCLK MAC B Receive Clock Input
MB_RXDV MAC B Receive Data Valid Output
MB_MDC MAC B Management Data Clock Output
MB_MDIO MAC B Management Data Bus Input/Output
MB_LINK MAC B Link Interrupt Input
8 AT91C140
AT91C140
Table 5-1. Signal Description (Continued)
NTRST Test Reset Input
TCK Test Clock Input
In-Circuit Emulator TMS Test Mode Select Input
TDI Test Data Input Input
TDO Test Data Output Output
NRST Reset Input
FIQ Fast Interrupt Input
IRQ0-IRQ1 Interrupt Lines Input
PLLRC PLL RC Filter Analog
Miscellaneous
XTALIN Crystal Input Analog
XTALOUT External Crystal Analog
TST Test Mode Input
ACLKO ARM Clock Output Output
9
6. ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture
is Von Neumann load/store architecture, characterized by a single data and address bus for
instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction
set. The ARM instruction set has 32-bit wide instructions and provides maximum performance.
Thumb instructions are 16-bit wide and give maximum code density.
Instructions operate on 8-bit, 16-bit and 32-bit data types.
The CPU has seven operating modes. Each operating mode has dedicated banked registers
for fast exception handling. The processor has a total of 37 32-bit registers, including six sta-
tus registers.
7. Power Supplies
The AT91C140 has three types of power supply pins:
• VDDCORE pins power the core, including the ARM7TDMI processor, the memories and
the peripherals; voltage is between 1.65V and 1.95V, 1.8V nominal.
• VDDIO pins power the I/O lines, including those of the External Bus Interface and those of
the peripherals; voltage is between 3V and 3.6V, 3.3V nominal.
• VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and 1.95V,
1.8V nominal.
Ground pins are common to all power supplies.
10 AT91C140
AT91C140
8. System Controller
The AT91C140 features a System Controller that takes care of and controls:
• the Test Mode
• the Reset
• the System Clocks
• the Chip Identifier
The System Controller manages the reset of all the system and integrates a clock generator,
made up of an oscillator and a PLL.
8.1 Test
The AT91C140 features a test pin (TST). This pin must be tied low for normal operations.
Using the AT91C140 with the TST pin at a high level might lead to unpredictable results.
8.2 Reset Controller
8.2.1 NRST Pin

The AT91C140 is reset by asserting the NRST pin low. It should be asserted for a time ade-
quate to ensure the startup of the oscillator on a power on, and at least 1 ACLK cycle for a
warm reset. As the ACLK switches on the 31,25kHz (assuming the crystal is at 16 MHz) as
soon as the reset is asserted, it must remain low for at least 32 µs. The first instruction fetch
happens 10 ACLK cycles after the reset releases.
8.2.2 System Reset

A reset initializes the user interface registers to their default states as defined in the peripheral
sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from
address zero. Except for the program counter and the Current Program Status Register, the
ARM processor registers do not have defined reset states. When NRST is active, the inputs of
the AT91C140 must be held at valid logic levels to reduce the power consumption to a
minimum.
8.2.3 Boot Memory and Remap Command

When NRST is released, the PA0 pin is sampled to determine if the ARM processor should
boot from internal ROM or from external memory connected to NCE0. The details of the boot
operations are described in ”Memory Controller (MC)” on page 16. The Boot Program is
described in ”Boot Program” on page 24.
After a reset, the RM bit in the Mode Register reflects the state of the PA0 pin. Then, writing
this bit at 1 removes the ROM from the address 0. Writing it at 0 remaps the ROM at address
0x0.
8.3 Clock Generator

The AT91C140 features a Clock Generator based on a 16 MHz oscillator and a PLL. It pro-
vides all the clocks of the system, including a clock signal named ACLK, to the ARM
processor, to the memory controller and to the External Bus Interface and to all the embedded
peripherals
The ACLK signal is also provided on the ACLKO pin, through PIO Controller A.
Figure 8-1 below shows the architecture of the Clock Generator.
11
Figure 8-1. Clock Generator
LP
LPCS
Counter and Control Logic RDY
DIV
SA 1
XTALIN
ACLK
DIV7 1
16 MHz 16MHz
Crystal 0
Oscillator ACLKO
0
LP DIV6
XTALOUT
PLLRC PLL 240 MHz

x15
After the reset, the ACLK clock is running at 31.25 kHz. The user can program the LPCS field
to speed the boot sequence.
The ACLKST (ARM Clock Status) bit reflects the clock being used for the ARM. When read at
0, ACLK is 40 MHz if SA is 0 and 34.3 MHz if SA is 1. When read at 1, ACLK is at a frequency
according to the value programmed in the LPCS field in the System Mode Register
(SYS_MR).
8.4 Chip ID
The System Controller features a Chip ID Register that reads a value of 0x00010221
12 AT91C140
AT91C140
8.5 System Controller User Interface
Base Address: 0xFF00 0000.
Table 8-1. System Controller Register Mapping

Offset Register Name Register Description Access Reset Value
0x0 SYS_MD System Mode Register Read/Write 0x0000 034x
0x4 SYS_ID System ID Register Read-only 0x0001 0221
0x8 Reserved
0xC SYS_CLKF System Clock Status Register Read-only 0x0000001
13
8.5.1 System Mode Register
Register Name: SYS_MD
Access: Read/Write
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– 0 – 0 – – LPCS
7 6 5 4 3 2 1 0
SA LP – – 0 – 0 RM
• RM: Remap
0 =The ROM is mapped only at its normal address.
1 =The ROM is mapped at its address and at address 0x0.
• LP: Low Power Mode
0 =The PLL is enabled and ACLK is the output of the PLL divided by 6 or 7.
1 =The PLL is disabled and ACLK is defined by LPCS.
• SA: Slow ARM
0 =The ARM divider is 6.
1 =The ARM divider is 7.
• LPCS: Low Power Clock Select
LPCS Divisor ACLK

0 0 2 8 MHz
0 1 16 1 MHz
1 0 64 250 kHz
1 1 512 31,25 kHz
14 AT91C140
AT91C140
8.5.2 System ID Register
Register Name: SYS_ID
Access: Read-only
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 1
8.5.3 System Clock Status Register

Register Name: SYS_CLKF
Access: Read-only
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – ACLKST
• ACLKST: ARM Clock Status

0 = ARM Clock currently using the 240 MHz source (PLL).
1 = ARM Clock currently using the 16 MHz source (oscillator).
15
9. Memory Controller (MC)
9.1 Architecture
The AT91C140 architecture is made up of two Advanced System Buses, the ARM ASB and
the MAC ASB. Both handle a single memory space.
The ARM ASB handles the access requests of the ARM7TDMI and the PDC. It also handles
the access requests coming from the MAC ASB. It connects with the External Bus Interface,
the Peripheral Bridge and the Internal Memories. It also connects with the MAC ASB.
The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also han-
dles the access requests coming from the the ARM ASB. It connects essentially with the
Frame Buffer, but also connects with the ARM ASB.
The major advantage of this double-ASB architecture is that the Ethernet traffic does not
occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maximum
speed while the Ethernet traffic goes through the Frame Buffer.
The AT91C140 architecture is shown in Figure 9-1.
Figure 9-1. AT91C140 Memory Controller Architecture

PA0 Memory Controller
ARM ASB
ARM7TDMI
Processor
Internal
ROM
Main
Bus
Peripheral Arbiter
Data
Controller External
Bus
Interface
From Master ASB-ASB
to Slave Bridge
Peripheral APB
MACA Bridge
DMA
Secondary
Bus
Arbiter
Frame
MACB Buffer
DMA
MAC ASB
16 AT91C140
AT91C140
9.2 Memory Map
The AT91C140 memory map is divided into regions of 256 megabytes. The top memory
region (0xF000_0000) is reserved and subdivided for the internal memories and shared mem-
ory and the embedded peripherals.
The device can define up to five other active external memory regions by means of the static
memory controller and SDRAM memory controller.
The memory map is divided between both ASBs, as shown in Figure 9-1. All regions except
the 16 megabytes between 0xFC00 0000 and 0xFCFF FFFF are located on the Main ASB.
Accesses to locations between 0xFC00 0000 and 0xFCFF FFFF are routed to the MAC ASB.
The memory map assumes default values on reset. External memory regions can be repro-
grammed to other base addresses in the Static Memory Controller or in the SDRAM
Controller. Note that the internal memory regions have fixed locations that cannot be
reprogrammed.
There are no hardware locks to prevent incorrect programming of the regions. Programming
two or more regions to have the same base address or overlapping two memory regions
results in undefined behavior.
The ARM processor reset vector at address 0x00000000 is mapped into the internal ROM or
external memory connected on NCE0. This selection depends on the PA0 signal pin. After
booting, the ROM region can be disabled and any external memory can be mapped to the bot-
tom of the memory map by programming SMC_CSRx or SDRAMC_ADDR.
Figure 9-2. AT91C140 Memory Map

0x0000 0000 External Static Memory
256M bytes
0x0FFF FFFF connected on NCE0
256M bytes
SMC
256M bytes
256M bytes
256M bytes SDRAMC
0x4FFF FFFF connected on SDCS
0x5000 0000
10 x 256M bytes Unused
0xEFFF FFFF
0xF000 0000 Internal Memories
256M bytes
0xFFFF FFFF and Peripherals
17
Figure 9-3 below shows the mapping of the internal memories and the address space
reserved for the Peripheral Bridge.
Figure 9-3. Internal Memory Mapping

Actual Size
0xFF00 0000
144M bytes Reserved
0xF8FF FFFF
0xF900 0000
16M bytes ROM 1K byte
0xF9FF FFFF
0xFA00 0000
16M bytes Reserved 512 bytes
0xFAFF FFFF
0xFB00 0000
16M bytes Reserved
0xFBFF FFFF
0xFC00 0000
16M bytes Frame Buffer 16K bytes
0xFCFF FFFF
0xFD00 0000
16M bytes Reserved 64K bytes
0xFDFF FFFF
0xFD00 0000
16M bytes Unused
0xEFFF FFFF
0xFF00 0000
16M bytes Peripherals
0xFFFF FFFF
9.3 ARM ASB Arbitration

The ARM ASB is arbitrated with the following priorities:
• The PDC has the highest priority.
• The Bridge from the MAC ASB has the middle priority.
• The ARM processor has the lowest priority.
9.4 MAC ASB Arbitration

The MAC ASB is arbitrated with the following priorities:
• The Bridge from the ARM ASB has the highest priority.
• The MAC A has the middle priority.
• The MAC B has the lowest priority.
9.5 ASB-ASB Bridge Arbitration

The MAC ASB has two priority levels; the two MACs share low priority access and the ASB-
ASB Bridge has high priority. The MACs do not burst more than four words per access and
release the bus request between accesses so the MACs share a priority level with a simple
round-robin arbitration scheme.
The ARM is likely to be the only master accessing the MAC bus via the bridge and should not
perform more than a couple of cycles before releasing the MAC bus. Care should be taken to
prevent other masters on the ARM bus holding the MAC bus for more than a few cycles. Oth-
erwise, the MACs drop frames due to FIFO overflow or underflow.
When a master on one bus accesses a slave on the other bus, the following operations occur:
18 AT91C140
AT91C140
• The local bus arbiter arbitrates the master’s request for the local ASB bus if it does not
already have access to the bus.
• When the local bus arbiter grants the local bus to the master, the master initiates a cycle
with an address corresponding to a slave on the remote bus.
• The bridge is selected as the slave on the local bus and responds by inserting wait cycles.
The bridge also requests the remote bus from the remote bus arbiter.
• When the bridge is granted the remote bus, the two ASB buses are coupled and the transfer
completes.
The ASB performs pipelined arbitration. The ASB-ASB Bridge can only request the bus when
the address of the slave is available. For this reason, the ASB-ASB Bridge inserts a wait cycle
during the arbitration cycle on the remote bus because it cannot request the bus early.
9.6 Boot Mode

The AT91C140 has an integrated 1-Kbyte ROM to support the boot software. When the device
is released from reset, the pin PA0 is sampled by the Memory Controller. If sampled low, the
internal ROM becomes accessible from the address 0x0, so that the ARM processor starts
execution of the Boot Program. Note that the ROM remains accessible at its normal address.
If the pin PA0 is sampled high at reset, the mapping does not change and the external mem-
ory connected on NCE0 should contain a valid boot sequence.
The level of the pin PA0 at resets is indicated by the RM flag in the System Mode Register
(SYS_MD). Then, the RM bit can be written at any value to map to or remove the ROM from
address 0x0.
If PA0 is asserted on reset, the Boot Program in ROM is executed. The Boot Program is
described in ”Boot Program” on page 24.
Figure 9-4 below shows the mapping of the ROM depending on the Boot Mode.
Figure 9-4. ROM Mapping Depending on the Boot Mode

RM = 0 RM = 1
0x0000 0000
1K byte ROM
0x0000 03FF
0x0000 0400
External Memory External Memory

256M bytes Connected on Connected on
NCE0 NCE0
0x0FFF FFFF
19
9.7 Endianness
The AT91C140 Memory Controller operates in little-endian mode only. The user has to make
sure that the data structures used by the ARM7TDMI, the Ethernet DMAs and the PDC are
compliant with this mode of byte arrangement.
20 AT91C140
AT91C140
10. Peripherals
The Peripheral Bridge allows access to the embedded peripheral user interfaces. It is opti-
mized for low power consumption, as it is built without usage of any clock. However, any
access on the peripheral is performed in two cycles.
The AT91C140 peripherals are designed to be programmed with a minimum number of
instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the
address space.
10.1 Peripheral Registers

All of the peripheral registers are 32-bits wide and support only aligned accesses. When a
misaligned access is performed within the peripheral address space, the access is automati-
cally performed at the lower aligned address.
All undefined or unused register bits (marked “-”) read 0. It is recommended to write them at 0
for software upward compatibility.
21
10.2 Peripheral Memory Map
Figure 10-1 below gives the mapping of the peripherals integrated in the AT91C140.
Figure 10-1. Peripheral Memory Map

Peripheral Name Size
0xFF00 0000
SYSC System Controller 16K bytes
0xFF00 3FFF
0xFF00 4000
SMC Static Memory Controller 16K bytes
0xFF00 7FFF
0xFF00 8000
SDRAMC SDRAM Controller 16K bytes
0xFF00 BFFF
0xFF00 C000
PIOA Parallel I/O Controller A 16K bytes
0xFF00 FFFF
0xFF01 0000
PIOB Parallel I/O Controller B 16K bytes
0xFF01 3FFF
0xFF01 4000
TC0, TC1, TC2 Timer Counter Channel 0, 1 and 2 16K bytes
0xFF01 7FFF
0xFF01 8000
UART A Universal Asynchronous 16K bytes
Receiver Transmitter A
0xFF01 BFFF
0xFF01 C000
UART B Universal Asynchronous 16K bytes
0xFF01 FFFF Receiver Transmitter B
0xFF02 0000
SPI Serial Peripheral Interface 16K bytes
0xFF02 3FFF
0xFF02 4000
Reserved
0xFF02 FFFF
0xFF03 0000
AIC Advanced Interrupt Controller 16K bytes
0xFF03 3FFF
0xFF03 4000
MACA Ethernet MAC A 16K bytes
0xFF03 7FFF
AIC is
0xFF03 8000 mapped
MACB Ethernet MAC B 16K bytes
at both
0xFF03 BFFF addresses
0xFF03 C000 Reserved
0xFFFF EFFF
0xFFFF F000
AIC Advanced Interrupt Controller 16K bytes
0xFFFF FFFF
22 AT91C140
AT91C140
11. Peripheral Data Controller (PDC)
11.1 PDC Overview

The AT91C140 features a six-channel Peripheral Data Controller (PDC) dedicated to the two
on-chip UARTs and the SPI. One PDC channel is connected to the receiving channel and one
to the transmitting channel of each UART and of the SPI.
Each PDC channel operates as DMA (Direct Memory Access).
The User Interface of a PDC channel is integrated in the memory space of each peripheral. It
contains a 32-bit address pointer register and a 16-bit count register. When the programmed
number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible
in the peripheral status register. This status bit might trigger an interrupt.
11.2 PDC Channel Priority

The transfer requests from the peripherals are treated in the order they happen.
When several transfer requests happen in the same cycle, the following priority order is
applied:
• the UART A receiver
• the UART A transmitter
• the UART B receiver
• the UART B transmitter
• the SPI receiver
• the SPI transmitter
23
12. Boot Program
The AT91C140 can boot in several ways as explained below. When the ARM7TDMI proces-
sor is released from reset it basically attempts a fetch from address 0x00000000. Depending
on an hardware configuration, the memory mapping can be altered and thus modify how the
system boots.
12.1 Boot Mode

When the master reset is released, the pin PA0 is latched. Its state defines how the system
boots. When PA0 is latched at 1, the AT91C140 is said to be configured in external boot
mode. The initial state of the EBI maps the 1-Mbyte address range starting from 0x00000000
in the external device selected by NCE0. In this boot mode, NCE0 is assumed to be con-
nected to an external memory device containing the suitable boot code.
When PA0 is latched at 0, the AT91C140 is said to be configured in internal boot mode. The
internal boot ROM normally located at base address 0xf9000000 is aliased at address
0x00000000. In this boot mode, the ARM Processor executes the first instructions out of the
internal boot ROM.
The boot mode is reflected by the RM bit in register SYS_MD. Reading RM at 0 indicates that
the boot ROM is aliased at base address 0x00000000, eventually overlapping the memory
layout defined by the SMC and the SDRAMC registers. Reading RM at 1 indicates that the
boot ROM can be accessed only from base address 0xf9000000. Writing RM allows to select
the mapping of the boot ROM under software control.
12.2 Hardware Connection of the DataFlash

The internal boot software provides the AT91C140 with the capability of booting from an exter-
nal serial DataFlash connected on the on-chip SPI interface as described above.
When the internal boot software is used in conjunction with DataFlash, the latter must be con-
nected to the AT91C140 as shown below in Figure 12-1.
Figure 12-1. DataFlash Connection
AT91C140 DataFlash
NPCS0/PA22 CS
MOSI SI
MISO SO
SPCK CK
12.3 Internal Boot Software

The internal boot code goes through the following steps in sequence:
• The processor enters the supervisor mode and all the interrupts are masked.
• A branch is executed into the ROM alias based from 0xf9000000.
• The ROM alias based at 0x00000000 is removed by writing the RM bit at 1.
• The clock is programmed at the highest frequency achievable without using the on-chip
PLL (i.e. the frequency of the crystal divided by 2).
24 AT91C140
AT91C140
• The on-chip SPI interface is setup to prepare for communications with DataFlash.
• A bunch of data is downloaded from the DataFlash. This data is expected to contain a
formatted header describing the contents of the DataFlash.
• This header is analyzed to verify whether a DataFlash is actually present and contains valid
executable code.
• If the DataFlash is there and contains valid executable code, this code is downloaded into a
location specified by the header, and an absolute branch to this code is performed.
• If the DataFlash is missing, or if the header is not valid, an absolute branch to address
0x00000000 is performed. A suitable memory device should be mapped at this address
and contain the expected code.
12.4 DataFlash Header Details

To ensure correct operation of the boot out of DataFlash, the DataFlash must contain a valid
header. This header contains several fields which define how the application software residing
further must be handled. The structure of the DataFlash header is illustrated below in Table
12-1.
Table 12-1. Header Structure

Field Address Field Name Field Length
(1)
0x00 MAGIC 4 bytes
0x04 DSRC 4 bytes
0x08 DDST 4 bytes
0x0c DSIZE 4 bytes
0x10 ENTRY 4 bytes
Note: 1. The field address is respective to the DataFlash space. 0x00 corresponds to the first loca-
tion of the DataFlash.
The MAGIC field contains a predefined magic number which allows identification of the suit-
ability of the DataFlash. The value of this field must be 0x0075C221 to allow the boot routine
to proceed. If another value is read, the boot code gives up the download and branches to
0x0000 0000 where the real application code is expected.
The DSRC field contains the address where the code to be downloaded resides in DataFlash.
This address is respective to the DataFlash address space (not the ARM Processor address
space) and follows the non-linear addressing scheme defined in the documentation of the
DataFlash. Note that all bits are not necessarily significant, depending on the specific
DataFlash device.
The DDST field contains the destination address where the downloaded code will be copied.
This address is respective to the ARM Processor address space. Typically, this address
should point into some internal RAM.
The DSIZE field contains the number of bytes to be downloaded. This value is exclusive of the
header. It must be even.
The ENTRY field contains the address where the boot routine must branch when the down-
load is complete. It is the entry point of the newly downloaded software. Although this is not
required, the ENTRY field equals the DDST field in most cases.
25
12.5 Reserved Resources
The internal boot code needs some resources to operate correctly, especially as it programs
some on-chip peripherals. These must not be assumed to be in their reset state when the con-
trol is given to the application code. The concerned peripherals are:
• the clock management system
• the SPI interface
• the PIO pin PA22
• the RM bit
The internal boot code also uses some internal RAM locations to store temporary data. These
reside in the first 64 bytes of RAM, i.e. from 0xFD00 FFC0 to 0xFD00 FFFF. The DDST,
DSIZE fields of the DataFlash header must not define a memory area overlapping the loca-
tions used by the internal boot routine. The ENTRY field must not point into this area.
26 AT91C140
AT91C140
13. External Bus Interface (EBI)
The External Bus Interface (EBI) generates the signals that control access to external memo-
ries or peripheral devices. It contains two controllers, the SDRAM Controller and the Static
Memory Controller and manages the sharing of data and address busses between both of
these controllers.
13.1 Signal Multiplexing

Table 13-1. Signal Description and Multiplexing
Controlled by
Name Description Controlled by SMC SDRAMC
[D15:0] Data Bus [D15:0] [D15:0]
[A9:0] Address Lines 0 to 9 [A9:0] [A9:0]
A10 Address Line 10 A10
SDA10 SDRAM Controller Address Line 10 A10
[A12:11] Address Lines 11 to 12 [A12:11] [A12:11]
[A18:13] Address Lines 13 to 18 [A18:13]
A19/BA0 Address Line 19 or Bank Address 0 A19 BA0
A20/BA1 Address Line 20 or Bank Address 1 A20 BA1
[A23:21] Address Lines 21 to 23 [A23:21]
SDCK SDRAM Clock SDCK
SDCS SDRAM Controller Chip Select SDCS
RAS SDRAM Row Signal RAS
CAS SDRAM Column Signal CAS
WE SDRAM Write Enable WE
DQM0-DQM1 SDRAM Data Mask Enable Signals DQM0-DQM1
NCE0-NCE3 Active low chip enable NCE0-NCE3
NWE0-NWE1 Active low byte select/write strobe signals NWE0-NWE1
NWR Active low write strobe signals NWR
NSOE Active low read enable signal NSOE
27
14. SDRAM Controller (SDRAMC)
14.1 Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to
8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit)
and word (32-bit) accesses. The maximum addressable SDRAM size is 256M bytes.
The SDRAM Controller supports a read or write burst length of one location. It keeps track of
the active row in each bank, thus maximizing SDRAM performance, e.g., the application may
be placed in one bank and data in the other banks. So as to optimize performance, it is advis-
able to avoid accessing different rows in the same bank.
14.2 Block Diagram
Figure 14-1. SDRAM Controller Block Diagram
SDRAMC
SDCK
SDRAMC
Memory
Chip Select
Controller SDCS
BA[1:0]
RAS
CAS
System ACLK
Controller WE
DQM[1:0]
A[12:11, 9:0]
SDA10
D[15:0]
User Interface
APB
28 AT91C140
AT91C140
14.3 I/O Lines Description
Table 14-1. I/O Line Description
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCS SDRAM Controller Chip Select Output Low
BA[1:0] Bank Select Signals Output High
RAS Row Signal Output Low
CAS Column Signal Output Low
WE SDRAM Write Enable Output Low
DQM[1:0] Data Mask Enable Signals Output Low
A [12:11]
SDA10 Address Bus Output
A[9:0]
D[15:0] Data Bus I/O
14.4 Application Example
14.4.1 Hardware Interface

Figure 14-2 shows an example of an SDRAM device connection by using a 16-bit data bus
width.
Figure 14-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
D0-D31
RAS 2M x 8 2M x 8
CAS
SDCK D0-D7 SDRAM D8-D15 SDRAM
WE D0-D7 D0-D7
DQM0
DQM1 CS CS
VDD CKE VDD CKE
A0-A11 A0- A11
CLK A0--A11 CLK A0-A11
SDWE SDWE
WE BA0 BA0 WE BA0 BA0
RAS BA1 RAS BA1 BA1
BA1
CAS CAS
DQM DQM
DQM0 DQM1
A0-A11
A0-A9, SDA10, A11
A19/BA0
A20/BA1
SDRAM SDCS
Controller
14.4.2 Software Interface

The SDRAM Controller’s function is to make the SDRAM device access protocol transparent
to the user. Table 14-2 to Table 14-4 illustrate the SDRAM device memory mapping therefore
seen by the user in correlation with the device structure. Various configurations are illustrated.
29
16-bit Memory Data Bus Width
Table 14-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[10:0] Column[7:0] M0

Bk[1:0] Row[10:0] Column[8:0] M0
Bk[1:0] Row[10:0] Column[9:0] M0

CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0] M0

Bk[1:0] Row[11:0] Column[8:0] M0

CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[7:0] M0
30 AT91C140
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14.5 SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by
the following sequence:
1. A minimum pause of 200 µs is provided to precede any signal toggle.
2. An All Banks Precharge command is issued to the SDRAM devices.
3. Eight auto-refresh (CBR) cycles are provided.
4. A mode register set (MRS) cycle is issued to program the parameters of the SDRAM
devices, in particular CAS latency and burst length.
5. A Normal Mode command is provided, 3 clocks after tMRD is met.
6. Perform a dummy access in the SDRAM Memory Space to initialize the state
machine.
7. Write refresh rate into the count field in the SDRAMC Refresh Timer register.
(Refresh rate = delay between refresh cycles).
After these six steps, the SDRAM devices are fully functional.
The commands (NOP, MRS, CBR, normal mode) are generated by programming the com-
mand field in the SDRAMC Mode register.
Figure 14-3. SDRAM Device Initialization Sequence
tRP tRC tMRD
SDCK
A[9:0]
SDA10
A[12:11]
SDCS
RAS
CAS
WE
NBS
Inputs Stable for Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
200 µsec
31
14.6 SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access.
If the next access is a sequential write access, writing to the SDRAM device is carried out. If
the next access is a write-sequential access, but the current access is to a boundary page, or
if the next access is in another row, then the SDRAM Controller generates a precharge com-
mand, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (tRP) commands
and active/write (tRCD) commands. For a definition of these timing parameters, refer to the
”SDRAMC Configuration Register” on page 39. This is described in Figure 14-4 below.
Figure 14-4. Write Burst, 16-bit SDRAM Access

tRCD = 3
SDCS
SDCK
A[12:0] Row n col a col b col c col d col e col f col g col h col i col j col k col l
RAS
CAS
WE
D[15:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl
32 AT91C140
AT91C140
14.7 SDRAM Controller Read Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access.
If the next access is a sequential read access, reading to the SDRAM device is carried out. If
the next access is a sequential read access, but the current access is to a boundary page, or if
the next access is in another row, then the SDRAM Controller generates a precharge com-
mand, activates the new row and initiates a read command. To comply with SDRAM timing
parameters, an additional clock cycle is inserted between the precharge/active (tRP) command
and the active/read (tRCD) command, After a read command, additional wait states are gener-
ated to comply with cas latency. The SDRAM Controller supports a cas latency of two. For
definition of these timing parameters, refer to ”SDRAMC Configuration Register” on page 39.
This is described in Figure 14-5 below.
Figure 14-5. Read Burst, 16-bit SDRAM access
tRCD = 3 CAS = 2
SDCS
SDCK
A[12:0] Row n col a col b col c col d col e col f
RAS
CAS
WE
D[15:0] Dna Dnb Dnc Dnd Dne Dnf

(Input)
33
14.8 Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In
this case, the SDRAM controller generates a precharge command, activates the new row and
initiates a read or write command. To comply with SDRAM timing parameters, an additional
clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD)
command. This is described in Figure 14-6 below.
Figure 14-6. Read Burst with Boundary Row Access
TRP = 3 TRCD = 3 CAS = 3
SDCS
SDCK
Row n
A[12:0] col a col b col c col d Row m col a col b col c col d col e
RAS
CAS
WE
D[15:0] Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme
34 AT91C140
AT91C140
14.9 SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gen-
erated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. A timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory
accesses are not delayed. However, if the ARM tries to access the SDRAM, it is held until the
refresh cycle has completed. See Figure 14-7 below.
Figure 14-7. Refresh Cycle Followed by a Read Access

tRP = 3 tRC = 8 tRCD = 3 CAS = 2
SDCS
SDCK
Row n
A[12:0] col c col d Row m col a
RAS
CAS
WE
D[15:0] Dnb Dnc Dnd Dma

(input)
35
14.10 SDRAM User Interface
Base Address: 0xFF00 8000
Table 14-5. SDRAM Controller Register Mapping

Offset Register Name Register Description Access Reset State
0x00 SDRAMC_MR SDRAMC Mode Register Read/Write 0x00000000
0x04 SDRAMC_TR SDRAMC Refresh Timer Register Read/Write 0x00000800
0x08 SDRAMC_CR SDRAMC Configuration Register Read/Write 0x0299C140
0x0C SDRAM_16BIT SDRAM 16-bit configuration Read/Write 0x00000001
0x10 SDRAMC_ADDR Base address for SDCS Read/Write 0x00000040
36 AT91C140
AT91C140
14.10.1 SDRAMC Mode Register
Register Name: SDRAMC_MR
Access Type: Read/Write
Reset Value: 0x00000010
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – MODE
7 6 5 4 3 2 1 0
MODE – – – – – –
• MODE: SDRAMC Command Mode

This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
MODE Description
0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
0 0 1 The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
0 1 0
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program
0 1 1
the Mode Register. For instance, when this mode is activated, an access to the “SDRAM_Base + offset” address
generates a “Load Mode Register” command with the value “offset” written to the SDRAM device Mode Register.
The SDRAM Controller issues a “Refresh” Command when the SDRAM device is accessed regardless of the
1 0 0
cycle. Prior to this, an “All Banks Precharge” command must be issued.
Others Reserved
37
14.10.2 SDRAMC Refresh Timer Register
Register Name: SDRAMC_TR
Reset Value: 0x00000800
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – COUNT
7 6 5 4 3 2 1 0
COUNT
• COUNT: SDRAMC Refresh Timer Count

This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh
burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate
of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of one length.
To refresh the SDRAM device even if the reset value is not equal to 0, this 12-bit field must be written. If this condition is not
satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.
38 AT91C140
AT91C140
14.10.3 SDRAMC Configuration Register
Register Name: SDRAMC_CR
Reset Value: 0x0299C140
31 30 29 28 27 26 25 24
– – – – – TRAS
23 22 21 20 19 18 17 16
TRAS TRCD TRP
15 14 13 12 11 10 9 8
TRP TRC TWR
7 6 5 4 3 2 1 0
TWR 1 0 NB NR NC
• NC: Number of Column Bits

Reset value is 8 column bits.
NC Column Bits
0 0 8
0 1 9
1 0 10
1 1 11
• NR: Number of Row Bits

Reset value is 11 row bits.
NR Row Bits
0 0 11
0 1 12
1 0 13
1 1 Reserved
• NB: Number of Banks

Reset value is two banks.
NB Number of Banks
0 2
1 4
• TWR: Write Recovery Delay

Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15.
If TWR is less than or equal to 2, two clock periods are inserted by default.
39
• TRC: Row Cycle Delay
Reset value is eight cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is
between 2 and 15.
If TRC is less than or equal to 2, two clock periods are inserted by default.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 2 and 15.
If TRP is less than or equal to 2, two clock periods are inserted by default.
• TRCD: Row to Column Delay
Reset value is three cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 2 and 15.
If TRCD is less than or equal to 2, two clock periods are inserted by default.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 2 and 15.
If TRAS is less than or equal to 2, two clock periods are inserted by default.
40 AT91C140
AT91C140
14.10.4 SDRAMC Address Register
Register Name: SDRAMC_ADDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
SDCS_ADDR
• SDCS_ADDR
This field defines the eight most significant bits of the base address of the SDRAMC.
41
15. Static Memory Controller (SMC)
The AT91C140 features a Static Memory Controller (SMC), that enables interfacing with a
wide range of external static memory on peripheral devices, including Flash, ROM, static
RAM, and parallel peripherals.
The SMC provides a glueless memory interface to external memory using common address,
data bus and dedicated control signals. The SMC is highly programmable and has up to 24
bits of address bus, a 16-bit data bus and up to four chip select lines. The SMC supports differ-
ent access protocols allowing single clock-cycle accesses. The SMC is programmed as an
internal peripheral that has a standard APB bus interface and a set of memory-mapped regis-
ters. It shares the external address and data buses with the SDRAMC and any external bus
master.
15.1 External Memory Mapping

The memory map associates the internal 32-bit address space with the external 24-bit
address bus. The memory map is defined by programming the base address and page size of
the external memories. Only address bits A1 to A23 are significant for 16-bit memories.
If the physical memory-mapped device is smaller than the programmed page size, it wraps
around and appears to be repeated within the page. The SMC correctly handles any valid
access to the memory device within the page.
In the event of an access request to an address outside any programmed page, an abort sig-
nal is generated by the internal decoder. Two types of abort are possible: instruction prefetch
abort and data abort. The corresponding exception vector addresses are 0x0000000C and
0x00000010. It is up to the system programmer to program the exception handling routine
used in case of an abort.
15.2 Pin Description

Table 15-1 below lists the pins used by the SMC to control external memories.
Table 15-1. SMC Pin Description

FPDRAM Description Type
[A23:0] Address bus Output
[D15:0] Data bus I/O
NCE0-NCE3 Active low chip enable Output
NWE0-NWE1 Active low byte select/write strobe signals Output
NWR Active low write strobe signals Output
NSOE Active low read enable signal Output
15.3 Byte Write or Byte Select Mode

Each chip select can be individually programmed to operate in Byte Write or Byte Select
Mode.
• The Byte Write Mode supports byte write signals and a single read signal.
• The Byte Select Mode selects the appropriate byte using two byte-select lines and
separate read and write signals.
42 AT91C140
AT91C140
This option is controlled by the BAT bit in the Chip Select Register (SMC_CSR0 to
SMC_CSR3).
The Byte Write Mode is used to connect two 8-bit devices on a 16-bit bus.
• The NWE0 signal is used as the write enable signal for byte 0.
• The NWE1 signal is used as the write enable signal for byte 1.
• The NSOE signal enables memory reads to all memory blocks.
The Byte Select Mode is used to connect one 16-bit device on a 16-bit data bus.
• The NWE0 signal is used to select byte 0 for read and write operations.
• The NWE1 signal is used to select byte 1 for read and write operations.
• The NWR signal is used as the write enable signal for the memory block.
• The NSOE signal enables memory reads to the memory block.
15.4 Read Protocols

The SMC provides two alternative protocols for external memory read access; standard and
early read. The difference between the two protocols lies in the timing of the NSOE (read
cycle) waveform.
The protocol is selected by the DRP field in the Memory Control Register (SMC_MCR) and is
valid for all memory devices. Standard read protocol is the default protocol after reset.
15.4.1 Standard Read Protocol

Standard read protocol implements a read cycle in which NSOE and the write strobes are sim-
ilar. Both are active during the second half of the clock cycle. The first half of the clock cycle
allows time to ensure completion of the previous access, as well as the output of address and
NCE before the read cycle begins.
During a standard read protocol external memory access, the chip enable signal NCE0 to
NCE3 are set low and the address lines are valid at the beginning of the access, whereas
NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The
write strobes are the same in both protocols. The write strobes always go low in the second
half of the master clock cycle.
15.4.2 Early Read Protocol

Early read protocol provides more time for a read access from the memory by asserting NSOE
at the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NSOE remains active continuously. Since a read cycle normally limits the speed of operation
of the external memory system, early read protocol allows a faster clock frequency to be used.
However, an extra wait state is required in some cases to avoid contention on the external
bus.
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins. This wait state is generated in addition to any other programmed wait
states (i.e., data float wait). No wait state is added when a read cycle is followed by a write
cycle, between consecutive accesses of the same type or between external and internal mem-
ory accesses.
43
15.5 Write Protocol
During a write cycle, the data becomes valid after the falling edge of the write strobe signal
and remains valid after the rising edge of the write strobe. The external write strobe waveform
on the appropriate write strobe pin is used to control the output data timing to guarantee this
operation.
Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the
write signal too long and cause a contention with a subsequent read cycle in standard proto-
col. In early read protocol, the data can remain valid longer than in standard read protocol due
to the additional wait cycle that follows a write access.
15.6 Wait States

The SMC can automatically insert wait states. The different types of wait states are:
• Standard wait states
• Data float wait states
• Chip select change wait states
• Early read wait states, as described in “Early Read Protocol” above.
15.6.1 Standard Wait States

Each chip select can be programmed to insert one or more wait states during an access on
the corresponding device. This is done by setting the WSE field in the corresponding
SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same
register.
When no wait state is programmed (WSE = 0), the NWE signal lasts only one-half cycle. If at
least one wait state is programmed, the NWE signal lasts an integer number of cycles, accord-
ingly to the number of wait states programmed.
15.6.2 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices it is necessary
to add wait states (data float waits) after a read access before starting a write access or a read
access to a different external memory.
The Data Float Output Time (TDF) for each external memory device is programmed in the
TDF field of the SMC_CSR register for the corresponding chip select. The value (0 - 7 clock
cycles) indicates the number of data float waits to be inserted and represents the time allowed
for the data output to go to high impedance after the memory is disabled.
The SMC keeps track of the programmed external data float time even when it makes internal
accesses to ensure that the external memory system is not accessed while it is still busy.
Internal memory accesses and consecutive accesses to the same external memory do not
insert added data float wait states.
When data float wait states are being used, the SMC prevents the SDRAM Controller from
accessing the external data bus.
15.6.3 Chip Select Change Wait States

A chip select wait state is automatically inserted when consecutive accesses are made to two
different external memories (if no wait states have already been inserted). If any wait states
have already been inserted (e.g., data float wait), then none are added.
44 AT91C140
AT91C140
15.7 SMC User Interface
The memory control register (SMC_MCR) is used to program the number of active chip
selects and data read protocol. Four chip select registers (SMC_CSR0 to SMC_CSR3) are
used to program the parameters for the individual external memories. Each SMC_CSR must
be programmed with a different base address, even for unused chip selects.
During the boot sequence, the Chip Select Registers must be programmed as required
depending on the devices connected on the external bus. The chip select addresses that are
programmed take effect immediately. Wait states also take effect immediately when they are
programmed to optimize boot program execution.
Table 15-2. SMC Register Mapping

Offset Register Name Register Description Access Reset Value
0x00 SMC_CSR0 Chip Select Register Read/Write 0x0000203D
0x04 SMC_CSR1 Chip Select Register Read/Write 0x10000000
0x08 SMC_CSR2 Chip Select Register Read/Write 0x20000000
0x0C SMC_CSR3 Chip Select Register Read/Write 0x30000000
0x10 – Reserved – –
0x1C – Reserved – –
0x24 SMC_MCR Memory Control Register Read/ Write 0x0
45
15.7.1 SMC Chip Select Register
Register Name: SMC_CSR0..SMC_CSR3
Access: Read/Write
31 30 29 28 27 26 25 24
BA
23 22 21 20 19 18 17 16
BA – – – –
15 14 13 12 11 10 9 8
– – CSEN BAT TDF PAGES
7 6 5 4 3 2 1 0
PAGES MWS WSE NWS DBW
• DBW: Data Bus Width
DBW Data Bus Width

0 0 Reserved
0 1 16-bit external bus
1 0 Reserved
1 1 Reserved
• NWS: Number of Wait States

• WSE: Wait State Enable
• MWS: Multiply Wait States
NWS WSE Wait States Number

MWS = 0 MWS = 1
X X X 0 0 0
0 0 0 1 1 8
0 0 1 1 2 16
0 1 0 1 3 24
0 1 1 1 4 32
1 0 0 1 5 40
1 0 1 1 6 48
1 1 0 1 7 56
1 1 1 1 8 64
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• PAGES: Page Size
PAGES Page Size Base Address

0 0 1M byte BA20-BA31
0 1 4M bytes BA22-BA31
1 0 16M bytes BA24-BA31
1 1 Reserved –
• TDF: Data Float Output Time
TDF Cycles after Transfer

0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
• BAT: Byte Access Mode

0 = Byte Write Mode
1= Byte Select Mode
• CSEN: Chip Select Enable
0 = Chip Select is disabled
1 = Chip Select is enabled
• BA: Base Address
This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of
the base address are ignored by the SMC decoder.
47
15.7.2 SMC Memory Control Register
Register Name: SMC_MCR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – DRP – – – –
• DRP: Data Read Protocol

0 =Standard Read Mode
1 =Early Read Mode
48 AT91C140
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16. Ethernet MAC (EMAC)
The AT91C140 features two identical Ethernet MACs, both of which feature the following:
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbits per Second Data Throughput Capability
• Full- and Half-duplex Operation
• Media Independent Interface to the Physical Layer
• Register Interface to Address, Status and Control Registers
• DMA Interface
• Interrupt Generation to Signal Receive and Transmit Completion
• 28-byte Transmit and 28-byte Receive FIFOs
• Automatic Pad and CRC Generation on Transmitted Frames
• Address Checking Logic to Recognize Four 48-bit Addresses
• Supports Promiscuous Mode Where All Valid Frames are Copied to Memory
• Supports Physical Layer Management through MDIO Interface
The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model
between the physical layer (PHY) and the logical link layer (LLC). It controls the data
exchange between a host and a PHY layer according to Ethernet IEEE 802.3 data frame for-
mat. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA
management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management.
The Ethernet MAC transfers data in media-independent interface (MII).
16.1 Block Diagram
Figure 16-1. Block Diagram
MAC
ASB
DMA Mx_TXCLK, Mx_RXCLK
Mx_TXEN, Mx_TXER
APB Bridge
Mx_CRS, Mx_COL
Mx_RXER, Mx_RXDV
APB
Ethernet MAC
Mx_RXD[3:0]
Mx_TXD[3:0]
Mx_MDC
ACLK
Mx_MDIO
Interrupt Control
EMAC IRQ
49
16.2 Media Independent Interface
Table 16-1. Pin Configuration
MII Signal Signal Name Pin Name EMAC A Pin Name EMAC B
Transmit Clock ETXCK MA_TXCLK MB_TXCLK
Carrier Sense ECRS MA_CRS MB_CRS
Collision Detect ECOL MA_COL MB_COL
Receive Data Valid ERXDV MA_RXDV MB_RXDV
4-bit Receive Data ERX0-ERX3 MA_RXD[0:3] MB_RXD[0:3]
Receive Error ERXER MA_RXER MB_RXER
Receive Clock ERXCK MA_RXCLK MB_RXCLK
Transmit Enable ETXEN MA_TXEN MB_TXEN
4-bit Transmit Data ETX0-ETX3 MA_TXD[0:3] MB_TXD[0:3]
Transmit Error ETXER MA_TXER MB_TXER
16.3 Transmit/Receive Operation

A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame delim-
iter (SFD), destination address (DA), source address (SA), length, data (Logical Link Control
Data) and frame check sequence CRC32 (FCS).
Table 16-2. Packet Format

Preamble Frame(1)
Alternating 1s/0s SFD DA SA Length/type LLC Data PAD FCS
Up to 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes
Note: 1. Frame Length between 64 bytes and 1518 bytes.

The packets are Manchester-encoded and -decoded and transferred serially using NRZ data
with a clock. All fields are of fixed length except for the data field. The MAC generates and
appends the preamble, SFD and CRC fields during transmission.
The preamble and SFD fields are stripped during reception.
16.3.1 Preamble and Start of Frame Delimiter (SFD)

The preamble field is used to acquire bit synchronization with an incoming packet. When
transmitted, each packet contains 62 bits of alternating 1,0 preamble. Some of this preamble
is lost as the packet travels through the network. Byte alignment is performed with the Start of
Frame Delimiter (SFD) pattern that consists of two consecutive 1's.
16.3.2 Destination Address (DA)

The destination address (DA) indicates the destination of the packet on the network and is
used to filter unwanted packets. There are three types of address formats: physical, multicast
and broadcast. The physical address is a unique address that corresponds only to a single
node. All physical addresses have an MSB of 0.
Multicast addresses begin with an MSB of 1. The MAC filters multicast addresses using a
standard hashing algorithm that maps all multicast addresses into a 6-bit value. This 6-bit
50 AT91C140
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value indexes a 64-bit array that filters the value. If the address consists of all ones, it is a
broadcast address, indicating that the packet is intended for all nodes.
16.3.3 Source Address (SA)

The source address (SA) is the physical address of the node that sent the packet. Source
addresses cannot be multicast or broadcast addresses. This field is passed to buffer memory.
16.3.4 Length/Type
If the value of this field is less than or equal to 1500, then the Length/Type field indicates the
number of bytes in the subsequent LLC Data field. If the value of this field is greater than or
equal to 1536, then the Length/Type field indicates the nature of the MAC client protocol (pro-
tocol type).
16.3.5 LLC Data

The data field consists of anywhere from 46 to 1500 bytes. Messages longer than 1500 bytes
need to be broken into multiple packets. Messages shorter than 46 bytes require appending a
pad to bring the data field to the minimum length of 46 bytes. If the data field is padded, the
number of valid data bytes is indicated in the length field.
16.3.6 Frame Check Sequence Field (FCS)

The Frame Check Sequence (FCS) is a 32-bit CRC field, calculated and appended to a packet
during transmission to allow detection of errors when a packet is received. During reception,
error free packets result in a specific pattern in the CRC generator. Packets with improper
CRC will be rejected.
16.3.7 Frame Format Extensions

The original Ethernet standards define the minimum frame size as 64 bytes and the maximum
as 1518 bytes. These numbers include all bytes from the Destination MAC Address field
through the Frame Check Sequence field. The Preamble and Start Frame Delimiter fields are
not included when quoting the size of a frame. The IEEE 802.3ac standard extended the max-
imum allowable frame size to 1522 bytes to allow a VLAN tag to be inserted into the Ethernet
frame format. The BIG bit defined in the ETH_CFG register processes packets with a VLAN
tag.
The VLAN protocol permits insertion of an identifier, or tag, into the Ethernet frame format to
identify the VLAN to which the frame belongs. It allows frames from stations to be assigned to
logical groups. This provides various benefits, such as easing network administration, allowing
formation of work groups, enhancing network security, and providing a means of limiting
broadcast domains (refer to IEEE standard 802.1Q for definition of the VLAN protocol). The
802.3ac standard defines only the implementation details of the VLAN protocol that are spe-
cific to Ethernet.
If present, the 4-byte VLAN tag is inserted into the Ethernet frame between the Source MAC
Address field and the Length field. The first 2 bytes of the VLAN tag consist of the “802.1Q Tag
Type” and are always set to a value of 0x8100. The 0x8100 value is a reserved Length/Type
field assignment that indicates the presence of the VLAN tag, and signals that the traditional
Length/Type field can be found at an offset of four bytes further into the frame. The last two
bytes of the VLAN tag contain the following information.
• The first three bits are a User Priority Field that may be used to assign a priority level to the
Ethernet frame.
51
• The following one bit is a Canonical Format Indicator (CFI) used in Ethernet frames to
indicate the presence of a Routing Information Field (RIF).
• The last twelve bits are the VLAN Identifier (VID) that uniquely identifies the VLAN to which
the Ethernet frame belongs.
With the addition of VLAN tagging, the 802.3ac standard permits the maximum length of an
Ethernet frame to be extended from 1518 bytes to 1522 bytes. Table 16-3 on page 52 illus-
trates the format of an Ethernet frame that has been “tagged” with a VLAN identifier according
to the IEEE 802.3ac standard.
Table 16-3. Ethernet Frame with VLAN Tagging

Preamble 7 bytes
Start Frame Delimiter 1 byte
Dest. MAC Address 6 bytes
Source MAC Address 6 bytes
Length/Type = 802.1Q Tag Type 2 byte
Tag Control Information 2 bytes
Length / Type 2 bytes
MAC Client Data 0 - n bytes
Pad 0 - p bytes
Frame Check Sequence 4 bytes
16.4 DMA Operations

Frame data is transferred to and from the Ethernet MAC via the DMA interface. All transfers
are 32-bit words and may be single accesses or bursts of two, three or four words. Burst
accesses do not cross 16-byte boundaries.
The DMA controller performs four types of operations on the ASB bus. In order of priority,
these operations are receive buffer manager read, receive buffer manager write, transmit data
DMA read and receive data DMA write.
16.4.1 Transmitter Mode

Transmit frame data needs to be stored in contiguous memory locations. It does not need to
be word-aligned.
The transmit address register is written with the address of the first byte to be transmitted.
Transmit is initiated by writing the number of bytes to transfer (length) to the transmit control
register.
The transmit channel then reads data from memory 32 bits at a time and places them in the
transmit FIFO.
The transmit block starts frame transmission when three words have been loaded into the
FIFO.
The transmit address register must be written before the transmit control register. While a
frame is being transmitted, it is possible to set up one other frame for transmission by writing
new values to the transmit address and control registers. Reading the transmit address regis-
ter returns the address of the buffer currently being accessed by the transmit FIFO.
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Reading the transmit control register returns the total number of bytes to be transmitted. The
BNQ bit in the Transmit Status Register indicates whether another buffer can be safely
queued. An interrupt is generated whenever this bit is set.
Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from
the transmit FIFO word-by-word. If necessary, padding is added to make the frame length 60
bytes. The CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end
of the frame, making the frame length a minimum of 64 bytes. The CRC is not appended if the
NCRC bit is set in the transmit control register.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted
at least 96 bit times apart to guarantee the inter-frame gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert
and then starts transmission after the inter-frame gap of 96 bit-times.
If the collision signal is asserted during transmission, the transmitter transmits a jam sequence
of 32 bits taken from the data register and then retries transmission after the backoff time has
elapsed. An error is indicated and any further attempts aborted if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mechanism
as jam insertion. Underrun also causes TXER to be asserted.
16.4.2 Receiver Mode

When a packet is received, it is checked for valid preamble, CRC, alignment, length and
address. If all these criteria are met, the packet is stored successfully in a receive buffer. If at
the end of reception the CRC is bad, then the received buffer is recovered. Each received
frame including CRC is written to a single receive buffer.
Receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (BIG = 1
in ETH_CFG) of data (the maximum length of an Ethernet frame).
The start location for each received frame is stored in memory in a list of receive buffer
descriptors at a location pointed to by the receive buffer queue pointer register. Each entry in
the list consists of two words. The first word is the address of the received buffer; the second is
the receive status. Table 16-4 defines an entry in the received buffer descriptor list.
To receive frames, the buffer queue must be initialized by writing an appropriate address to
bits [31:2] in the first word of each list entry. Bit zero of word zero must be written with zero.
After a frame is received, bit zero becomes set and the second word indicates what caused
the frame to be copied to memory. The start location of the received buffer descriptor list
should be written to the received buffer queue pointer register before receive is enabled (by
setting the receive enable bit in the network control register). As soon as the received block
starts writing received frame data to the receive FIFO, the received buffer manager reads the
first receive buffer location pointed to by the received buffer queue pointer register. If the filter
block is active, the frame should be copied to memory; the receive data DMA operation starts
writing data into the receive buffer. If an error occurs, the buffer is recovered. If the frame is
received without error, the queue entry is updated. The buffer pointer is rewritten to memory
with its low-order bit set to indicate successful frame reception and a used buffer. The next
word is written with the length of the frame and how the destination address was recognized.
The next receive buffer location is then read from the following word or, if the current buffer
pointer had its wrap bit set, the beginning of the table. The maximum number of buffer pointers
before a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that
53
entry. The received buffer queue pointer register must be written with zero in its lower-order bit
positions to enable the wrap function to work correctly.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then
the buffer has already been used and cannot be used again until software has processed the
frame and cleared bit zero. In this case, the DMA block sets the buffer unavailable bit in the
received status register and triggers an interrupt. The frame is discarded and the queue entry
is reread on reception of the next frame to see if the buffer is now available. Each discarded
frame increments a statistics register that is cleared on being read. When there is network
congestion, it is possible for the MAC to be programmed to apply back pressure.
This is when half-duplex mode collisions are forced on all received frames by transmitting 64
bits of data (a default pattern).
Reading the received buffer queue register returns the location of the queue entry currently
being accessed. The queue wraps around to the start after either 1024 entries (i.e., 2048
words) or when the wrap bit is found to be set in bit 1 of the first word of an entry.
Table 16-4. Received Buffer Descriptor List

Bit Function
Word 0
31:2 Base address of receive buffer
1 Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue
pointer register to give the pointer to entries in this table is cleared after the buffer is
used.
0 Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA
owns the buffer. If this bit is not zero when the entry is read by the receiver, the
buffer unavailable bit is set in the received status register and the receiver goes
inactive.
Word 1
31 Global all ones broadcast address detected
30 Multicast hash match
29 Unicast hash match
28 External address
27 Unknown source address (reserved for future use)
26 Local address match (Specific address 1 match)
22:11 Reserved; written to 0
10:0 Length of frame including FCS
54 AT91C140
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16.5 Address Checking
Whether or not a frame is stored depends on what is enabled in the network configuration reg-
ister, the contents of the specific address and hash registers and the frame destination
address. In this implementation of the MAC the frame source address is not checked.
A frame is not copied to memory if the MAC is transmitting in half-duplex mode at the time a
destination address is received.
The hash register is 64 bits long and takes up two locations in the memory map.
There are four 48-bit specific address registers, each taking up two memory locations. The
first location contains the first four bytes of the address; the second location contains the last
two bytes of the address stored in its least significant byte positions. The addresses stored
can be specific, group, local or universal.
Ethernet frames are transmitted a byte at a time, LSB first. The first bit (i.e., the LSB of the first
byte) of the destination address is the group/individual bit and is set one for multicast
addresses and zero for unicast. This bit corresponds to bit 24 of the first word of the specific
address register. The MSB of the first byte of the destination address corresponds to bit 31 of
the specific address register.
The specific address registers are compared to the destination address of received frames
once they have been activated. Addresses are deactivated at reset or when the first byte
[47:40] is written and activated or when the last byte [7:0] is written. If a receive frame address
matches an active address, the local match signal is set and the store frame pulse signal is
sent to the DMA block via the ACLK synchronization block.
A frame can also be copied if a unicast or multicast hash match occurs, it has the broadcast
address of all ones, or the copy all frames bit in the network configuration register is set.
The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the network
configuration register is zero. This sets the broadcast match signal and triggers the store
frame signal.
The unicast hash enable and the multicast hash enable bits in the network configuration regis-
ter enable the reception of hash matched frames. So all multicast frames can be received by
setting all bits in the hash register.
The CRC algorithm reduces the destination address to a 6-bit index into a 64-bit hash regis-
ter.If the equivalent bit in the register is set, the frame is matched depending on whether the
frame is multicast or unicast and the appropriate match signals are sent to the DMA block. If
the copy all frames bit is set in the network configuration register, the store frame pulse is
always sent to the DMA block as soon as any destination address is received.
55
16.6 EMAC User Interface
MACA Memory Address: 0xFF034000
MACB Memory Address: 0xFF038000
Table 16-5. Ethernet MAC Register Mapping

Offset Register Name Register Description Read/Write Reset
0x00 ETH_CTL Network Control Register Read/Write 0x0
0x04 ETH_CFG Network Configuration Register Read/Write 0x800
0x08 ETH_SR Network Status Register Read-only 0x6
0x0C ETH_TAR Transmit Address Register Read/Write 0x0
0x10 ETH_TCR Transmit Control Register Read/Write 0x0
0x14 ETH_TSR Transmit Status Register Read/Write 0x18
0x18 ETH_RBQP Receive Buffer Queue Pointer Read/Write 0x0
0x1C – Reserved Read-only 0x0
0x20 ETH_RSR Receive Status Register Read/Write 0x0
0x24 ETH_ISR Interrupt Status Register Read/Write 0x0
0x28 ETH_IER Interrupt Enable Register Write-only –
0x2C ETH_IDR Interrupt Disable Register Write-only –
0x30 ETH_IMR Interrupt Mask Register Read-only 0xFFF
0x34 ETH_MAN PHY Maintenance Register Read/Write 0x0
(1)
Statistics Registers
0x40 ETH_FRA Frames Transmitted OK Register Read/Write 0x0
0x44 ETH_SCOL Single Collision Frame Register Read/Write 0x0
0x48 ETH_MCOL Multiple Collision Frame Register Read/Write 0x0
0x4C ETH_OK Frames Received OK Register Read/Write 0x0
0x50 ETH_SEQE Frame Check Sequence Error Register Read/Write 0x0
0x54 ETH_ALE Alignment Error Register Read/Write 0x0
0x58 ETH_DTE Deferred Transmission Frame Register Read/Write 0x0
0x5C ETH_LCOL Late Collision Register Read/Write 0x0
0x60 ETH_ECOL Excessive Collision Register Read/Write 0x0
0x64 ETH_CSE Carrier Sense Error Register Read/Write 0x0
0x68 ETH_TUE Transmit Underrun Error Register Read/Write 0x0
0x6C ETH_CDE Code Error Register Read/Write 0x0
0x70 ETH_ELR Excessive Length Error Register Read/Write 0x0
0x74 ETH_RJB Receive Jabber Register Read/Write 0x0
0x78 ETH_USF Undersize Frame Register Read/Write 0x0
0x7C ETH_SQEE SQE Test Error Register Read/Write 0x0
0x80 ETH_DRFC Discarded RX Frame Register Read/Write 0x0
Address Registers
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Table 16-5. Ethernet MAC Register Mapping (Continued)
Offset Register Name Register Description Read/Write Reset
0x90 ETH_HSH Hash Address High [63:32] Read/Write 0x0
0x94 ETH_HSL Hash Address Low [31:0] Read/Write 0x0
0x98 ETH_SA1L Specific Address 1 Low, First 4 Bytes Read/Write 0x0
0x9C ETH_SA1H Specific Address 1 High, Last 2 Bytes Read/Write 0x0
0xA0 ETH_SA2L Specific Address 2 Low, First 4 Bytes Read/Write 0x0
0xA4 ETH_SA2H Specific Address 2 High, Last 2 Bytes Read/Write 0x0
0xA8 ETH_SA3L Specific Address 3 Low, First 4 Bytes Read/Write 0x0
0xAC ETH_SA3H Specific Address 3 High, Last 2 Bytes Read/Write 0x0
0xB0 ETH_SA4L Specific Address 4 Low, First 4 Bytes Read/Write 0x0
0xB4 ETH_SA4H Specific Address 4 High, Last 2 Bytes Read/Write 0x0
Note: 1. For further details on the statistics registers, see Table 16-6, “Statistics Register Block,” on page 71.
57
16.6.1 EMAC Control Register
Register Name: ETH_CTL
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – BP
7 6 5 4 3 2 1 0
WES ISR CSR MPE TE RE LBL LB
• LB: Loopback
. When set, loopback signal is at high level.
• LBL: Loopback Local
When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK
with ACK divided by 4.
• RE: Receive Enable
When set, enables the Ethernet MAC to receive data.
• TE: Transmit Enable
When set, enables the Ethernet transmitter to send data.
• MPE: Management Port Enable
Set to one to enable the management port. When zero, forces MDIO to high impedance state.
• CSR: Clear Statistics Registers
This bit is write-only. Writing a one clears the statistics registers.
• ISR: Increment Statistics Registers
This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.
• WES: Write Enable for Statistics Registers
Setting this bit to one makes the statistics registers writable for functional test purposes.
• BP: Back Pressure
If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data
(default pattern).
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16.6.2 EMAC Mode Register
Name: ETH_CFG
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – RTY CLK EAE BIG
7 6 5 4 3 2 1 0
UNI MTI NBC CAF – BR FD SPD
• SPD: Speed
Set to 1 to indicate 100 Mbit/sec, 0 for 10 Mbit/sec. Has no other functional effect.
• FD: Full Duplex
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.
• BR: Bit Rate
• CAF: Copy All Frames
When set to 1, all valid frames are received.
• NBC: No Broadcast
When set to 1, frames addressed to the broadcast address of all ones are not received.
• MTI: Multicast Hash Enable
When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the
hash register.
• UNI: Unicast Hash Enable
When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the
hash register.
• BIG: Receive 1522 Bytes
When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.
This bit allows to receive extended Ethernet frame with “VLAN tag” (IEEE 802.3ac)
• EAE: External Address Match Enable
• CLK
The ARM clock is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC
must not exceed 2.5 MHz. At reset this field is set to 10 so that ACK is divided by 32.
CLK MDC
00 ACK divided by 8
01 ACK divided by 16
• RTY: Retry Test

When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.
59
16.6.3 EMAC Status Register
Name: ETH_SR
Access Type: Read-only
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – IDLE MDIO LINK
• LINK
0 = LINK is at 0.
1 = LINK is at 1.
• MDIO
0 = MDIO pin not set.
1 = MDIO pin set.
• IDLE
0 = PHY logic is idle.
1 = PHY logic is running.
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16.6.4 EMAC Transmit Address Register
Name: ETH_TAR
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
7 6 5 4 3 2 1 0
ADDRESS
• ADDRESS: Transmit Address Register

Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the trans-
mit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated.
16.6.5 EMAC Transmit Control Register

Name: ETH_TCR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
NCRC – – – – LEN
7 6 5 4 3 2 1 0
LEN
• LEN: Transmit Frame Length

This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is
asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC
is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the
previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of
bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmission does not start
until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are
loaded.
• NCRC: No CRC
If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not
append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered
so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame cur-
rently being transmitted.
61
16.6.6 EMAC Transmit Status Register
Name: ETH_TSR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– UND COMP BNQ IDLE RLE COL OVR
• OVR: Ethernet Transmit Buffer Overrun

Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ
was not set. Cleared by writing a one to this bit.
• COL: Collision Occurred
Set by the assertion of a collision. Cleared by writing a one to this bit.
• RLE: Retry Limit Exceeded
Cleared by writing a one to this bit.
• IDLE: Transmitter Idle
Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of
the Transmit Control register. This bit is read-only.
• BNQ: Ethernet Transmit Buffer not Queued
Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame
ready to transmit and another in the process of being transmitted. This bit is read-only.
• COMP: Transmit Complete
Set when a frame has been transmitted. Cleared by writing a one to this bit.
• UND: Transmit Underrun
Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC.
Cleared by writing a one to this bit.
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16.6.7 EMAC Receive Buffer Queue Pointer Register
Name: ETH_RBQP
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
7 6 5 4 3 2 1 0
ADDRESS
• ADDRESS: Receive Buffer Queue Pointer

Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive
buffer is forced to word alignment.
16.6.8 EMAC Receive Status Register

Name: ETH_RSR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – OVR REC BNA
• BNA: Buffer Not Available

An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads
the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has
not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.
• REC: Frame Received
One or more frames have been received and placed in memory. Cleared by writing a one to this bit.
• OVR: RX Overrun
The DMA block was unable to store the receive frame to memory, either because the MAC ASB bus was not granted in
time or because an abort occurred. The buffer is recovered if this happens. Cleared by writing a one to this bit.
63
16.6.9 EMAC Interrupt Status Register
Name: ETH_ISR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – ABT ROVR LINK TIDLE
7 6 5 4 3 2 1 0
TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE
• DONE: Management Done

The PHY maintenance register has completed its operation. Cleared on read.
• RCOM: Receive Complete
A frame has been stored in memory. Cleared on read.
• RBNA: Receive Buffer Not Available
Cleared on read.
• TOVR: Transmit Buffer Overrun
Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of
the Transmit Status Register (ETH_TSR) was not set. Cleared on read.
• TUND: Transmit Buffer Underrun
Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted.
Cleared on read.
• RTRY: Retry Limit
Retry limit exceeded. Cleared on read.
• TBRE: Transmit Buffer Register Empty
Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to
transmit and another in the process of being transmitted. Cleared on read.
• TCOM: Transmit Complete
Set when a frame has been transmitted. Cleared on read.
• TIDLE: Transmit Idle
Set when all frames have been transmitted. Cleared on read.
• LINK
Set when LINK pin changes value.
• ROVR: RX Overrun
Set when the RX overrun status bit is set. Cleared on read.
• ABT: Abort
Set when the DMA generates an Abort. Cleared on read.
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16.6.10 EMAC Interrupt Enable Register
Name: ETH_IER
Access Type: Write-only
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• DONE: Management Done Interrupt Enable

• RCOM: Receive Complete Interrupt Enable
• RBNA: Receive Buffer Not Available Interrupt Enable
• TOVR: Transmit Buffer Overrun Interrupt Enable
• TUND: Transmit Buffer Underrun Interrupt Enable
• RTRY: Retry Limit Interrupt Enable
• TBRE: Transmit Buffer Register Empty Interrupt Enable
• TCOM: Transmit Complete Interrupt Enable
• TIDLE: Transmit Idle Interrupt Enable
• LINK: LINK Interrupt Enable
• ROVR: RX Overrun Interrupt Enable
• ABT: Abort Interrupt Enable
0 =No effect.
1 =Enables the corresponding interrupt.
65
16.6.11 EMAC Interrupt Disable Register
Name: ETH_IDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• DONE: Management Done Interrupt Disable

• RCOM: Receive Complete Interrupt Disable
• RBNA: Receive Buffer Not Available Interrupt Disable
• TOVR: Transmit Buffer Overrun Interrupt Disable
• TUND: Transmit Buffer Underrun Interrupt Disable
• RTRY: Retry Limit Interrupt Disable
• TBRE: Transmit Buffer Register Empty Interrupt Disable
• TCOM: Transmit Complete Interrupt Disable
• TIDLE: Transmit Idle Interrupt Disable
• LINK: LINK Interrupt Disable
• ROVR: RX Overrun Interrupt Disable
• ABT: Abort Interrupt Disable
0 =No effect.
1 =Disables the corresponding interrupt.
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16.6.12 EMAC Interrupt Mask Register
Name: ETH_IMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• DONE: Management Done Interrupt Mask

• RCOM: Receive Complete Interrupt Mask
• RBNA: Receive Buffer Not Available Interrupt Mask
• TOVR: Transmit Buffer Overrun Interrupt Mask
• TUND: Transmit Buffer Underrun Interrupt Mask
• RTRY: Retry Limit Interrupt Mask
• TBRE: Transmit Buffer Register Empty Interrupt Mask
• TCOM: Transmit Complete Interrupt Mask
• TIDLE: Transmit Idle Interrupt Mask
• LINK: LINK Interrupt Mask
• ROVR: RX Overrun Interrupt Mask
• ABT: Abort Interrupt Mask
0 =The corresponding interrupt is enabled.
1 =The corresponding interrupt is not enabled.
Important Note: The interrupt is disabled when the corresponding bit is set. This is non-standard with other peripherals of
the product, as generally a mask bit set enables the interrupt.
67
16.6.13 EMAC PHY Maintenance Register
Name: ETH_MAN
31 30 29 28 27 26 25 24
LOW HIGH RW PHYA
23 22 21 20 19 18 17 16
PHYA REGA CODE
15 14 13 12 11 10 9 8
DATA
7 6 5 4 3 2 1 0
DATA
Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO
pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO
pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.
When read, gives current shifted value.
• DATA
For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read
from the PHY.
• CODE
Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.
• REGA
Register address. Specifies the register in the PHY to access.
• PHYA
PHY address. Normally is 0.
• RW
Read/Write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.
• HIGH
Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
• LOW
Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
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16.6.14 EMAC Hash Address High Register
Register Name: ETH_HSH
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Hash address bits 63 to 32.
16.6.15 EMAC Hash Address Low Register

Register Name: ETH_HSL
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Hash address bits 31 to 0.
69
16.6.16 EMAC Specific Address (1, 2, 3 and 4) High Register
Register Name: ETH_SA1H,...ETH_SA4H
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Unicast addresses (1, 2, 3 and 4), Bits 47:32.
16.6.17 EMAC Specific Address (1, 2, 3 and 4) Low Register

Register Name: ETH_SA1L,...ETH_SA4L
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Unicast addresses (1, 2, 3 and 4), Bits 31:0.
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16.7 EMAC Statistics Register Block Registers
These registers reset to zero on a read and remain at all ones when they count to their maxi-
mum value. They should be read frequently enough to prevent loss of data.
The statistics register block contains the registers found in Table 16-5, “Ethernet MAC Regis-
ter Mapping,” on page 56.
Table 16-6. Statistics Register Block

Register Register Description
Name
Frames Transmitted OK
ETH_FRA A 24-bit register counting the number of frames successfully transmitted.
Register
A 16-bit register counting the number of frames experiencing a single collision
Single Collision Frame Register ETH_SCOL
before being transmitted and experiencing no carrier loss nor underrun.
A 16-bit register counting the number of frames experiencing between two and
Multiple Collision Frame
ETH_MCOL fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no
Register
underrun).
A 24-bit register counting the number of good frames received, i.e., address
Frames Received OK Register ETH_OK recognized. A good frame is of length 64 to 1518 bytes and has no FCS,
alignment or code errors.
Frame Check Sequence Error An 8-bit register counting address-recognized frames that are an integral number
ETH_SEQE
Register of bytes long, that have bad CRC and that are 64 to 1518 bytes long.
An 8-bit register counting frames that:
- are address-recognized,
Alignment Error Register ETH_ALE - are not an integral number of bytes long,
- have bad CRC when their length is truncated to an integral number of bytes,
- are between 64 and 1518 bytes long.
A 16-bit register counting the number of frames experiencing deferral due to
Deferred Transmission Frame
ETH_DTE carrier sense active on their first attempt at transmission (no underrun or
Register
collision).
An 8-bit register counting the number of frames that experience a collision after
Late Collision Register ETH_LCOL the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is
counted twice, i.e., both as a collision and a late collision.
An 8-bit register counting the number of frames that failed to be transmitted
Excessive Collision Register ETH_ECOL because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or
underrun).
An 8-bit register counting the number of frames for which carrier sense was not
Carrier Sense Error Register ETH_CSE detected and that were maintained in half-duplex mode one slot time (512 bits)
after the start of transmission (no excessive collision).
An 8-bit register counting the number of frames not transmitted due to a transmit
Transmit Underrun Error
ETH_TUE DMA underrun. If this register is incremented, then no other register is
Register
incremented.
An 8-bit register counting the number of frames that are address-recognized,
Code Error Register ETH_CDE had RXER asserted during reception. If this counter is incremented, then no
other counters are incremented.
An 8-bit register counting the number of frames received exceeding 1518 bytes
Excessive Length Error
ETH_ELR in length but that do not have either a CRC error, an alignment error or a code
Register
error.
An 8-bit register counting the number of frames received exceeding 1518 bytes
Receive Jabber Register ETH_RJB
in length and having either a CRC error, an alignment error or a code error.
71
Table 16-6. Statistics Register Block (Continued)
Register Register Description
Name
An 8-bit register counting the number of frames received that are less than 64
Undersize Frame Register ETH_USF bytes in length but that do not have either a CRC error, an alignment error or a
code error.
An 8-bit register counting the number of frames where pin ECOL was not
SQE Test Error Register ETH_SQEE
asserted within a slot time of pin ETXEN being deasserted.
This 16-bit counter is incremented every time an address-recognized frame is
Discarded RX Frame Register ETH_DRFC
received but cannot be copied to memory because the receive buffer is available.
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17. Advanced Interrupt Controller (AIC)
The AT91C140 integrates the Atmel advanced interrupt controller (AIC).
The interrupt controller is connected to the fast interrupt request (nFIQ) and the standard inter-
rupt request (NIRQ) inputs of the ARM7TDMI processor. The processor’s nFIQ line can only
be asserted by the external fast interrupt request input (FIQ). The nIRQ line can be asserted
by the interrupts generated by the on-chip peripherals and the two external interrupt request
lines, IRQ0 to IRQ1.
An 8-level priority encoder allows the user to define the priority between the different interrupt
sources. Internal sources are programmed to be level-sensitive or edge-triggered. External
sources can be programmed to be positive- or negative-edge triggered or high- or low-level
sensitive.
Figure 17-1. Advanced Interrupt Controller Block Diagram
NFIQ NFIQ
FIQ Source Memorization Manager
Advanced Peripheral Bus Control ARM7TDMI

(APB) Logic Core
Internal Interrupt Sources

Prioritization NIRQ NIRQ
Memorization
External Interrupt Sources Controller Manager
Table 17-1. Interrupt Sources

Interrupt Source Interrupt Name Interrupt Description
0 FIQ Fast Interrupt (LOWP)
1 --
2 SWI Software Interrupt
3 UARTA UART A Interrupt
4 TC0 Timer Channel 0 Interrupt
7 PIOA PIO A Interrupt
8 MACA MAC A Interrupt
9 SPI Serial Peripheral Interface
10 IRQ0 External Interrupt
73
Table 17-1. Interrupt Sources (Continued)
Interrupt Source Interrupt Name Interrupt Description
11 IRQ1 External Interrupt
12 Reserved
13 MACB MAC B Interrupt
14 UARTB UART B Interrupt
15 PIOB PIO B Interrupt
16 - 31 Reserved
17.1 Priority Controller

The nIRQ line is controlled by an 8-level priority encoder. Each source has a programmable
priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with the
highest priority is serviced first. If both interrupts have equal priority, the interrupt with the low-
est interrupt source number is serviced first.
The current priority level is defined as the priority level of the current interrupt at the time the
register AIC_IVR is read (the interrupt which will be serviced). In the case when a higher prior-
ity unmasked interrupt occurs while an interrupt already exists, there are two possible
outcomes depending on whether the AIC_IVR has been read.
1. If the nIRQ line has been asserted but the AIC_IVR has not been read, then the pro-
cessor will read the new higher priority interrupt handler number in the AIC_IVR
register and the current interrupt level is updated.
2. If the processor has already read the AIC_IVR, then the nIRQ line is reasserted.
When the processor has authorized nested interrupts to occur and reads the
AIC_IVR again, it reads the new, higher priority interrupt handler address. At the
same time the current priority value is pushed onto a first-in last-out stack and the
current priority is updated to the higher priority.
When the End of Interrupt Command Register (AIC_EOICR) is written, the current interrupt
level is updated with the current interrupt level from the stack (if any). Hence, at the end of a
higher priority interrupt, the AIC returns to the previous state corresponding to the preceding
lower priority interrupt which had been interrupted.
17.2 Interrupt Handling

The interrupt handler must read the AIC_IVR as soon as possible. This deasserts the nIRQ
request to the processor and clears the interrupt in case it is programmed to be edge-trig-
gered. This permits the AIC to assert the nIRQ line again when a higher priority unmasked
interrupt occurs.
At the end of the interrupt service routine, the End of Interrupt Command Register
(AIC_EOICR) must be written. This allows pending interrupts to be serviced.
17.2.1 Interrupt Masking

Each interrupt source, including FIQ, can be enabled or disabled using the command registers
AIC_IECR and AIC_IDCR. The interrupt mask can be read in the read only register AIC_IMR.
A disabled interrupt does not affect the servicing of other interrupts.
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17.2.2 Interrupt Clearing and Setting
All interrupt sources which are programmed to be edge-triggered (including FIQ) can be indi-
vidually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This
function of the interrupt controller is available for auto-test or software debug purposes.
17.3 Standard Interrupt Sequence

It is assumed that:
• The advanced interrupt controller has been programmed, AIC_SVR registers are loaded
with corresponding interrupt service routine addresses and interrupts are enabled.
When nIRQ is asserted and if the I bit of CPSR is 0, the sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded
in the IRQ link register (R14_IRQ) and the Program Counter (R15) is loaded with
0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts
R14_IRQ, decrementing it by 4.
2. The ARM core enters IRQ mode if it is not already.
3. When the instruction at 0x18 is executed, the Program Counter is loaded with the
value read in the AIC_IVR. Reading the AIC_IVR has the following effects:
Sets the current interrupt to be the pending one with the highest priority. The current level
is the priority level of the current interrupt.
De-asserts the nIRQ line on the processor (even if vectoring is not used, AIC_IVR must be
read in order to de-assert nIRQ).
Automatically clears the interrupt if it has been programmed to be edge-triggered.
Pushes the current level on to the stack.
Returns the AIC_SVR corresponding to the current interrupt.
4. The previous step establishes a connection to the corresponding ISR. This begins by
saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note that the link reg-
ister must be decremented by 4 when it is saved if it is to be restored directly into the
Program Counter at the end of the interrupt.
5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing
re-assertion of the nIRQ to be taken into account by the core. This can occur if an
interrupt with a higher priority than the current one occurs.
6. The interrupt handler then proceeds as required, saving the registers which are used
and restoring them at the end. During this phase, an interrupt of priority higher than
the current level will restart the sequence from step 1. Note that if the interrupt is pro-
grammed to be level-sensitive, the source of the interrupt must be cleared during this
phase.
7. The I bit in the CPSR must be set in order to mask interrupts before exiting to ensure
that the interrupt is completed in an orderly manner.
8. The service routine should then connect to the common exit routine.
9. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to
indicate to the AIC that the current interrupt is finished. This causes the current level
to be popped from the stack, restoring the previous current level if one exists. If
another interrupt with lower or equal priority than the old current level is pending, the
nIRQ line is re-asserted but the interrupt sequence does not immediately start
because the I bit is set in the core.
75
10. The SPSR (SPSR_IRQ) is restored. Finally, the saved value of the Link Register is
restored directly into the PC. This has the effect of returning from the interrupt to the
step previously executed, of loading the CPSR with the stored SPSR and of masking
or unmasking the interrupts depending on the state saved in the SPSR (the previous
state of the ARM core).
Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to
mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is
restored, the mask instruction is completed (IRQ is masked).
17.4 Fast Interrupt

The external FIQ line is the only source which can raise a fast interrupt request to the proces-
sor. Therefore it has no priority controller. It can be programmed to be positive- or negative-
edge triggered or high- or low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written
into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised.
By storing the following instruction at address 0x0000001C, the processor will load the pro-
gram counter with the interrupt handler address stored in the AIC_FVR register.
LDR PC, [PC, #-&F20]
Alternatively, the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
17.4.1 Fast Interrupt Sequence

It is assumed that:
• The advanced interrupt controller has been programmed, AIC_SVR[0] is loaded with the
fast interrupt service routine address and the fast interrupt is enabled.
• Nested fast interrupts are not needed by the user.
When nFIQ is asserted, if the F bit of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded
in the FIQ link register (R14_FIQ) and the Program Counter (R15) is loaded with
0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts
R14_FIQ, decrementing it by 4.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the Program Counter is
loaded with the value read in AIC_FVR. Reading the AIC_FVR has the effect of clear-
ing the fast interrupt (source 0 connected to the FIQ line) if it has been programmed
to be edge-triggered. In this case only, it de-asserts the nFIQ line on the processor.
4. The previous step establishes a connection to the corresponding interrupt service
routine. It is not necessary to save the Link Register (R14_FIQ) and the SPSR
(SPSR_FIQ) if nested fast interrupts are not needed.
5. The interrupt handler can then proceed as required. It is not necessary to save regis-
ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, must be saved before being used and
restored at the end (before the next step). Note that if the fast interrupt is pro-
grammed to be level- sensitive, the source of the interrupt must be cleared during this
phase in order to de-assert the nFIQ line.
6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by 4
(e.g., with instruction SUB PC, LR, #4). This has the effect of returning from the inter-
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rupt to the step previously executed, of loading the CPSR with the SPSR and of
masking or unmasking the fast interrupt depending on the state saved in the SPSR.
Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to
mask FIQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is
restored, the interrupted instruction is completed (FIQ is masked).
17.5 Software Interrupt

Any interrupt source of the AIC can be a software interrupt. It must be programmed to be
edge-triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is
totally independent of the SWI instruction of the ARM7TDMI processor.
17.6 Spurious Interrupt

A spurious interrupt is a signal of very short duration on one of the interrupt input lines. A spu-
rious interrupt also arises when an interrupt is triggered and masked in the same cycle.
17.6.1 Spurious Interrupt Sequence

A spurious interrupt is handled by the following sequence of actions.
1. When an interrupt is active, the AIC asserts the nIRQ (or nFIQ) line and the
ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source disap-
pears, the nIRQ (or nFIQ) line is de-asserted but the ARM7TDMI continues with the
interrupt handler.
2. If the IRQ Vector Register (AIC_IVR) is read when the nIRQ is not asserted, the
AIC_IVR is read with the contents of the Spurious Interrupt Vector Register.
3. If the FIQ Vector Register (AIC_FVR) is read when the nFIQ is not asserted, the
AIC_FVR is read with the contents of the Spurious Interrupt Vector Register.
4. The Spurious ISR must write an End of Interrupt command as a minimum, however, it
is sufficient to write to the End of Interrupt Command Register (AIC_EOICR). Until
the AIC_EOICR write is received by the interrupt controller, the nIRQ (or nFIQ) line is
not re-asserted.
5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine.
6. During a spurious ISR, the AIC_ISR reads 0.
77
17.7 AIC User Interface
Base Address: 0xFF030000 with double mapping at address 0xFFFF F000
Table 17-2. AIC Register Mapping

Offset Register Register Name Access Reset State
0x000 Source Mode Register 0 AIC_SMR0 Read/Write 0
0x004 Source Mode Register 1 AIC_SMR1 Read/Write 0
– – – – –
0x07C Source Mode Register 31 AIC_SMR31 Read/Write 0
0x080 Source Vector Register 0 AIC_SVR0 Read/Write 0
0x084 Source Vector Register 1 AIC_SVR1 Read/Write 0
– – – – –
0xFC0 Source Vector Register 31 AIC_SVR31 Read/Write 0
0x100 IRQ Vector Register AIC_IVR Read-only 0
0x104 FIQ Vector Register AIC_FVR Read-only 0
0x108 Interrupt Status Register AIC_ISR Read-only 0
(1)
0x10C Interrupt Pending Register AIC_IPR Read-only
0x110 Interrupt Mask Register AIC_IMR Read-only 0
0x114 Core Interrupt Status Register AIC_CISR Read-only 0
0x118 Reserved – – –
0x11C Reserved – – –
0x120 Interrupt Enable Command Register AIC_IECR Write-only –
0x124 Interrupt Disable Command Register AIC_IDCR Write-only –
0x128 Interrupt Clear Command Register AIC_ICCR Write-only –
0x12C Interrupt Set Command Register AIC_ISCR Write-only –
0x130 End-of-interrupt Command Register AIC_EOICR Write-only –
0x134 Spurious Interrupt Vector Register AIC_SPU Read/Write 0
Note: 1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset.
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17.7.1 AIC Source Mode Register
Register Name: AIC_SMR0...AIC_SMR31
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– SRCTYPE – – PRIOR
• PRIOR: Priority Level

Programs the priority level for all sources except source 0 (FIQ).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ in the SMR0.
• SRCTYPE: Interrupt Source Type
Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive.
The active level or edge is not programmable for the internal sources.
SRCTYPE Internal Sources External Sources
0 0 Level-sensitive Low-level sensitive
0 1 Edge-triggered Negative-edge triggered
1 0 Level-sensitive High-level sensitive
1 1 Edge-triggered Positive-edge triggered
79
17.7.2 AIC Source Vector Registers
Register Name: AIC_SVR0...AIC_SVR31
31 30 29 28 27 26 25 24
Vector
23 22 21 20 19 18 17 16
Vector
15 14 13 12 11 10 9 8
Vector
7 6 5 4 3 2 1 0
Vector
• Vector
In these registers, the user may store the addresses of the corresponding handler for each interrupt source.
17.7.3 AIC Interrupt Vector Registers

Register Name: AIC_IVR
Reset Value: 0
31 30 29 28 27 26 25 24
IRQV
23 22 21 20 19 18 17 16
IRQV
15 14 13 12 11 10 9 8
IRQV
7 6 5 4 3 2 1 0
IRQV
• IRQV
The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the
current interrupt. The SVR Register (1 to 31) is indexed by the current interrupt number when the IVR register is read.
When there is no interrupt, the IRQ register reads 0.
80 AT91C140
AT91C140
17.7.4 AIC FIQ Vector Register
Register Name: AIC_FVR
Reset Value: 0
31 30 29 28 27 26 25 24
FIQV
23 22 21 20 19 18 17 16
FIQV
15 14 13 12 11 10 9 8
FIQV
7 6 5 4 3 2 1 0
FIQV
• FIQ
The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ.
81
17.7.5 AIC Interrupt Status Register
Register Name: AIC_ISR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – IRQID
• IRQID
The interrupt status register returns the current interrupt source register.
17.7.6 AIC Interrupt Pending Register

Register Name:AIC_IPR
Access Type:Read-only
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA
7 6 5 4 3 2 1 0
PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ
• Interrupt Pending
0 = Corresponding interrupt is not pending.
1 = Corresponding interrupt is pending.
82 AT91C140
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17.7.7 AIC Interrupt Mask Register
Register Name: AIC_IMR
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
PIOB UARTB MACB 0 IRQ1(1) IRQ0 SPI MACA
7 6 5 4 3 2 1 0
• Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
17.7.8 AIC Core Interrupt Status Register

Register Name: AIC_CISR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – NIRQ nFIQ
• nFIQ: nFIQ Status

0 = nFIQ line inactive.
1 = nFIQ line active.
• NIRQ: nIRQ Status
0 = nIRQ line inactive.
1 = nIRQ line active.
83
17.7.9 AIC Interrupt Enable Command Register
Register Name: AIC_IECR
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
17.7.10 AIC Interrupt Disable Command Register

Register Name: AIC_IDCR
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
84 AT91C140
AT91C140
17.7.11 AIC Interrupt Clear Command Register
Register Name: AIC_ICCR
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• Interrupt Clear
0 = No effect.
1 = Clears the corresponding interrupt.
17.7.12 AIC Interrupt Set Command Register

Register Name: AIC_ISCR
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• Interrupt Set
0 = No effect.
1 = Sets the corresponding interrupt.
85
17.7.13 AIC End of Interrupt Command Register
Register Name: AIC_EOICR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – –
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any value can be written as it is only necessary to make a write to this register location to signal the end of interrupt
treatment.
17.7.14 AIC Spurious Interrupt Vector Register

Register Name: AIC_SPU
31 30 29 28 27 26 25 24
SIQV
23 22 21 20 19 18 17 16
SIQV
15 14 13 12 11 10 9 8
SIQV
7 6 5 4 3 2 1 0
SIQV
• SIQV
This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts.
The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted.
The programmed address is read in the AIC_FVR if it is read when the nFIQ line is not asserted.
86 AT91C140
AT91C140
18. Parallel I/O Controller (PIO)
The AT91C140 integrates two PIO controllers, PIOA and PIOB. PIOA controls 15 I/O lines and
PIOB controls 10 I/O lines. Each I/O line can be programmed as an input or an output and can
generate an interrupt on level change.
These pins are used for several functions:
• External I/O for Internal Peripherals
• Keypad Controller Function
• General Purpose I/O
18.1 Output Selection

The user can enable each individual I/O signal as an output with the PIO_OER and PIO_ODR
registers. The output status of the I/O signals can be read in the PIO_OSR register. The direc-
tion defined has an effect only if the pin is configured to be controlled by the PIO controller.
18.2 I/O Levels

Each pin can be configured to be driven high or low. The level is defined in four different ways,
according to the following conditions:
• If a pin is controlled by the PIO controller and is defined as an output, the level is
programmed using the PIO_SODR and PIO_CODR registers. In this case, the
programmed value can be read in the PIO_ODSR register.
• If a pin is controlled by the PIO controller and is not defined as an output, the level is
determined by the external circuit.
• If a pin is not controlled by the PIO controller, the state of the pin is defined by the
peripheral.
In all cases, the level on the pin can be read in the register PIO_PDSR.
18.3 Interrupts
Each parallel I/O can be programmed to generate an interrupt when a level change occurs.
This is controlled by the PIO_IER and PIO_IDR registers which enable/disable the I/O inter-
rupt by setting/clearing the corresponding bit in PIO_IMR. When a change in level occurs, the
corresponding bit in PIO_ISR is set depending on whether the pin is used as a PIO or a
peripheral, and whether it is defined as input or output. If the corresponding interrupt in
PIO_IMR is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
87
18.4 I/O Line Control
Figure 18-1. I/O Line Block Diagram
PIO_OSR
1
Pad Output Enable
Peripheral
0 Output
Enable
PIO_PSR
PIO_ODSR
1
Pad Output
0 Peripheral
Output
Pad
Pad Input
0
Peripheral
Input
1
PIO_PSR
PIO_PDSR
Event
Detection
PIO_ISR
PIO_IMR
PIOIRQ
88 AT91C140
AT91C140
18.5 Parallel I/O Controller (PIO) User Interface
Each individual I/O is associated with a bit position in the parallel I/O user interface registers. Each of these registers is 32
bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read as zero.
Table 18-1. PIO Controller Memory Map

Offset Register Name Description Access Reset Value
0x00 PIO_PER PIO Enable Register Write-only –
0x04 PIO_PDR PIO Disable Register Write-only –
0x08 PIO_PSR PIO Status Register Read-only –
0x10 PIO_OER Output Enable Register Write-only –
0x14 PIO_ODR Output Disable Register Write-only –
0x18 PIO_OSR Output Status Register Read-only 0x0
0x28 – Reserved – 0x0
0x30 PIO_SODR Set Output Data Register Write-only –
0x34 PIO_CODR Clear Output Data Register Write-only –
0x38 PIO_ODSR Output Data Status Register Read-only 0x0
(1)
0x3C PIO_PDSR Pin Data Status Register Read-only See Note 1
0x40 PIO_IER Interrupt Enable Register Write-only –
0x44 PIO_IDR Interrupt Disable Register Write-only –
0x48 PIO_IMR Interrupt Mask Register Read-only –
(2)
0x4C PIO_ISR Interrupt Status Register Read-only See Note 2
Notes: 1. The reset value of this register depends on the level of the external pins at reset.
2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have
occurred on any pins between the reset and the read.
89
18.5.1 PIO Enable Register
Register Name: PIO_PER
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to enable individual pins to be controlled by the PIO controller instead of the associated peripheral.
When the PIO is enabled, the associated peripheral (if any) is held at logic zero.
1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
0 = No effect.
18.5.2 PIO Disable Register

Register Name: PIO_PDR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func-
tion is enabled on the corresponding pin.
1 = Disables PIO control (enables peripheral control) on the corresponding pin.
0 = No effect.
90 AT91C140
AT91C140
18.5.3 PIO Status Register
Register Name: PIO_PSR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or
disabled.
1 = PIO is active on the corresponding line (peripheral is inactive).
0 = PIO is inactive on the corresponding line (peripheral is active).
18.5.4 PIO Output Enable Register

Register Name: PIO_OER
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to enable PIO output drivers. If the pin is driven by a peripheral, there is no effect on the pin but the
information is stored. The register is programmed as follows:
1 = Enables the PIO output on the corresponding pin.
0 = No effect.
91
18.5.5 PIO Output Disable Register
Register Name: PIO_ODR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the
information is stored. The register is programmed as follows:
1 = Disables the PIO output on the corresponding pin.
0 = No effect.
18.5.6 PIO Output Status Register

Register Name: PIO_OSR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The
defined value is effective only if the pin is controlled by the PIO. The register reads as follows:
1 = The corresponding PIO is output on this line.
0 = The corresponding PIO is input on this line.
92 AT91C140
AT91C140
18.5.7 PIO Set Output Data Register
Register Name: PIO_SODR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the
pin is controlled by the PIO. Otherwise, the information is stored.
1 = PIO output data on the corresponding pin is set.
0 = No effect.
18.5.8 PIO Clear Output Data Register

Register Name: PIO_CODR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the
pin is controlled by the PIO. Otherwise, the information is stored.
1 = PIO output data on the corresponding pin is cleared.
0 = No effect.
93
18.5.9 PIO Output Data Status Register
Register Name: PIO_ODSR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec-
tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output.
1 = The output data for the corresponding line is programmed to 1.
0 = The output data for the corresponding line is programmed to 0.
18.5.10 PIO Pin Data Status Register

Register Name: PIO_PDSR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins
are enabled as PIO, peripheral, input or output. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.
94 AT91C140
AT91C140
18.5.11 PIO Interrupt Enable Register
Register Name: PIO_IER
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not.
1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.
0 = No effect.
18.5.12 PIO Interrupt Disable Register

Register Name: PIO_IDR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not.
1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected.
0 = No effect.
95
18.5.13 PIO Interrupt Mask Register
Register Name: PIO_IMR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to
PIO_IER or PIO_IDR.
1 = Interrupt is enabled on the corresponding pin.
0 = Interrupt is not enabled on the corresponding pin.
18.5.14 PIO Interrupt Status Register

Register Name: PIO_ISR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid
whether the PIO is selected for the pin or not and whether the pin is an input or an output.
The register is reset to zero following a read and at reset.
1 = At least one input change has been detected on the corresponding pin since the register was last read.
0 = No input change has been detected on the corresponding pin since the register was last read.
96 AT91C140
AT91C140
19. Universal Asynchronous Receiver Transmitter (UART)
The AT91C140 provides two identical full-duplex Universal Asynchronous Receiver Transmit-
ters, UART A and UART B. These peripherals sit on the APB bus but are also connected to
the ASB bus (and hence external memory) via a dedicated PDC.
The main features are:
• Programmable Baud Rate Generator
• Parity, Framing and Overrun Error Detection
• Line Break Generation and Detection
• Automatic Echo, Local Loopback and Remote Loopback Channel Modes
• Interrupt Generation
• Two Dedicated Peripheral Data Controller Channels
• 6-, 7- and 8-bit Character Length
• Modem Control Signals
19.1 Block Diagram
Figure 19-1. UART Block Diagram
ARM
ASB
Peripheral Data Controller

Peripheral
Bridge
Receive Transmit
Channel Channel
UART
APB PIO
Control Logic
Receiver RXD
UART Interrupt Interrupt Control
ACLK Transmitter TXD

Baud Rate Generator Baud Rate Clock
ACLK/8
SCK
NRTS
Modem Control NCTS
NRI
NDTR
NDSR
NDCD
97
19.2 Pin Description
Each UART channel has external signals as defined in Table 19-1.
Table 19-1. UART Pins

Signal Name Description Type
SCK UART Serial Clock. Can be configured as input or output. See US_MR I/O
TXD Transmit Serial Data Output
RXD Receive Serial Data Input
NRTS Request to Send Output
NCTS Clear to Send Input
NDTR Data Terminal Ready Output
NDSR Data Set Ready Input
NDCD Data Carrier Detect Input
NRI Ring Indicator Input
19.3 Baud Rate Generator

The baud rate generator provides the bit period clock (the baud rate clock) to both the receiver
and the transmitter.
The baud rate generator can select between external and internal clock sources. The external
clock source is SCK. The internal clock sources can be either the ARM Clock (ACLK) or the
ARM Clock divided by 8 (ACLK/8).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
system clock (ACLK) period. The external clock frequency must be at least 2.5 times lower than
the system clock.
The selected clock is divided by 16 times the value (CD) written in US_BRGR (Baud Rate
Generator Register). If US_BRGR is set to 0, the baud rate clock is disabled.
Selected Clock
Baud Rate =
16 x CD
Table 19-2. Clock Generator Table with Crystal Frequency of 16 MHz

Required Baud Rate
(bps) CD Actual CD Actual Baud Rate (bps) Error (bps) % Error
9600 260.42 260 9615.385 15,38 0.16
19200 130.21 130 19230.77 30.77 0.16
38400 65.10 65 38461.54 61.54 0.16
57600 43.41 43 58139.53 539.53 0.94
115200 21.70 22 113636.40 -1163.64 -1.36
98 AT91C140
AT91C140
Figure 19-2. Baud Rate Generator
USCLKS [0] CD
CD
ACLK 0 CLK
16-bit Counter
OUT
ACLK/8 1 >1
1 Divide Baud Rate
by 16 Clock
0 0
19.4 Receiver Operations

The UART detects the start of a received character by sampling the RXD signal until it detects
a valid start bit. A low level (space) on RXD is interpreted as a valid start bit if it is detected for
more than seven cycles of the sampling clock, which is 16 times the baud rate. Hence, a
space which is longer than 7/16 of the bit period is detected as a valid start bit. A space which
is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start
bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period)
so the sampling point is eight cycles (0.5-bit periods) after the start of the bit. The first sam-
pling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was
detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 19-3. Start Bit Detection
16 x Baud
Rate Clock
RXD
Sampling
True Start D0
Detection
Figure 19-4. Character Reception

Example: 8-bit, parity enabled 1 stop
0.5-bit 1-bit
periods period
RXD
Sampling D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit

True Start Detection Parity Bit
99
19.4.1 Receiver Ready
When a complete character is received, it is transferred to the US_RHR and the RXRDY sta-
tus bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE
status bit in US_CSR is set.
19.4.2 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits in
accordance with the field PAR in US_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in US_CSR is set.
19.4.3 Framing Error

If a character is received with a stop bit at low level and with at least one data bit at high level,
a framing error is generated. This sets FRAME in US_CSR.
19.4.4 Time-out
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the UART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR. When this register is set to 0, no time-out is detected. Oth-
erwise, the receiver waits for a first character and then initializes a counter which is
decremented at each bit period and reloaded at each byte reception. When the counter
reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first charac-
ter with the STTTO (Start Time-out) bit in US_CR.
Calculation of time-out duration:
Duration = Value × 4 × Bit Period
19.5 Transmitter
Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the
falling edge of the serial clock.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR, it is transferred to the Shift Register as soon as it is
empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new character is
written to US_THR. If the Transmit Shift Register and US_THR are both empty, the TXEMPTY
bit in US_CSR is set.
Figure 19-5. Character Transmission

Example: 8-bit, parity enabled 1 stop
Baud Rate
Clock
TXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop

Bit Bit Bit
100 AT91C140
AT91C140
19.5.1 Time-guard
The time-guard function allows the transmitter to insert an idle state on the TXD line between
two characters. The duration of the idle state is programmed in US_TTGR. When this register
is set to zero, no time-guard is generated. Otherwise, the transmitter holds a high level on TXD
after each transmitted byte during the number of bit periods programmed in US_TTGR.
Idle state duration = Time-guard x Bit
between two characters value period
19.6 Channel Modes

The UART can be programmed to operate in three different test modes using the field
CHMODE in US_MR.
Automatic echo mode allows bit-by-bit re-transmission. When a bit is received on the RXD
line, it is sent to the TXD line. Programming the transmitter has no effect.
Local loopback mode allows the transmitted characters to be received. TXD and RXD pins are
not used and the output of the transmitter is internally connected to the input of the receiver.
The RXD pin level has no effect and the TXD pin is held high, as in idle state.
Remote loopback mode directly connects the RXD pin to the TXD pin. The transmitter and the
receiver are disabled and have no effect. This mode allows bit-by-bit re-transmission.
Figure 19-6. Channel Modes

Automatic Echo
Receiver RXD
Disabled
Transmitter TXD
Local Loopback
Disabled
Receiver RXD
VDD
Disabled
Transmitter TXD
Remote Loopback VDD

Disabled
Receiver RXD
Disabled
Transmitter TXD
101
19.7 Peripheral Data Controller
Each UART channel is closely connected to a corresponding peripheral data controller chan-
nel. One is dedicated to the receiver, the other is dedicated to the transmitter.
The PDC channel is programmed using US_TPR and US_TCR for the transmitter and
US_RPR and US_RCR for the receiver. The status of the PDC is given in US_CSR by the
ENDTX bit for the transmitter and by the ENDRX bit for the receiver.
The pointer registers US_TPR and US_RPR are used to store the address of the transmit or
receive buffers. The counter registers US_TCR and US_RCR are used to store the size of
these buffers.
The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is
triggered by TXRDY. When a transfer is performed, the counter is decremented and the
pointer is incremented. When the counter reaches 0, the status bit is set (ENDRX for the
receiver, ENDTX for the transmitter in US_CSR) and can be programmed to generate an inter-
rupt. Transfers are then disabled until a new non-zero counter value is programmed.
19.8 Modem Control and Status Signals
19.8.1 NCTS: Clear to Send

When low, this indicates that the modem or data set is ready to exchange data. The NCTS sig-
nal is a modem status input; its conditions can be tested by the CPU reading bit 4 (CTS) of the
Modem Status Register. Bit 4 is the complement of the NCTS signal. Bit 0 (DCTS) of the
Modem Status Register indicates whether the NCTS input has changed state since the previ-
ous read of the Modem Status Register. NCTS has no effect on the transmitter.
19.8.2 NDCD: Data Carrier Detect

When low, this indicates that the data carrier has been detected by the modem or data set.
The NDCD signal is a modem status input; its condition can be tested by the CPU reading bit
7 (DCD) of the Modem Status Register. Bit 7 is the complement of the NDCD signal. Bit 3
(DDCD) of the Modem Status Register indicates whether the NDCD input pin has changed
since the previous reading of the Modem Status Register. NDCD has no effect on the receiver.
19.8.3 NDSR: Data Set Ready

When low, this informs the modem or data set that the UART is ready to communicate. The
NDSR signal is a modem status input; its condition can be tested by the CPU reading bit 5
(DSR) of the Modem Status Register. Bit 5 is the complement of the NDSR signal. Bit 1
(DDSR of the Modem Status Register) indicates whether the NDSR input has changed state
since the previous read of the Modem Status Register.
19.8.4 NDTR: Data Terminal Ready

When low, this informs the modem or data set that the UART is ready to communicate. The
NDTR output signal can be set to active low by programming bit 0 (DTR) of the Modem Con-
trol Register to a high level. A master reset operation sets this signal to its inactive (high) state.
Loop mode operation holds this signal in its inactive state.
19.8.5 NRI: Ring Indicator

When low, this indicates that a telephone ringing signal has been received by the modem or
data set. The NRI signal is a modem status input; its condition can be tested by the CPU read-
ing bit 6 (RI) of the Modem Status Register. Bit 6 is the complement of the NRI signal. Bit 2
102 AT91C140
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(TERI) of the Modem Status Register indicates whether the NRI input signal has changed from
a low to a high state since the previous read of the Modem Status Register.
19.8.6 NRTS: Request to Send

When low, this informs the modem or data set that the UART is ready to exchange data. The
NRTS output signal can be set to an active low by programming bit 1 (RTS) of the Modem
Control Register. A master reset operation sets this signal to its inactive (high) state.
103
19.9 Universal Asynchronous Receiver/Transmitter (UART) User Interface
Table 19-3. UART Memory Map
0x00 US_CR Control Register Write-only –
0x04 US_MR Mode Register Read/Write 0
0x08 US_IER Interrupt Enable Register Write-only –
0x0C US_IDR Interrupt Disable Register Write-only –
0x10 US_IMR Interrupt Mask Register Read-only 0
0x14 US_CSR Channel Status Register Read-only 0x18
0x18 US_RHR Receiver Holding Register Read-only 0
0x1C US_THR Transmitter Holding Register Write-only –
0x20 US_BRGR Baud Rate Generator Register Read/Write 0
0x24 US_RTOR Receiver Time-out Register Read/Write 0
0x28 US_TTGR Transmitter Time-guard Register Read/Write 0
0x30 US_RPR Receive Pointer Register Read/Write 0
0x34 US_RCR Receive Counter Register Read/Write 0
0x38 US_TPR Transmit Pointer Register Read/Write 0
0x3C US_TCR Transmit Counter Register Read/Write 0
0x40 US_MC Modem Control Register Write-only –
0x44 US_MS Modem Status Register Read-only
104 AT91C140
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19.9.1 UART Control Register
Name: US_CR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – RSTSTA
7 6 5 4 3 2 1 0
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.
105
19.9.2 UART Mode Register
Name: US_MR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR –
7 6 5 4 3 2 1 0
CHRL USCLKS – – – –
• USCLKS: Clock Selection
USCLKS Selected Clock

0 0 ACLK
0 1 ACLK/8
1 X External (SCK)
• CHRL: Character Length
CHRL Character Length

0 0 Five bits
0 1 Six bits
1 0 Seven bits
1 1 Eight bits
• PAR: Parity Type
PAR Parity Type

0 0 0 Even parity
0 0 1 Odd parity
0 1 0 Parity forced to 0 (space)
0 1 1 Parity forced to 1 (mark)
1 0 x No parity
• NBSTOP: Number of Stop Bits
NBSTOP
0 0 1 stop bit
0 1 1.5 stop bits
1 0 2 stop bits
1 1 Reserved
106 AT91C140
AT91C140
• CHMODE: Channel Mode
CHMODE Mode Description

0 0 Normal Mode
The UART channel operates as an Rx/Tx
UART.
0 1 Automatic Echo
Receiver data input is connected to TXD pin.
1 0 Local Loopback
Transmitter output signal is connected to
receiver input signal.
1 1 Remote Loopback
RXD pin is internally connected to TXD pin.
107
19.9.3 UART Interrupt Enable Register
Name: US_IER
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY –
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Transfer Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• DMSI: Delta Modem Interrupt
0 = No effect.
108 AT91C140
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19.10 UART Interrupt Disable Register
Name: US_IDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• RXRDY: Disable RXRDY Interrupt

• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Transfer Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• DMSI: Disable Delta Modem Interrupt
0 = No effect.
109
19.11 UART Interrupt Mask Register
Name: US_IMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX RXBRK – RXRDY
• RXRDY: RXRDY Interrupt Mask

• TXRDY: TXRDY Interrupt Mask
• ENDRX: End of Receive Transfer Interrupt Mask
• ENDTX: End of Transmit Transfer Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• DMSI: Delta Modem Status Indication Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
110 AT91C140
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19.11.1 UART Channel Status Register
Name: US_CSR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
• RXRDY: Receiver Ready

0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register.
1 = US_THR is empty and there is no break request pending TSR availability.
Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
• ENDRX: End-of-receive Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active.
• ENDTX: End-of-transmit Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.
• OVRE: Overrun Error
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last
reset status bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted
since the last reset status bits command.
• FRAME: Framing Error
0 = No stop bit has been detected low since the last reset status bits command.
1 = At least one stop bit has been detected low since the last reset status bits command.
• PARE: Parity Error
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit”
command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command.
• TXEMPTY: Transmitter Empty
0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted.
1 = There are no characters in US_THR and the Transmit Shift Register and break is not active.
Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
• DMSI: Delta Modem Status Indication Interrupt
0 = No effect.
1 = There has been a change in the modem status delta bits since the last reset status bits command.
111
19.11.2 UART Receiver Holding Register
Name: US_RHR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
RXCHR
• RXCHR: Received Character

Last character received if RXRDY is set. When number of data bits is less than eight, the bits are right-aligned.
19.11.3 UART Transmitter Holding Register

Name: US_THR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
TXCHR
• TXCHR: Character to be Transmitted

Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than
eight, the bits are right-aligned.
112 AT91C140
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19.11.4 UART Baud Rate Generator Register
Name: US_BRGR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CD
7 6 5 4 3 2 1 0
CD
• CD: Clock Divisor

This register has no effect if synchronous mode is selected with an external clock.
CD Effect
0 Disables clock
1 Clock divisor bypass
2 to 65535 Baud rate = Selected clock/(16 x CD)
113
19.11.5 UART Receive Pointer Register
Name: US_RPR
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR
• RXPTR: Receive Pointer

RXPTR must be loaded with the address of the receive buffer.
19.11.6 UART Receive Counter Register

Name: US_RCR
Reset Value: 0x0
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR
• RXCTR: Receive Counter

RXCTR must be loaded with the size of the receive buffer.
0 =Stop peripheral data transfer dedicated to the receiver.
1 - 65535: Start peripheral data transfer if RXRDY is active.
114 AT91C140
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19.11.7 UART Transmit Pointer Register
Name: US_TPR
Reset Value: 0x0
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR
• TXPTR: Transmit Pointer

TXPTR must be loaded with the address of the transmit buffer.
19.11.8 UART Transmit Counter Register

Name: US_TCR
Reset Value: 0x0
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR
• TXCTR: Transmit Counter

TXCTR must be loaded with the size of the transmit buffer.
0 =Stop peripheral data transfer dedicated to the transmitter.
1 - 65535: Start peripheral data transfer if TXRDY is active.
115
19.11.9 Modem Control Register
Register Name: US_MC
Reset Value: Undefined
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – RTS DTR
This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of
the Control Register are indicated below.
• DTR: Data Terminal Ready
This bit controls the NDTR output. When bit 0 is set to a logic 1, the NDTR output is forced to a logic 0.
When bit 0 is reset to a logic 0, the NDTR output is forced to a logic 1.
The NDTR output of the UART can be applied to an EIA inverting line driver to obtain proper polarity input at the succeed-
ing modem or data set.
• RTS: Request to Send
This bit controls the NRTS output. Bit 1 affects the NRTS output in a manner identical to that described above for bit 0.
116 AT91C140
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19.11.10 Modem Status Register
Register Name: US_MS
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
DCD RI DSR CTS DDCD TERI DDSR DCTS
This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to
this current-state information, four bits of the Modem Status Register provide change information. These bits are set to a
logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the
Modem Status Register.
• DCTS: Delta Clear to Send
Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU.
• DDSR: Delta Data Set Ready
Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU.
• TERI: Trailing Edge Ring Indicator
Bit 2 indicates that the NRI input to the chip has changed from a low to a high state.
• DDCD: Delta Data Carrier Detect
Bit 3 indicates that the NDCD input has changed state.
Note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. This is reflected in the modem
status register.
• CTS: Clear to Send
This bit is the complement of the Clear to Send (NCTS) input.
• DSR: Data Set Ready
This bit is the complement of the Data Set Ready (NDSR) input.
• RI: Ring Indicator
This bit is the complement of the Ring Indicator (NRI) input.
• DCD: Data Carrier Detect
This bit is the complement of the Data Carrier Detect (NDCD) input.
117
20. Timer/Counter (TC)
The AT91C140 features a timer/counter block that includes three identical 16-bit timer/counter
channels. Each channel can be independently programmed to perform a wide range of func-
tions including frequency measurement, event counting, interval measurement, pulse
generation, delay timing and pulse-width modulation.
Each timer/counter channel has three external clock inputs, five internal clock inputs, and two
multi-purpose input/output signals that can be configured by the user. Each channel drives an
internal interrupt signal that can be programmed to generate processor interrupts via the AIC.
The timer/counter block has two global registers which act upon all three TC channels. The
Block Control Register allows the three channels to be started simultaneously with the same
instruction. The Block Mode Register defines the external clock inputs for each timer/counter
channel, allowing them to be chained.
20.1 Block Diagram
Figure 20-1. Timer/Counter Block Diagram
Parallel I/O
Controller
ACLK/2 TCLK0
TCLK0
TCLK1
ACLK/8 TIOA1 TCLK2
TIOA2 XC0 Timer/Counter
ACLK/32 TIOA
TCLK1 XC1 Channel 0 TIOA0 TIOA0
TIOB TIOB0
ACLK/128 TCLK2 XC2 TIOB0
TC0XC0S SYNC
ACLK/1024 INT
TCLK0
TCLK1 XC0 Timer/Counter

TIOA
TIOA0 XC1 Channel 1 TIOA1 TIOA1
TIOB TIOB1
TIOA2 XC2 TIOB1
TCLK2 SYNC
INT
TC1XC1S
TCLK0 XC0 Timer/Counter

TIOA
TCLK1 XC1 Channel 2 TIOA2 TIOA2
TIOB TIOB2
TCLK2 XC2 TIOB2
TIOA0 SYNC
TC2XC2S INT
TIOA1
Timer/Counter Block
Advanced
Interrupt
Controller
118 AT91C140
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20.2 Signal Name Description
Table 20-1. Timer Counter Signal Description

Channel Signal Description Type
XC0, XC1, XC2 External clock inputs I
Capture mode: General-purpose input I
TIOA
Waveform mode: General-purpose output O
Capture mode: General-purpose input I
TIOB
Waveform mode: General-purpose input/output O
INT Interrupt signal output O
SYNC Synchronization input signal I
Block Signal
TCLK0, TCLK1, TCLK2 External clock inputs I
TIOA0 TIOA signal for Channel 0 I/O
TIOB0 TIOB signal for Channel 0 I/O
Note: After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configured to be con-
trolled by the peripheral before being used.
20.3 Description
The three timer/counter channels are independent and identical in operation.
20.3.1 Counter
Each timer/counter channel is organized around a 16-bit counter. The value of the counter is
incremented at each positive edge of the selected clock. When the counter has reached the
value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Sta-
tus Register) is set.
The current value of the counter is accessible in real time by reading TC_CV. The counter can
be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge
of the selected clock.
20.3.2 Clock Selection

At block level, input clock signals of each channel can either be connected to the external
inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0,
TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode).
Each channel can independently select an internal or external clock source for its counter:
• Internal clock signals: ACLK/2, ACLK/8, ACLK/32,
ACLK/128, ACLK/1024
• External clock signals: XC0, XC1 or XC2
119
The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows
counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The
BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
system clock (ACLK) period. The external clock frequency must be at least 2.5 times lower than
the system clock (ACLK).
Figure 20-2. Clock Selection
CLKS
CLKI
ACLK/2
ACLK/8
ACLK/32
ACLK/128
Selected
ACLK/1024
Clock
XC0
XC1
XC2
BURST
20.3.3 Clock Control

The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped.
1. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In capture mode, it can be disabled by an RB load
event if LDBDIS is set to 1 in TC_CMR. In waveform mode, it can be disabled by an
RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the
stop actions have no effect: only a CLKEN command in the Control Register can re-
enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status
Register.
2. The clock can also be started or stopped: a trigger (software, synchro, external or
compare) always starts the clock. The clock can be stopped by an RB load event in
capture mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in waveform mode
(CPCSTOP = 1 in TC_CMR). The start and the stop commands have an effect only if
the clock is enabled.
20.3.4 Timer/Counter Operating Modes

Each timer/counter channel can operate independently in two different modes:
1. Capture mode allows measurement on signals
2. Waveform mode allows wave generation
120 AT91C140
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The timer/counter operating mode is programmed with the WAVE bit in the TC Mode Register.
In capture mode, TIOA and TIOB are configured as inputs. In waveform mode, TIOA is always
configured to be an output and TIOB is an output if it is not selected to be the external trigger.
Figure 20-3. Clock Control

Selected
Clock Trigger
CLKSTA CLKEN CLKDIS
Q S
R
Q S
R
Stop Disable
Counter Event Event
Clock
20.3.5 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common
to both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
1. Software trigger: Each channel has a software trigger, available by setting SWTRG in
TC_CCR.
2. SYNC: Each channel has a synchronization signal, SYNC. When asserted, this sig-
nal has the same effect as a software trigger. The SYNC signals of all channels are
asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
3. Compare RC trigger: RC is implemented in each channel and can provide a trigger
when the counter value matches the RC value if CPCTRG is set in TC_CMR.
The timer/counter channel can also be configured to have an external trigger. In capture
mode, the external trigger signal can be selected between TIOA and TIOB. In waveform
mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1
or XC2. This external event can then be programmed to perform a trigger by setting ENETRG
in TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the system clock
(ACLK) period in order to be detected.
Whatever the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value may not read zero just after a trigger, espe-
cially when a low-frequency signal is selected as the clock.
121
20.4 Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture mode allows the TC Channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are inputs.
Figure 20-4 shows the configuration of the TC Channel when programmed in capture mode.
20.4.1 Capture Registers A and B (RA and RB)

Registers A and B are used as capture registers; thus, they can be loaded with the counter
value when a programmable event occurs on the TIOA signal.
The parameter LDRA in TC_CMR defines the TIOA edge for the loading of Register A, and the
parameter LDRB defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag
(LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.
20.4.2 Trigger Conditions

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external
trigger can be defined.
Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter
ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If
ETRGEDG = 0 (none), the external trigger is disabled.
20.4.3 Status Register

The following bits in the status register are significant in capture operating mode.
• CPCS: RC Compare Status
There has been an RC Compare match at least once since the last read of the status.
• COVFS: Counter Overflow Status
The counter has attempted to count past $FFFF since the last read of the status.
• LOVRS: Load Overrun Status
RA or RB has been loaded at least twice without any read of the corresponding register
since the last read of the status.
• LDRAS: Load RA Status
RA has been loaded at least once without any read since the last read of the status.
• LDRBS: Load RB Status
RB has been loaded at least once without any read since the last read of the status.
• ETRGS: External Trigger Status
An external trigger on TIOA or TIOB has been detected since the last read of the status.
122 AT91C140
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Figure 20-4. Capture Mode
TCCLKS
CLKSTA CLKEN CLKDIS
CLKI
ACLK/2
ACLK/8
ACLK/32
Q S
ACLK/128
ACLK/1024
R
Q S
XC0
R
XC1
XC2
LDBSTOP LDBDIS
BURST
Register C
Capture Capture
1 Register A Register B Compare RC =
16-bit Counter
SWTRG
CLK
OVF
RESET
SYNC Trig
ABETRG
ETRGEDG CPCTRG
MTIOB Edge
Detector
TIOB LDRA LDRB
ETRGS
COVFS
LOVRS
LDRAS
LDRBS
TC_SR
CPCS
MTIOA Edge Edge
Detector Detector
If RA is not loaded
or RB is loaded If RA is loaded
TC_IMR
TIOA
Timer/Counter Channel
INT
20.5 Waveform Operating Mode

This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register).
Waveform operating mode allows the TC channel to generate 1 or 2 PWM signals with the
same frequency and independently programmable duty cycles, or to generate different types
of one-shot or repetitive pulses.
In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an
external event (EEVT parameter in TC_CMR).
Figure 20-5 on page 126 shows the configuration of the TC channel when programmed in
waveform operating mode.
20.5.1 Compare Register A, B and C (RA, RB, and RC)

In waveform operating mode, RA, RB and RC are all used as compare registers.
RA Compare is used to control the TIOA output. RB Compare is used to control the TIOB (if
configured as output). RC Compare can be programmed to control TIOA and/or TIOB outputs.
123
RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the
counter clock (CPCDIS = 1 in TC_CMR).
As in capture mode, RC Compare can also generate a trigger if CPCTRG = 1. A trigger resets
the counter so RC can control the period of PWM waveforms.
20.5.2 External Event/Trigger Conditions

An external event can be programmed to be detected on one of the clock sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
The parameter EEVT in TC_CMR selects the external trigger. The parameter EEVTEDG
defines the trigger edge for each of the possible external triggers (rising, falling or both). If
EEVTEDG is cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output
and the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in
TC_CMR.
As in capture mode, the SYNC signal, the software trigger and the RC compare trigger are
also available as triggers.
20.5.3 Output Controller

The output controller defines the output level changes on TIOA and TIOB following an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC com-
pare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can
be programmed to set, clear or toggle the output as defined in the corresponding parameter in
TC_CMR.
Table 20-2 and Table 20-3 show which parameter in TC_CMR is used to define the effect of
each event.
Table 20-2. TIOA Events

Parameter TIOA Event
ASWTRG Software trigger
AEEVT External event
ACPC RC compare
ACPA RA compare
Table 20-3. TIOB Events

Parameter TIOB Event
BSWTRG Software trigger
BEEVT External event
BCPC RC compare
BCPB RB compare
124 AT91C140
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If two or more events occur at the same time, the priority level is defined as follows:
1. Software trigger
2. External event
3. RC compare
4. RA or RB compare
20.5.4 Status
The following bits in the status register are significant in waveform mode:
• CPAS: RA Compare Status
There has been a RA Compare match at least once since the last read of the status
• CPBS: RB Compare Status
There has been a RB Compare match at least once since the last read of the status
There has been a RC Compare match at least once since the last read of the status
• COVFS: Counter Overflow
Counter has attempted to count past $FFFF since the last read of the status
• ETRGS: External Trigger
External trigger has been detected since the last read of the status
125
126
TCCLKS
CLKSTA CLKEN CLKDIS
ACPC
ACLK/2
CLKI
ACLK/8
ACLK/32
Q S
AT91C140
ACLK/128 CPCDIS MTIOA
ACPA
Figure 20-5. Waveform Mode
ACLK/1024
R
Q S
XC0
R
XC1
TIOA
XC2 CPCSTOP
AEEVT
Output Controller
BURST
Register A Register B Register C
ASWTRG
1 Compare RA = Compare RB = Compare RC =
16-bit Counter
CLK
OVF
RESET
SWTRG
BCPC
SYNC Trig
BCPB MTIOB
CPCTRG
EEVT TIOB
BEEVT
EEVTEDG
ENETRG
Output Controller
CPAS
CPBS
CPCS
TC_SR
ETRGS
COVFS
Edge
Detector BSWTRG
TIOB
TC_IMR
Timer/Counter Channel
INT
AT91C140
20.6 Timer/Counter (TC) User Interface
Table 20-4. TC Global Memory Map
Offset Register Name Channel/Register Access Reset Value
0x00 TC Channel 0 See Table 20-5
0xC0 TC_BCR TC Block Control Register Write-only –
0xC4 TC_BMR TC Block Mode Register Read/Write 0
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are con-
trolled by the registers listed in Table 20-5. The offset of each of the channel registers in Table 20-5 is in relation to the
offset of the corresponding channel as specified in Table 20-4.
Table 20-5. TC Channel Memory Map

0x00 TC_CCR Channel Control Register Write-only –
0x04 TC_CMR Channel Mode Register Read/Write 0
0x08 Reserved –
0x0C Reserved –
0x10 TC_CVR Counter Value Register Read/Write 0
0x14 TC_RA Register A Read/Write(1) 0
(1)
0x18 TC_RB Register B Read/Write 0
0x1C TC_RC Register C Read/Write 0
0x20 TC_SR Status Register Read-only –
0x24 TC_IER Interrupt Enable Register Write-only –
0x28 TC_IDR Interrupt Disable Register Write-only –
0x2C TC_IMR Interrupt Mask Register Read-only 0
Note: 1. Read only if WAVE = 0.
127
20.6.1 TC Block Control Register
Register Name: TC_BCR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – SYNC
• SYNC: Synchro Command

0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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20.6.2 TC Block Mode Register
Register Name: TC_BMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – TC2XC2S TC1XC1S TC0XC0S
• TC0XC0S: External Clock Signal 0 Selection
TC0XC0S Signal Connected to XC0

0 0 TCLK0
0 1 None
1 0 TIOA1
1 1 TIOA2

0 0 TCLK1
0 1 none
1 0 TIOA0
1 1 TIOA2

0 0 TCLK2
0 1 none
1 0 TIOA0
1 1 TIOA1
129
20.6.3 TC Channel Control Register
Register Name: TC_CCR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – SWTRG CLKDIS CLKEN
• CLKEN: Counter Clock Enable Command

0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and clock is started.
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20.6.4 TC Channel Mode Register: Capture Mode
Register Name: TC_CMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS
• TCCLKS: Clock Selection
TCCLKS Clock Selected

0 0 0 ACLK/2
0 0 1 ACLK/8
0 1 0 ACLK/32
0 1 1 ACLK/128
1 0 0 ACLK/1024
1 0 1 XC0
1 1 0 XC1
1 1 1 XC2
• CLKI: Clock Invert

0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the selected clock.
• LDBSTOP: Counter Clock Stopped with RB Loading

0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
131
• ETRGEDG: External Trigger Edge Selection
ETRGEDG Edge
0 0 None
0 1 Rising edge
1 0 Falling edge
1 1 Each edge
• ABETRG: TIOA or TIOB External Trigger Selection

0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
• WAVE
0 = Capture mode is enabled.
1 = Capture mode is disabled (waveform mode is enabled).
• LDRA: RA Loading Selection
LDRA Edge
0 0 None
0 1 Rising edge of TIOA
1 0 Falling edge of TIOA
1 1 Each edge of TIOA
• LDRB: RB Loading Selection
LDRB Edge
0 0 None
0 1 Rising edge of TIOA
1 0 Falling edge of TIOA
1 1 Each edge of TIOA
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20.6.5 TC Channel Mode Register: Waveform Mode
Register Name: TC_CMR
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE CPCTRG – ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS
• TCCLKS: Clock Selection
TCCLKS Clock Selected

0 0 0 ACLK/2
0 0 1 ACLK/8
0 1 0 ACLK/32
0 1 1 ACLK/128
1 0 0 ACLK/1024
1 0 1 XC0
1 1 0 XC1
1 1 1 XC2
• CLKI: Clock Invert

0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
BURST
0 0 The clock is not gated by an external signal.
• CPCSTOP: Counter Clock Stopped with RC Compare

0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
133
• EEVTEDG: External Event Edge Selection
EEVTEDG Edge
0 0 None
0 1 Rising edge
1 0 Falling edge
1 1 Each edge
• EEVT: External Event Selection
Signal Selected as TIOB

EEVT External Event Direction
0 0 TIOB Input(1)
0 1 XC0 Output
1 0 XC1 Output
1 1 XC2 Output
Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
• ENETRG: External Event Trigger Enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the
TIOA output.
1 = The external event resets the counter and starts the counter clock.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
• WAVE
0 = Waveform mode is disabled (Capture mode is enabled).
1 = Waveform mode is enabled.
• ACPA: RA Compare Effect on TIOA
ACPA Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
• ACPC: RC Compare Effect on TIOA
ACPC Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
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• AEEVT: External Event Effect on TIOA
AEEVT Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
• ASWTRG: Software Trigger Effect on TIOA
ASWTRG Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
• BCPB: RB Compare Effect on TIOB
BCPB Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
• BCPC: RC Compare Effect on TIOB
BCPC Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
• BEEVT: External Event Effect on TIOB
BEEVT Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
135
• BSWTRG: Software Trigger Effect on TIOB
BSWTRG Effect
0 0 None
0 1 Set
1 0 Clear
1 1 Toggle
136 AT91C140
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20.6.6 TC Counter Value Register
Register Name: TC_CVR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV
• CV: Counter Value

CV contains the counter value in real-time.
20.6.7 TC Register A
Register Name: TC_RA
Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA
• RA: Register A
RA contains the Register A value in real-time.
20.6.8 TC Register B
Register Name: TC_RB
Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB
• RB: Register B
RB contains the Register B value in real-time.
137
20.6.9 TC Register C
Register Name: TC_RC
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC
• RC: Register C
RC contains the Register C value in real-time.
20.6.10 TC Status Register

Register Name: TC_SR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
• COVFS: Counter Overflow Status

0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-
tus Register if WAVE = 0.
• CPAS: RA Compare Status
0 = RA compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA compare has occurred since the last read of the Status Register if WAVE = 1.
• CPBS: RB Compare Status
0 = RB compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB compare has occurred since the last read of the Status Register if WAVE = 1.
0 = RC compare has not occurred since the last read of the Status Register.
1 = RC compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
138 AT91C140
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• LDRBS: RB Loading Status
0 = RB load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB load has occurred since the last read of the Status Register if WAVE = 0.
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, then TIOA pin is low. If WAVE = 1, then TIOA is driven low.
1 = TIOA is high. If WAVE = 0, then TIOA pin is high. If WAVE = 1, then TIOA is driven high.
• MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, then TIOB pin is low. If WAVE = 1, then TIOB is driven low.
1 = TIOB is high. If WAVE = 0, then TIOB pin is high. If WAVE = 1, then TIOB is driven high.
139
20.6.11 TC Interrupt Enable Register
Register Name: TC_IER
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0

• LOVRS: Load Overrun
• CPAS: RA Compare
• CPBS: RB Compare
• CPCS: RC Compare
• LDRAS: RA Loading
• LDRBS: RB Loading
0 = No effect.
20.6.12 TC Interrupt Disable Register

Register Name: TC_IDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0

0 = No effect.
140 AT91C140
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20.6.13 TC Interrupt Mask Register
Register Name: TC_IMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0

0 = The corresponding interrupt is disabled.
141
21. Serial Peripheral Interface (SPI)
The AT91C140 embeds a Serial Peripheral Interface featuring:
• Four Chip Selects with External Decoder Support Allowing Communication with Up to 15
Peripherals
• Serial Memories, such as DataFlash and 3-wire EEPROMS
• Serial Peripherals, such as ADCS, DACS, LCD Controllers, CAN Controllers And Sensors
• External Co-processors
• Master or Slave Serial Peripheral Bus Interface
• 8- to 16-bit Programmable Data Length Per Chip Select
• Programmable Phase and Polarity Per Chip Select
• Programmable Transfer Delays Between Consecutive Transfers and Between Clock and
Data Per Chip Select
• Programmable Delay Between Consecutive Transfers
• Selectable Mode Fault Detection
• Connection to PDC Channel Capabilities Optimizes Data Transfers
• One Channel for the Receiver, One Channel for the Transmitter
21.1 Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides
communication with external devices in Master or Slave Mode. It also allows communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs.
During a data transfer, one SPI system acts as the “master”' that controls the data flow, while
the other system acts as the “slave'' that has data shifted into and out of it by the master. Dif-
ferent CPUs can take turn being masters (Multiple Master Protocol versus Single Master
Protocol, where one CPU is always the master while all of the others are always slaves), and
one master may simultaneously shift data into multiple slaves. However, only one slave may
drive its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of
the master. There may be no more than one slave transmitting data during any particular
transfer.
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
142 AT91C140
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21.2 Block Diagram
Figure 21-1. Block Diagram
ASB
APB Bridge
PDC
APB
SPCK
MISO
MOSI
ACK
ACK/32 SPI Interface PIO NPCS0/NSS
NPCS1
NPCS2
Interrupt Control
NPCS3
SPI Interrupt
143
21.3 Connections
Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK SPCK
MISO MISO
Slave 0
MOSI MOSI
SPI Master NPCS0 NSS
NPCS1 SPCK
MISO
NPCS2 NC Slave 1
NPCS3 MOSI
NSS
SPCK
MISO
Slave 2
MOSI
NSS
21.4 Pin Name List

Table 21-1. I/O Lines Description
Pin Name Pin Description Type Mode Comments
Master Serial data input to SPI
MISO Master In Slave Out I/O
Slave Serial data output from SPI
Master Serial data output from SPI
MOSI Master Out Slave In I/O
Slave Serial data input to SPI
Master Clock output from SPI
SPCK Serial Clock I/O
Slave Clock input to SPI
NPCS1-NPCS3 Peripheral Chip Selects Input Master Select peripherals
Master Output: Selects peripheral
Peripheral Chip Select/Slave
NPCS0/NSS I/O Master Input: low causes mode fault
Select
Slave Input: chip select for SPI
21.5 Master Mode Operations

When configured in Master Mode, the Serial Peripheral Interface controls data transfers to and
from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s)
and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the core
writes to the SPI_TDR (Transmit Data Register).
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require-
ment for high-priority interrupt servicing. When new data is available in the SPI_TDR, the SPI
144 AT91C140
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continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before
new data is received, the Overrun Error (OVRES) flag is set.
Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status
register to clear it.
The delay between the activation of the chip select and the start of the data transfer (DLYBS),
as well as the delay between each data transfer (DLYBCT), can be programmed for each of
the four external chip selects. All data transfer characteristics, including the two timing values,
are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select Registers).
In Master Mode, the peripheral selection can be defined in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Figure 21-6 and Figure 21-7 show the operation of the SPI in Master Mode. For details con-
cerning the flag and control bits in these diagrams, see ”SPI Chip Select Register” on page
161.
21.5.1 Fixed Peripheral Select

This mode is used for transferring memory blocks without the extra overhead in the transmit
data register to determine the peripheral.
Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Register). The
peripheral is defined by the PCS field in SPI_MR.
This option is only available when the SPI is programmed in Master Mode.
21.5.2 Variable Peripheral Select

Variable Peripheral Select is activated by setting the PS bit to one. The PCS field in SPI_TDR
is used to select the destination peripheral. The data transfer characteristics are changed
when the selected peripheral changes, depending on the associated chip select register.
The PCS field in the SPI_MR has no effect.
This option is available only when the SPI is programmed in Master Mode.
21.5.3 Chip Selects

The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These
lines are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Reg-
ister) selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1).
If Variable Peripheral Select is active, the chip select signals are defined for each transfer in
the PCS field in SPI_TDR. Chip select signals can thus be defined independently for each
transfer.
If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field
PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until
the current transfer is completed, then change the value of PCS in SPI_MR before writing new
data in SPI_TDR.
The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive
Data Register).
By default, all NPCS signals are high (equal to one) before and after each transfer.
145
21.5.4 Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is
driven by an external master on the NPCS[0]/NSS signal.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read
and the SPI is disabled until re-enabled by bit SPIEN in the SPI_CR (Control Register).
By default, Mode Fault Detection is enabled. It is disabled by setting the MODFDIS bit in the
SPI Mode Register.
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21.5.5 Master Mode Flow Diagram
Figure 21-3. Master Mode Flow Diagram

SPI Enable
1
TDRE
0 Fixed peripheral
PS
1 Variable peripheral
NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
Delay DLYBCT
0
TDRE
1 0 Fixed peripheral
PS
NPCS = 0xF
1 Variable peripheral
Delay DLYBCS
Same peripheral
SPI_TDR(PCS)
New peripheral
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
147
21.5.6 Master Mode Block Diagram
Figure 21-4. Master Mode Block Diagram

SPI_MR(DIV32)
ACK 0 SPCK Clock Generator

SPI
Master SPI_CSRx[15:0] SPCK
ACK/32 1 Clock
SPIDIS SPIEN
Q
R
SPI_RDR
PCS RD
LSB MSB
MISO Serializer MOSI
SPI_TDR
PCS TD
NPCS3
NPCS2
NPCS1
SPI_MR(PS)
NPCS0
SPI_MR(PCS) 0
SPI_MR(MSTR)
SPI_SR S
M T R O P
O D D V I
D R R R E
F E F E N
S
SPI_IER
SPI_IDR
SPI_IMR
SPI Interrupt
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21.6 SPI Slave Mode
In Slave Mode, the SPI waits for NSS to go active low before receiving the serial clock from an
external master.
In Slave Mode, CPOL, NCPHA and BITS fields of SPI_CSR0 are used to define the transfer
characteristics. The other Chip Select Registers are not used in Slave Mode.
Figure 21-5. Slave Mode Block Diagram
SPCK
NSS
SPIDIS SPIEN
Q
R
SPI_RDR
RD
LSB MSB
MOSI Serializer MISO
SPI_TDR
TD
SPI_SR S
P T R O
I D D V
E R R R
N E F E
S
SPI_IER
SPI_IDR
SPI_IMR
SPI Interrupt
21.7 Data Transfers

Four modes are used for data transfers. These modes correspond to combinations of a pair of
parameters called clock polarity (CPOL) and clock phase (CPHA) that determine the edges of
149
the clock signal on which the data are driven and sampled. Each of the two parameters has
two possible states, resulting in four possible combinations that are incompatible with one
another. Thus a master/slave pair must use the same parameter pair values to communicate.
If multiple slaves are used and fixed in different configurations, the master must reconfigure
itself each time it needs to communicate with a different slave.
Table 21-2 shows the four modes and corresponding parameter settings.
Table 21-2. SPI Bus Protocol Mode

SPI Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
Figure 21-6 and Figure 21-7 show examples of data transfers.
Figure 21-6. SPI Transfer Format (NCPHA = 1, 8 bits per transfer
SPCK cycle (for reference) 1 2 3 4 5 6 7 8
SPCK
(CPOL=0)
SPCK
(CPOL=1)
MOSI
(from master)
MSB 6 5 4 3 2 1 LSB
MISO
(from slave) MSB 6 5 4 3 2 1 LSB *
NSS (to slave)
* Not defined, but normally MSB of previous character received.
150 AT91C140
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Figure 21-7. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) 1 2 3 4 5 6 7 8
SPCK
(CPOL=0)
SPCK
(CPOL=1)
MOSI
(from master)
MSB 6 5 4 3 2 1 LSB
MISO
(from slave) * MSB 6 5 4 3 2 1 LSB
NSS (to slave)
* Not defined but normally LSB of previous character transmitted.
21.8 Clock Generation

In Master Mode, the SPI Master Clock is either CLOCK or FDIV, as defined by the DIV32 field
of SPI_MR. The SPI baud rate clock is generated by dividing the SPI Master Clock by a value
between 4 and 510. The divisor is defined in the SCBR field in each Chip Select Register. The
transfer speed can thus be defined independently for each chip select signal.
CPOL and NCPHA in the Chip Select Registers define the clock/data relationship between
master and slave devices. CPOL defines the inactive value of the SPCK. NCPHA defines
which edge causes data to change and which edge causes data to be captured.
In Slave Mode, the input clock low and high pulse duration must be longer than two system
clock (CLOCK) periods.
151
21.9 Serial Peripheral Interface (SPI) User Interface
Table 21-3. SPI Memory Map
Offset Register Register Name Access Reset
0x00 Control Register SPI_CR Write-only ---
0x04 Mode Register SPI_MR Read/Write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only ---
0x10 Status Register SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only ---
0x18 Interrupt Disable Register SPI_IDR Write-only ---
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20 Receive Pointer Register SPI_RPR Read/Write 0x0
0x24 Receive Counter Register SPI_RCR Read/Write 0x0
0x28 Transmit Pointer Register SPI_TPR Read/Write 0x0
0x2C Transmit Counter Register SPI_TCR Read/Write 0x0
0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0
0x3C Chip Select Register 3 SPI_CSR3 Read/Write 0x0
152 AT91C140
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21.9.1 SPI Control Register
Name: SPI_CR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
SWRST – – – – – SPIDIS SPIEN
• SPIEN: SPI Enable

0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled
• SWRST: SPI Software Reset
0 = No effect.
1 = Resets the SPI. A software-triggered hardware reset of the SPI interface is performed.
153
21.9.2 SPI Mode Register
Name: SPI_MR
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
LLB – – MODFDIS DIV32 PCSDEC PS MSTR
• MSTR: Master/Slave Mode

0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR3 defines peripheral chip select signals 12 to 15*.
*Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration
to be defined by each chip select register.
• DIV32: Clock Selection
0 = SPI Master Clock equals ACK.
1 = SPI Master Clock equals ACK/32.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only.
154 AT91C140
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• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-over-
lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default.
Otherwise, the following equation determines the delay:
NPCS_to_SCK_Delay = DLYBCS * SPI_Master_Clock_period
155
21.9.3 SPI Receive Data Register
Name: SPI_RDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
RD
7 6 5 4 3 2 1 0
RD
• RD: Receive Data

Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
zero.
156 AT91C140
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21.9.4 SPI Transmit Data Register
Name: SPI_TDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – PCS
15 14 13 12 11 10 9 8
TD
7 6 5 4 3 2 1 0
TD
• TD: Transmit Data

Data to be transmitted by the SPI is stored in this register. Information to be transmitted must be written to the transmit data
register in a right-justified format.
PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
157
21.9.5 SPI Status Register
Name: SPI_SR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – SPIENS
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – ENDTX ENDRX OVRES MODF TDRE RDRF
• RDRF: Receive Data Register Full

0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR.
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR.
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR.
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
158 AT91C140
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21.9.6 SPI Interrupt Enable Register
Name: SPI_IER
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
• RDRF: Receive Data Register Full Interrupt Enable

• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
0 = No effect.
21.9.7 SPI Interrupt Disable Register

Name: SPI_IDR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
• RDRF: Receive Data Register Full Interrupt Disable

• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
0 = No effect.
159
21.9.8 SPI Interrupt Mask Register
Name: SPI_IMR
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
• RDRF: Receive Data Register Full Interrupt Mask

• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
0 = The corresponding interrupt is not enabled.
160 AT91C140
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21.9.9 SPI Chip Select Register
Name: SPI_CSR0... SPI_CSR3
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS – – NCPHA CPOL
• CPOL: Clock Polarity

0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
1 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.
NCPHA determines which edge of SCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS[3:0] Bits Per Transfer

0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
161
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock
(selected between CLOCK and FDIV). The Baud rate is selected by writing a value from 2 to 255 in the field SCBR. The fol-
lowing equation determines the SPCK baud rate:
SPCK Baudrate = SPI_Master_Clock / (2 * SCBR)
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
• DLYBS: Delay Before SCK
This field defines the delay from NPCS valid to the first valid SCK transition.
When DLYBS equals zero, the NPCS valid to SCK transition is 1/2 the SCK clock period.
NPCS_to_SCK_Delay = DLYBS * SPI_Master_Clock_period
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted.
Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period.
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21.9.10 SPI Receive Pointer Register
Register Name: SPI_RPR
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR
• RXPTR: Receive Pointer

RXPTR must be loaded with the address of the receive buffer.
21.9.11 SPI Receive Counter Register

Register Name: SPI_RCR
31 30 29 28 27 26 25 24
-- -- -- -- -- -- -- --
23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- --
15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR
• RXCTR: Receive Counter Register

RXCTR must be loaded with the size of the receive buffer.
0 = Stops peripheral data transfer
1 - 65535 = Start peripheral data transfer if RDRF is active.
163
21.9.12 SPI Transmit Pointer Register
Register Name: SP_TPR
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR
• TXPTR: Transmit Pointer Register

TXPTR must be loaded with the address of the transmit buffer.
21.9.13 SPI Transmit Counter Register

Register Name: SP_TCR
31 30 29 28 27 26 25 24
-- -- -- -- -- -- -- --
23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- --
15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR
• TXCTR: Transmit Counter Register

TXCTR must be loaded with the size of the receive buffer.
0 = Stops peripheral data transfer
1 - 65535 = Start peripheral data transfer if TDRE is active.
164 AT91C140
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22. Mechanical Characteristics and Packaging
22.1 PQFP Packaging Information
Figure 22-1. AT91C140 PQFP Package
For PQFP package data, see Table 22-1 on page 166,
165
22.2 PQFP Package Data
Table 22-1. Package Dimensions for 208-lead PQFP Package (in mm)
Symbol Min Nom Max
A 4.10
A1 0.25
A2 3.20 3.32 3.60
D 31.20 BASIC
D1 28.00 BASIC
E 31.20 BASIC
E1 28.00 BASIC
R2 0.13 0.30
R1 0.13
Q 0° 7°
Q1 0°
Q2 8° Ref
Q3 8° Ref
c 0.11 0.15 0.23
L 0.73 0.88 1.03
L1 1.60 REF
S 0.20
b 0.17 0.20 0.27
e 0.50 BSC
D2 25.50
E2 25.50
Tolerances of form and position
aaa 0.25 0.010
bbb 0.20 0.008
ccc 0.08 0.003
166 AT91C140
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23. Ordering Information
Table 23-1. Ordering Information

Ordering Code Package Package Type Temperature Operating Range
AT91C140-QU-001 PQFP208 Green -40°C to +85°C
167
168 AT91C140
AT91C140
Table of Contents
Features1
1 Description ............................................................................................. 1
2 Block Diagram ....................................................................................... 2
3 Pinout .................................................................................................... 3
3.1Mechanical Overview of the 208-lead PQFP Package ..........................................4
4 Peripheral Multiplexing on PIO Lines .................................................. 5

4.1PIO Controller A Multiplexing ................................................................................6
4.2PIO Controller B Multiplexing ................................................................................6
5 Signal Description ................................................................................ 7
6 ARM7TDMI Core .................................................................................. 10
7 Power Supplies .................................................................................... 10
8 System Controller ............................................................................... 11

8.1Test ......................................................................................................................11
8.2Reset Controller ...................................................................................................11
8.3Clock Generator ...................................................................................................11
8.4Chip ID .................................................................................................................12
8.5System Controller User Interface .........................................................................13
9 Memory Controller (MC) ..................................................................... 16

9.1Architecture ..........................................................................................................16
9.2Memory Map ........................................................................................................17
9.3ARM ASB Arbitration ............................................................................................18
9.4MAC ASB Arbitration ............................................................................................18
9.5ASB-ASB Bridge Arbitration .................................................................................18
9.6Boot Mode ............................................................................................................19
9.7Endianness ..........................................................................................................20
10 Peripherals ........................................................................................... 21
10.1Peripheral Registers ...........................................................................................21
10.2Peripheral Memory Map .....................................................................................22
11 Peripheral Data Controller (PDC) ....................................................... 23

11.1PDC Overview ....................................................................................................23
11.2PDC Channel Priority .........................................................................................23
i
12 Boot Program ...................................................................................... 24
12.1Boot Mode ..........................................................................................................24
12.2Hardware Connection of the DataFlash .............................................................24
12.3Internal Boot Software ........................................................................................24
12.4DataFlash Header Details ..................................................................................25
12.5Reserved Resources ..........................................................................................26
13 External Bus Interface (EBI) ............................................................... 27

13.1Signal Multiplexing ............................................................................................27
14 SDRAM Controller (SDRAMC) ............................................................ 28

14.1Description .........................................................................................................28
14.2Block Diagram ....................................................................................................28
14.3I/O Lines Description .........................................................................................29
14.4Application Example ...........................................................................................29
14.5SDRAM Device Initialization ..............................................................................31
14.6SDRAM Controller Write Cycle ..........................................................................32
14.7SDRAM Controller Read Cycle ..........................................................................33
14.8Border Management ..........................................................................................34
14.9SDRAM Controller Refresh Cycles ....................................................................35
14.10SDRAM User Interface .....................................................................................36
15 Static Memory Controller (SMC) ........................................................ 42

15.1External Memory Mapping .................................................................................42
15.2Pin Description ...................................................................................................42
15.3Byte Write or Byte Select Mode .........................................................................42
15.4Read Protocols ...................................................................................................43
15.5Write Protocol .....................................................................................................44
15.6Wait States .........................................................................................................44
15.7SMC User Interface ............................................................................................45
16 Ethernet MAC (EMAC) ......................................................................... 49

16.1Block Diagram ....................................................................................................49
16.2Media Independent Interface ............................................................................50
16.3Transmit/Receive Operation ..............................................................................50
16.4DMA Operations .................................................................................................52
16.5Address Checking ..............................................................................................55
16.6EMAC User Interface .........................................................................................56
16.7EMAC Statistics Register Block Registers .........................................................71
ii AT91C140
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17 Advanced Interrupt Controller (AIC) .................................................. 73
17.1Priority Controller ...............................................................................................74
17.2Interrupt Handling ...............................................................................................74
17.3Standard Interrupt Sequence .............................................................................75
17.4Fast Interrupt ......................................................................................................76
17.5Software Interrupt ...............................................................................................77
17.6Spurious Interrupt ...............................................................................................77
17.7AIC User Interface ..............................................................................................78
18 Parallel I/O Controller (PIO) ................................................................ 87

18.1Output Selection .................................................................................................87
18.2I/O Levels ...........................................................................................................87
18.3Interrupts ............................................................................................................87
18.4I/O Line Control ..................................................................................................88
18.5Parallel I/O Controller (PIO) User Interface ........................................................89
19 Universal Asynchronous Receiver Transmitter (UART) .................. 97

19.1Block Diagram ....................................................................................................97
19.2Pin Description ...................................................................................................98
19.3Baud Rate Generator .........................................................................................98
19.4Receiver Operations ..........................................................................................99
19.5Transmitter .......................................................................................................100
19.6Channel Modes ................................................................................................101
19.7Peripheral Data Controller ................................................................................102
19.8Modem Control and Status Signals ..................................................................102
19.9Universal Asynchronous Receiver/Transmitter (UART) User Interface ...........104
19.10UART Interrupt Disable Register ....................................................................109
19.11UART Interrupt Mask Register .......................................................................110
20 Timer/Counter (TC) ............................................................................ 118

20.1Block Diagram ..................................................................................................118
20.2Signal Name Description ..................................................................................119
20.3Description .......................................................................................................119
20.4Capture Operating Mode ..................................................................................122
20.5Waveform Operating Mode ..............................................................................123
20.6Timer/Counter (TC) User Interface ..................................................................127
21 Serial Peripheral Interface (SPI) ....................................................... 142

21.1Overview ..........................................................................................................142
iii
21.2Block Diagram ..................................................................................................143
21.3Connections .....................................................................................................144
21.4Pin Name List ..................................................................................................144
21.5Master Mode Operations ..................................................................................144
21.6SPI Slave Mode ...............................................................................................149
21.7Data Transfers .................................................................................................149
21.8Clock Generation .............................................................................................151
21.9Serial Peripheral Interface (SPI) User Interface ...............................................152
22 Ordering Information ........................................................................ 165
23 Mechanical Characteristics and Packaging .................................... 166

23.1PQFP Packaging Information ...........................................................................166
23.2PQFP Package Data ........................................................................................167
Table of Contentsi
Revision Historyv
iv AT91C140
AT91C140
Revision History
Doc. Rev. Date Comments Change Request Ref.

6069A 21-May-04 First issue.
6069B 16-May-05 Changed package to PQFP208. Updated ordering information. CSR 04-420, 05-156
Global, External Bus Interface references to 32-bit changed to 16-bit or CSR 05-403
removed.
Table 3-1, “Pinout for 208-lead PQFP Package,” DBW32 and BO256
changed to GND
Table 5-1, “Signal Description,” DBW32 removed
Global all instances of the following changed
DQM0-DQM3 changed to DQM0-DQM1
NWE0-NWE3 changed to NWE0-NWE1
6069C 01-Sep-05
Signal Waveforms section removed
Data Bus Width section removed
Table 3-1, “Pinout for 208-lead PQFP Package,” Replaced SCLKA, CSR 05-409
FSA, STXA, SRXA by GND or NC
Table 5-1, “Signal Description,” SCKA added to UART description, HIi

PIO descriptions changed.
v
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At91 Arm Thumb Microcontrollers AT91C140: Features

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At91 Arm Thumb Microcontrollers AT91C140: Features

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Features

• ARM7TDMI® ARM® Thumb® Processor Core

MII PHY Ethernet

Interrupt and Advanced USART A Serial Port

USART B Serial Port

Timer/Counter 0 PWM Signals

I/O Lines PIO Controller B

Timer/Counter 2 PWM Signals

2 GND 38 MB_TXD1 74 A16 110 CAS

3 VDDIO 39 MB_TXD2 75 A17 111 NC(1)

4 GND 40 GND 76 A18 112 WE

5 NC(1) 41 MB_TXD3 77 A19B/A0 113 DQM0

6 GND 42 MB_TXEN 78 A20/BA1 114 DQM1

7 NTRST 43 MB_TXCLK 79 A21 115 NC(1)

8 MA_COL 44 MB_RXD0 80 D0 116 GND

9 MA_CRS 45 MB_RXD1 81 D1 117 NC(1)

10 MA_TXER 46 MB_RXD2 82 D2 118 VDDCORE

11 MA_TXD0 47 MB_RXD3 83 D3 119 GND

12 MA_TXD1 48 MB_RXER 84 GND 120 VDDOSC

13 MA_TXD2 49 MB_RXCLK 85 D4 121 PLLRC

14 MA_TXD3 50 MB_RXDV 86 VDDIO 122 GND

15 MA_TXEN 51 MB_MDC 87 D5 123 GND

17 MA_TXCLK 53 GND 89 D7 125 XTALIN

18 GND 54 MB_MDIO 90 D8 126 VDDCORE

19 MA_RXD0 55 MB_LINK 91 D9 127 NCE0

20 MA_RXD1 56 A0 92 D10 128 NCE1

21 MA_RXD2 57 A1 93 D11 129 NCE2

23 MA_RXER 59 A3 95 D13 131 NCE3

24 MA_RXCLK 60 A4 96 D14 132 NWE0

25 GND 61 A5 97 VDDCORE 133 NWE1

26 VDDCORE 62 A6 98 GND 134 NC(1)

27 MA_RXDV 63 A7 99 D15 135 VDDIO

28 MA_MDC 64 A8 100 VDDIO 136 GND

29 MA_MDIO 65 A9 101 GND 137 NC(1)

30 MA_LINK 66 A10 102 VDDIO 138 NWR

31 MB_COL 67 A11 103 NC(1) 139 NSOE

32 MB_CRS 68 A12 104 VDDIO 140 GND

33 GND 69 VDDIO 105 GND 141 VDDCORE

34 VDDCORE 70 GND 106 SDCK 142 VDDIO

35 VDDIO 71 A13 107 SDCS 143 MISO

36 MB_TXER 72 A14 108 SDA10 144 MOSI

146 PA22 162 TCK 178 PA4 194 PB0

147 VDDIO 163 PA19 179 PA3 195 PB1

148 GND 164 VDDCORE 180 PA2 196 PB2

149 NRST 165 GND 181 PA1 197 PB3

150 FIQ 166 PA12 182 PA0 198 PB4

151 IRQ0 167 GND 183 GND 199 PB5

152 TST 168 VDDIO 184 RXDA 200 PB6

153 GND 169 PA11 185 TXDA 201 PB7

154 VDDCORE 170 PA10 186 NRSTA 202 PB8

156 VDDIO 172 PA8 188 NDTRA 204 VDDIO

157 GND 173 PA7 189 NDSRA 205 GND

158 VDDIO 174 PA6 190 NDCDA 206 GND

159 TDO 175 VDDIO 191 RXDB 207 GND

3.1 Mechanical Overview of the 208-lead PQFP Package

Figure 3-1. 208-lead PQFP Package Orientation (Top View)

4.2 PIO Controller B Multiplexing

Synchronous Dynamic SDA10 SDRAM Address Line 10 Output

8.2 Reset Controller