Resume 202304190850

Priyanshu Patel
(M.tech) VLSI & Embedded System Email : priyanshupatel587@gmail.com

Electronics and Communication Engg Dept Phone : +91-8707783532
Sardar Vallabhbhai National Institute of Technology, Surat Date of Birth : 24/11/1995
Objective
• Dynamic and career-oriented engineering professional with experience in Physical Design and Verification. I am looking
for a responsible position as a VLSI Physical Design Engineer or Verification Engineer with a view to utilizing my
technical skills, experience, and willingness toward professional and organizational growth.
Work Experience
Pre Si Validation Engineer from August 2022 to present

–• Project Title: Inline Memory Encryption Engine.
Description: This is Security IP that has been used on the data path to system memory. It works as encryption and
decryption of the data to and from the memory.The security IP supports two AXI master and slave interface for read and
write .The IP is supporting AES-XTS mode with some configurations:
• 1. Encrypt and Decrypt modes.
• 2. Key size of 256 bits for each data stream.
• Role: In this verification work I have worked on making small coverage script files to run regression and worked in signal
exclusions to get 100 % coverage milestone.
• I have worked on the Verdi tool for debugging failing assertion test cases and reported to the team.
• Worked on writing random and directed test cases to achive 100 % functional coverage.
• Ran various regression files to check the coverage status on weekly basis and reported the results to the entire team.
• worked on writing some of the sequences as per the test need.
SOC Design Engineer intern at Intel from June 2021 to April 2022
Project Title: Physical Design of a SOC in 7 nm technology.
Description : The design is a block-level implementation with 7 Macros,3 clocks,15 metal layers, and around 80k standard cells
with multi-voltage supplies and the subsystem has various complex modules that serve different purposes in the design. The
real-time complexity of ASIC design flow is experienced.
• Block Specification - 7nm Technology,15 metal layers,3 clocks, and various macros.
• Role: for one physical block implementation from synthesis to GDS.

perform Synthesis, Sanity Checks, Floorplan, Power Plan, Placement, Trial Route and Congestion Analysis, CTS, detail
Routing, and Timing Closure.
• Multiple releases of the block from the FE Team.Understood the data flow and updated the floor plan accordingly.
• Observed congestion related to high pin density, cell density at corners, and near macros and reported the same to the FE
team which they corrected in the next releases.
• Manual clocks and Macro placement using Fusion compiler tool as per provided specifications.
• Worked on fixing Latency at CTS, Timing, and shorts/opens in the design at Route opt
• Done SPEF extraction and post PNR static timing analysis.

Academic Qualifications
Year Degree/Certificate Institute CGPA/%
2020 - 2022 (M.Tech) VLSI & Embedded System Sardar Vallabhbhai National Institute of 8.42/10
Technology, Surat
2017 (B.Tech) Electronics & Communication Engg University of Allahabad(Under JEE Mains) 71.86%
2012 SSC(XII) UP Board New Standard Public School, Raebareli 83.6%
2010 SSC(X) UP Board New Standard Public School, Raebareli 80.16%
Projects
• Multi-objective Optimization Framework for Analog Circuit Optimization: (Optimization of multiple parameters is re-
quired to get the optimum performance, due to a large number of components on SOC. Various multi-objective opti-
mization techniques like PSO are being used to get optimum performance of the circuit). (current
work )
• Designed 180nm PMOS using Visual TCAD software and studied its properties. (2020 )
• Traffic light controller using Verilog: To control the traffic lights by giving highest priority to “high traffic (2020 )
density road” & less priority to “low traffic density road”.
Technical Skills
• Hardware Description Language: Verilog,System-verilog,UVM
• Good knowledge about Synthesis.
• In-depth knowledge of CMOS fundamentals and CMOS circuits.
• Comprehensive knowledge of ASIC design flow, physical design implementation, physical design strategies, and static
timing analysis.
• Tool Expertise: DC for Synthesis, IC Compiler II for PnR, Prime Time For Static Timing Analysis, Verdi for
debugging the test cases
• Programming Languages: C Language.
Area of Interests
• Physical Design.
• Digital Design
• SOC Design.
• SOC Verification.
• Static Timing Analysis.
• Mos Devices and VLSI Technology.
Courses
• Digital VLSI Design.
• Digital Electronics.
• Static Timing Analysis.
• CMOS.
• Physical Design.
• Basic TCL.
• 8085 Microprocessor.
Achievement and Medals

• District topper in the English subject in my 10th standard in 2010.
• Got best singing solo award in B.Tech fresher in 2013.
• Got first prize in group singing event at “AVIRBHAV” in 2016.
• Cleared Written Test of BARC Exam in 2018.
• Cleared Written Test of ISRO Scientist ’C’ Exam in 2020.
Extra Curricular activities
• Attended “Skill Development Workshop for Verilog/System Verilog” organized by MNIT Jaipur.
• Attended the webinar on VLSI Workshop:Transforming Silicon Industry organized by VLSI system design.
• Volunteer at the chess event in : “AVIRBHAV”,Annual cultural fest of J.K Institute of Applied Physics and Technology
in 2013.
• Head of inter hostel and inter college singing event organized at DR.Sarvepalli Radhakrishnan hostel in 2015.
• Head of singing event at “AVIRBHAV” Annual cultural fest of J.K. Institute of Applied Physics and Technology in 2017.
Present Responsibility
• Currently taking the position of class representative of 2020-2022 Batch.
• Training and Placement Co-Ordinator of the VLSI And Embedded System branch from September 2020 to till now.
Hobbies and Interests

• Singing.
• Interested in doing Electronics projects.
• Public Speaking.
Personal Information
• Languages Known : English,Hindi.
Declaration
I do hereby declare that all the particulars made above are true to the best of my knowledge and belief.
Place:Lucknow Signature :
Priyanshu Patel

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Priyanshu Patel

(M.tech) VLSI & Embedded System Email : priyanshupatel587@gmail.com

Pre Si Validation Engineer from August 2022 to present

• Role: for one physical block implementation from synthesis to GDS.

• Done SPEF extraction and post PNR static timing analysis.

Achievement and Medals

Hobbies and Interests

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