Chapter 4.

Photolithography
Contents

 Overview

 Photolithography Process

Semiconductor Device Processing, Chapter 4 1

 4-1. Overview
Pattern Transfer by Photolithography Process
 A pattern is formed on the light-sensitive materials (photoresist) using
light and transferred from the photoresist (PR) to the layers on the wafer
surface by chemical or plasma etching
 Therefore, patterning process includes mask fabrication for light
exposure, photolithographic process, and etching

Semiconductor Device Processing, Chapter 4 2

 Process Flow for Patterning

Expose pattern
Clean wafers
(Thin Develop (Photo-
Film Deposit layers: lithography)
Process) metal, oxide,
Hard bake
etc.
(post-bake)

Coat resist
Etching (Etching)

(Photo- Soft bake

Remove resist
(pre-bake)
lithography)
Align Masks

Semiconductor Device Processing, Chapter 4 3

 Photolithographic Process for Patterning

Semiconductor Device Processing, Chapter 4 4

 Photomask

 A stencil is used to repeatedly generate

a desired pattern on resist-coated wafer
Reticle(10X)
 A glass plate with Cr pattern as a stencil
 Light-field and dark-field masks
 Reticle : unit mask pattern usually
magnified of the real pattern size (10X,
5X)
 Photomask : repeated pattern in real size
Photomask

Light field Dark field

Cr
Semiconductor Device Processing, Chapter 4 5
 Photomask Fabrication Procedure

Semiconductor Device Processing, Chapter 4 6

 Mask Fabrication (I)

 Composite computer graphics plot of all masks for IC

Semiconductor Device Processing, Chapter 4 7

 Mask Fabrication (II)
 10x reticle of metal-level mask
- An optical pattern generator uses a flash lamp to expose the series of
rectangles composing the mask image directly onto a photographic
plate called the “reticle” / reduce the reticle image to the final size
- In modern technology, direct laser or e-beam writing is used to define
the pattern on the reticle or mask using the same lithographic
techniques

Semiconductor Device Processing, Chapter 4 8

 Mask Fabrication (III)
 Final-size emulsion mask with 400 copies of the metal level of the IC
- Final master copy is made in metal(chrome) on a glass plate
(photographic process)
- Working emulsion masks are made from the chrome master (in case
of contact printing)
- Not used in the current technology

Semiconductor Device Processing, Chapter 4 9

 4-2. Photolithography Process
Process Flow of Patterning

Thin film deposition PR coating exposure development etching

Semiconductor Device Processing, Chapter 4 10

 Detailed Photolithography Process

HMDS Cooling1 PR coating Soft Bake Cooling2

COATER
Deposition Edge
treatment

PR strip
Align
STEPPER
IIP Etching Rework
Exposure
Expose

DEVELOPER
Inspection
CD Hard Bake Develop Cooling P.E.B

Semiconductor Device Processing, Chapter 4 11

 Clean Room

 A clean room is needed

U.S.federal Standard 209b

for clean room classification

Semiconductor Device Processing, Chapter 4 12

 Wafer and Wafer Cleaning
 Wafer flat standard  The pattern of particles on the wafer can
be transferred to the wafer during
lithographic process! ⇒ need cleaning

(not used for 300mm wafers

 has a small “notch”)
Semiconductor Device Processing, Chapter 4 13
 Photoresist

 Photoresist : a light sensitive organic material

 Components
- Resin :
 Hydrocarbon, inactive base of the resist
- Photoactive compound (PAC) :
 Change to chemically soluble/insoluble upon light exposure
 Inhibitor before exposure
 Sensitizer upon exposure
- Solvent :
 Control mechanical property i.e. adjust viscosity
 Enable spin coating

Semiconductor Device Processing, Chapter 4 14

 Photoresist Tone

 PR tone
- Positive: rupture or chain scission by photochemical reaction under
illumination ⇒ exposed areas become soluble in developer
- Negative: cross-linking or photochemical reaction ⇒ exposed areas
become insoluble in developer

Semiconductor Device Processing, Chapter 4 15

 Positive Resist

 AZ-1350, AZ-240000, Kodak204, Shipley S-1400

 Advantages Novolac (resin)

- High resolution OH
CH3OH
CH3
- Good dry etch resistance
- No oxygen sensitivity CH2 CH2 CH2
O
- Thermally stable
N2
 Disadvantages Diazoquinone
- Medium exposure time (PAC)
- Melting under high dose implantation SO2

 Composition
- Base: a thick resin (novolac)
- Sensitizer (PAC): DQ (diazoquinones) CH3 C CH3
- Solvent

Semiconductor Device Processing, Chapter 4 16

 Negative Resist

 Photoactive compound reacts with the polymer to form crosslinks

between rubber molecule during exposure
 Kodak747, SU-8, KMPR
 Advantages
- Short exposure time
- Good adhesion with SiO2
- Low cost
 Disadvantages
- Low resolution
- Swelling during developing
 Composition
- Base: cyclized rubber resin
- Sensitizer (PAC): bis-arylazide
- Solvent
Semiconductor Device Processing, Chapter 4 17
 Photoresist Coating

 Spin coating
- Wafer is held on a vacuum chuck
- Spin with 1000 - 5000 rpm
- Drop the liquid form of photoresist
- Resist spreads by centrifugal force

Semiconductor Device Processing, Chapter 4 18

 Soft Baking and Mask Alignment
 Soft baking (prebaking)
- Improve adhesion
- Remove solvent from the resist
- 10 - 30 min in an oven at 80 - 90°C
- Convection oven, microwave/IR oven, vacuum hot plate

 Mask Alingment
- Computer-controlled alignment
- Use alignment marks

Semiconductor Device Processing, Chapter 4 19

 Exposure (Light source)

(refractive)
Near UV
kλ
R= 1
NA Deep UV

(electrostatic)
(reflective or diffractive)
(electrostatic)
(electrostatic)
(reflective)
Semiconductor Device Processing, Chapter 4 20
 Exposure (Exposure Systems)

Contact Printing Proximity Printing Projection Printing

Light
Source

Optical
System

Mask
Photoresist
Si Wafer

Usually 4X or 5X
1:1 Exposure Systems Reduction

Semiconductor Device Processing, Chapter 4 21

 Exposure (Comparison of Exposure Systems )

Exposure Contact Printing Proximity Printing Projection

systems Printing

Pros.  High resolution  Trade-off  High resolution

capable between resolution and low defect
 Simple and and defect density density
cheap process

Cons.  Particle  Resolution is  Sophisticated

contamination, degraded due to optics and
damage in PR and the diffraction expensive
mask effects hardware
 Alignment
limitation

Semiconductor Device Processing, Chapter 4 22

 Exposure (Exposing Methods)
 1:1 full field scanning optical projection
- High throughput
- Resolution limit (minimum feature size > 3 µm)
 For large-diameter wafer with submicron features, uniform exposure and maintaining
alignment are difficult ⇒ exposure of individual die pattern on the wafer directly
 Step and repeat reduction projection  “stepper”
- Repetition of single chip exposure
- Not limited by the wafer size
 Step and scan projection  “scanner”
- step and scanning for each die

Semiconductor Device Processing, Chapter 4 23

 Exposure (Resolution in Projection Printing)
“Minimum resolved dimension with a grating mask”

k1λ
R=
NA

Experimentally determined parameter, 0.6~0.8

(resist performance, process conditions, mask
k1
aligner optics)
λ Wavelength of the light

NA = n sin α Numerical aperture of the imaging lens system

Semiconductor Device Processing, Chapter 4 24

 Exposure (Depth of Focus (DOF))
(optical path difference)

a virtual aperture

k2λ
DOF = ±δ = ±
(NA) 2
● Large DOF is needed to ensure that the image stays in focus over
the entire field
● Small DOF values require expensive planarization process
● Trade-off is needed between “R” and “DOF”
Semiconductor Device Processing, Chapter 4 25
 Exposure (Reflection issue)
 Problems in exposure
- Standing wave effect
 Interference between incident and reflected beam from
resist/substrate interface
 Nonuniform exposure
 Solutions:
ARC (anti-reflective coating): organic or inorganic
PEB (post-exposure bake)

Semiconductor Device Processing, Chapter 4 26

 Development to Photoresist Removal
 Development
- Developer
 For positive resist: alkaline solution diluted with water
 For negative resist: organic solvent
 Hard baking
- Annealing in an oven at 120-180°C for 20-30 min
- Harden the photoresist
- Remove residual solvent
- Improve adhesion and increase dry etch resistance
 Etching
- Wet etching or dry (plasma) etching
 Photoresist removal
- Wet process
- Dry process: remove the resist by plasma (dry) ashing (burning) in the
oxygen-based plasma system

Semiconductor Device Processing, Chapter 4 27

 Evolution of Photolithography Technology

, EUVL

(immersion)

Semiconductor Device Processing, Chapter 4 28

 Potential Solution of Future Litho.
ITRS Roadmap (2005)

Semiconductor Device Processing, Chapter 4 29

 RET (Resolution Enhancement Techniques)

ARC (Anti Reflective Coating)

Semiconductor Device Processing, Chapter 4 30

 RET (Resolution Enhancement Techniques)

PSM (Phase Shift Mask)

phase
phase

intensity intensity

Semiconductor Device Processing, Chapter 4 31

 RET (Resolution Enhancement Techniques)

OPC (Optical Proximity Correction)

Semiconductor Device Processing, Chapter 4 32

 RET (Resolution Enhancement Techniques)

OAI (Off Axis Illumination)

0-th order, ±1st order 0-th order, one of the ±1st order
For very small feature, ±1st order When the symmetric two beams pass
beams are rejected due to larger through the lens, the highest resolution
acceptance angle  gratings not resolved is obtained.

Semiconductor Device Processing, Chapter 4 33

 RET (Resolution Enhancement Techniques)

Immersion lithography (high NA)

 Interpose a liquid medium between the optics and the wafer surface,
replacing the usual air gap
 This liquid (ultra-pure, degassed water ) has a refractive index greater
than one
kλ kλ
R= 1 = 1
NA n sin α
0.25 ×193
For air R= = 52nm
0.93
For water
0.25 ×193
R= = 35nm
1.47 × 0.93

Semiconductor Device Processing, Chapter 4 34

 NGL (Next-generation Lithography)

EUVL (Extreme Ultraviolet Lithography)

© Sandia
Semiconductor Device Processing, Chapter 4 35
 NGL (Next-generation Lithography)

Mirror Optical vs. EUV mask(reticle)

Reflectivity ~ 68% for Mo/Si ML

Semiconductor Device Processing, Chapter 4 36

 NGL (Next-generation Lithography)

EPL (Electron Projection lithography)

• SCALPEL (Scattering with Angular Limitation Projection E-Beam Lithography)

Semiconductor Device Processing, Chapter 4 37