XMC Scu

1 /**
2 * @file xmc_scu.h
3 * @date 2015-06-20
4 *
5 * @cond
6
*************************************************************************************
********************************
7 * XMClib v2.0.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list
of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the
distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be
used to endorse or promote
22 * products derived from this software without specific prior written
permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share
modifications, enhancements or bug fixes with
33 * Infineon Technologies AG
dave@infineon.com).
34
*************************************************************************************
********************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial 
41 *
42 * 2015-05-20:
43 * - Documentation improved 
44 * - XMC_ASSERT() hanging issues have fixed for XMC4 devices. 
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API
48 * - Removed STATIC_INLINE property for the below APIs and declared as void
49 * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,
50 * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,
51 * XMC_SCU_INTERUPT_ClearEventStatus
52 *
53 * @endcond
54 *
55 */
56 #ifndef XMC_SCU_H
57 #define XMC_SCU_H
58
59 /*************************************************************************************
********************************
60 * HEADER FILES
61
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62 #include <xmc_common.h>
63
64 /**
65 * @addtogroup XMClib XMC Peripheral Library
66 * @{
67 */
68
69 /**
70 * @addtogroup SCU
71 * @brief System Control Unit(SCU) driver for XMC microcontroller family.
72 *
73 * System control unit is the SoC power, reset and a clock manager with additional
responsibility of
74 * providing system stability protection and other auxiliary functions. 
75 * SCU provides the following features,
76 * -# Power control
77 \if XMC4
78 * -# Hibernate control
79 \endif
80 * -# Reset control
81 * -# Clock control
82 * -# Miscellaneous control(boot mode, system interrupts etc.) 
83 *
84 * The SCU driver is divided in to clock control logic, reset control logic, system
interrupt control logic
85 \if XMC4
86 * , hibernate control logic, trap control logic, parity control logic
87 \endif
88 * and miscellaneous control logic. 
89 *
90 * Clock driver features:
91 * -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API
XMC_SCU_CLOCK_Init()
92 \if XMC4
93 * -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL
94 * -# Allows selection of clock source for system PLL,
XMC_SCU_CLOCK_GetSystemPllClockSource()
95 * -# Provides APIs for configuring different module clock frequencies
XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()
96 * -# Allows selection of clock source for external output,
XMC_SCU_CLOCK_SetExternalOutputClockSource()
97 * -# Provides APIs for enabling external high power oscillator and ultra low power
oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(),
XMC_SCU_CLOCK_EnableLowPowerOscillator()
98 * -# Provides APIs for getting various clock frequencies
XMC_SCU_CLOCK_GetPeripheralClockFrequency(),
99 XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency() 
100 \endif
101 \if XMC1
102 * -# Allows selection of peripheral clock frequency,
XMC_SCU_CLOCK_SetFastPeripheralClockSource()
103 * -# Provides API to get the peripheral clock frequency,
XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()
104 \endif
105 *
106 * Reset driver features:
107 \if XMC4
108 * -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(),
XMC_SCU_RESET_DeassertPeripheralReset()
109 * -# Allows configuration of NMI generation for selected events,
XMC_SCU_INTERRUPT_EnableNmiRequest()
110 \endif
111 \if XMC1
112 * -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()
113 * -# Allows to configure multiple sources for reset,
XMC_SCU_RESET_EnableResetRequest()
114 \endif 
115 *
116 * Interrupt driver features:
117 * -# Provides APIs for enabling/ disabling interrupt event generation
XMC_SCU_INTERRUPT_EnableEvent(),
118 XMC_SCU_INTERRUPT_DisableEvent()
119 * -# Provides API for registering callback function for events
XMC_SCU_INTERRUPT_SetEventHandler() 
120 *
121 \if XMC4
122 * Hibernate driver features:
123 * -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(),
XMC_SCU_HIB_DisableHibernateDomain()
124 * -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()
125 * -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()
126 * -# Provides API for enabling slow internal clock used for backup clock,
XMC_SCU_HIB_EnableInternalSlowClock() 
127 *
128 * Trap driver features:
129 * -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(),
XMC_SCU_TRAP_Trigger() 
130 *
131 * Parity driver features:
132 * -# Parity error generated by on-chip RAM can be monitored,
XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()
133 * -# Allows configuration of trap generation on detection of parity error,
XMC_SCU_PARITY_EnableTrapGeneration()
134 *
135 * Power driver features:
136 * -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(),
XMC_SCU_POWER_DisableUsb()
137 \endif
138 *
139 * Miscellaneous features:
140 * -# Allows to trigger multiple capture compare unit(CCU) channels to be started
together XMC_SCU_SetCcuTriggerHigh()
141 \if XMC4
142 * -# Enables configuration of out of range comparator (ORC)
XMC_SCU_EnableOutOfRangeComparator()
143 * -# Enables configuration of die temperature sensor
XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()
144 * -# Enables configuration of device boot mode XMC_SCU_SetBootMode() 
145 \endif
146 \if XMC1
147 * -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(),
XMC_SCU_SetRawTempLimits()
148 * -# Allows configuring supply monitor unit using the structure
XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()
149 * -# Allows handling of protected bits XMC_SCU_LockProtectedBits(),
XMC_SCU_UnlockProtectedBits() 
150 \endif
151 * @{
152 */
153
154 /*************************************************************************************
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155 * MACROS
156
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157
158 /*************************************************************************************
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159 * ENUMS
160
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161 /**
162 * Defines the status of SCU API execution, used to verify the SCU related API calls.
163 */
164 typedef enum XMC_SCU_STATUS
165 {
166 XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/
167 XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot
fulfill request, this value is returned. */
168 XMC_SCU_STATUS_BUSY , /**< Cannot execute the SCU related operation request
because
169 another operation is in progress. \a
XMC_SCU_STATUS_BUSY is returned when API is busy
170 processing another request. */
171 } XMC_SCU_STATUS_t;
172
173
174 /*************************************************************************************
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175 * DATA TYPES
176
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177
178 /**
179 * Function pointer type used for registering callback functions on SCU event
occurence.
180 */
181 typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);
182
183 /*************************************************************************************
********************************
184 * DEVICE EXTENSIONS
185
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186
187 #if (UC_FAMILY == XMC1)
188 #include <xmc1_scu.h>
189 #elif (UC_FAMILY == XMC4)
190 #include <xmc4_scu.h>
191 #else
192 #error "Unspecified chipset"
193 #endif
194
195 /*************************************************************************************
********************************
196 * API Prototypes
197
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*******************************/
198
199 #ifdef __cplusplus
200 extern "C" {
201 #endif
202
203
204 /**
205 *
206 * @param trigger CCU slices to be triggered synchronously via software. The value
is a bitmask of CCU slice bits
207 * in the register CCUCON. 
208 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of
individual CCU slices. Multiple slices can be
209 * combined using \a OR operation.
210 *
211 * @return None
212 *
213 * \parDescription 
214 * Generates active edge(low to high) trigger for multiple CCU units at the same
time.\n\n
215 * Before executing this API, all the required CCU timers should configure external
start.
216 * The edge of the start signal should be selected as active edge.
217 * The input signal for the CCU slice should be selected as SCU input.
218 * The above mentioned configurations can be made using the CCU LLD API
XMC_CCU4_SLICE_StartConfig().
219 * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before
triggering
220 * the timer using this API. 
221 * \parRelated APIs: 
222 * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(),
XMC_SCU_SetCcuTriggerLow()\n\n\n
223 */
224 __STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger)
225 {
226 SCU_GENERAL->CCUCON |= (uint32_t)trigger;
227 }
228
229 /**
230 *
231 * @param trigger CCU slices to be triggered synchronously via software. The value
is a bitmask of CCU slice bits
232 * in the register CCUCON. 
233 * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of
individual CCU slices. Multiple slices can be
234 * combined using \a OR operation.
235 *
236 * @return None
237 *
239 * Generates passive edge(high to low) trigger for multiple CCU units at the same
time.\n\n
240 * Before executing this API, all the required CCU timers should configure external
start.
241 * The edge of the start signal should be selected as passive edge.
242 * The input signal for the CCU slice should be selected as SCU input.
243 * The above mentioned configurations can be made using the CCU LLD API
XMC_CCU4_SLICE_StartConfig().
244 * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before
triggering
245 * the timer using this API. 
247 * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(),
XMC_SCU_SetCcuTriggerHigh()\n\n\n
248 */
249 __STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger)
250 {
251 SCU_GENERAL->CCUCON &= (uint32_t)~trigger;
252 }
253
254 /**
255 *
256 * @param config Pointer to structure holding the clock prescaler values and divider
values for
257 * configuring clock generators and clock tree.\n
258 * \b Range: Configure the members of structure @ref
XMC_SCU_CLOCK_CONFIG_t for various
259 * parameters of clock setup.
260 *
261 * @return None
262 *
264 * Initializes clock generators and clock tree.\n\n
265 * \if XMC1
266 * Peripheral clock and system clock are configured based on the input configuration
\a config.
267 * The system clock frequency is tuned by configuring the FDIV and IDIV values of
CLKCR register.
268 * The values of FDIV and IDIV can be provided as part of input configuration.
269 * The PCLK divider determines the ratio of peripheral clock to the system clock.
270 * The source of RTC clock is set based on the input configuration.
271 * \a SystemCoreClock variable will be updated with the value of
272 * system clock frequency. Access to protected bit fields are handled internally.
273 * \endif
274 * \if XMC4
275 * Enables the high precision oscillator(fOHP) input and configures the system and
peripheral clock frequencies.
276 * Based on the system clock source selected in \a config, either fPLL or fOFI will
be chosen as system clock.
277 * Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve
target frequency.
278 * The clock dividers for CPU, CCU and peripheral clocks will be set based on the
input configuration.
279 * The \a SystemCoreClock variable is set with the value of system clock frequency.
280 * \endif
282 * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency()
\n\n\n
283 */
284 void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);
285
286 /**
287 *
288 * @param event Bit mask of the event to enable. \b Range: Use type @ref
XMC_SCU_INTERRUPT_EVENT_t
289 * for providing the input value. Multiple events can be combined
using the \a OR operation.
290 *
291 * @return None
292 *
294 * Enables the generation of interrupt for the input events.\n\n
295 * The events are enabled by setting the respective bit fields in the SRMSK register.
\n
296 * Note: User should separately enable the NVIC node responsible for handling the SCU
interrupt.
297 * The interrupt will be generated when the respective event occurs.
299 * NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n
300 */
301 void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
302
303
304 /**
305 *
306 * @param event Bit mask of the event to disable. \b Range: Use type @ref
308 *
309 * @return None
310 *
312 * Disables generation of interrupt on occurence of the input event.\n\n
313 * The events are disabled by resetting the respective bit fields in the SRMSK
register. \n
315 * NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n
316 */
317 void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
318
319 /**
320 *
321 * @param event Bit mask of the event to be triggered. \b Range: Use type @ref
323 *
324 * @return None
325 *
327 * Triggers the event as if the hardware raised it.\n\n
328 * Event will be triggered by setting the respective bitfield in the SRSET register.\n
329 * Note: User should enable the NVIC node that handles the respective event for
interrupt generation.
331 * NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(),
XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n
332 */
333 void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
334
335 /**
336 * @return uint32_t Status of the SCU events.
337 *
339 * Provides the status of all SCU events.\n\n
340 * The status is read from the SRRAW register. To check the status of a particular
341 * event, the returned value should be masked with the bit mask of the event. The
bitmask
342 * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple
events'
343 * status can be checked by combining the bit masks using \a OR operation.
344 * After detecting the event, the event status should be cleared using software to
detect the event again.
346 * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(),
XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
347 */
348 XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void);
349
350 /**
351 *
352 * @param event Bit mask of the events to clear. \b Range: Use type @ref
354 *
355 * @return None
356 *
358 * Clears the event status bit in SRRAW register.\n\n
359 * The events are cleared by writing value 1 to their bit positions in the SRCLR
register.
360 * The API can be used when polling method is used. After detecting the event, the
event status
361 * should be cleared using software to detect the event again.
362 *
364 * XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n
365 */
366 void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);
367
368 /**
369 *
370 * @return uint32_t Status representing the reason for device reset.
371 *
373 * Provides the value representing the reason for device reset.\n\n
374 * The return value is an encoded word, which can indicate multiple reasons for the
last reset. Each bit position of the
375 * returned word is representative of a last reset cause. The returned value should
be appropriately masked to check
376 * the cause of reset.
377 * The cause of the last reset gets automatically stored in
378 * the \a SCU_RSTSTAT register. The reset status shall be reset after each
379 * startup in order to ensure consistent source indication after the next reset.
380 * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of
the reset cause.
381 *
383 * XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n
384 */
385 __STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void)
386 {
387 return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);
388 }
389 /**
390 * @return None
391 *
393 * Clears the reset reason bits in the reset status register. \n\n
394 * Clearing of the reset status information in the \a SCU_RSTSTAT register via
register bit \a RSTCLR.RSCLR is strongly
395 * recommended to ensure a clear indication of the cause of next reset.
396 *
398 * XMC_SCU_RESET_GetDeviceResetReason() \n\n\n
399 */
400 __STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void)
401 {
402 /* Clear RSTSTAT.RSTSTAT bitfield */
403 SCU_RESET->RSTCLR |= (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
404 }
405
406 /**
407 * @return uint32_t Value of CPU clock frequency.
408 *
410 * Provides the vlaue of CPU clock frequency.\n\n
411 * The value is stored in a global variable \a \b SystemCoreClock.
412 * It is updated when the clock configuration is done using the SCU LLD APIs.
413 * The value represents the frequency of clock used for CPU operation.
414 * \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz.
415 *
417 * XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock()
\n\n\n
418 */
419 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void)
420 {
421 return SystemCoreClock;
422 }
423
424 /**
425 * @return uint32_t Value of peripheral clock frequency in Hertz.
426 *
428 * Provides the vlaue of clock frequency at which the peripherals are working.\n\n
429 * The value is derived from the CPU frequency. \b Range: Value is of type uint32_t.
It is represented in Hertz.
431 * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
432 */
433 uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void);
434
435 #if(UC_SERIES != XMC45)
436
437 /**
438 *
439 * @param peripheral The peripheral for which the clock has to be gated. \b Range:
Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
440 * to identify the peripheral clock to be gated.
441 *
442 * @return None
443 *
445 * Blocks the supply of clock to the selected peripheral.\n\n
446 * Clock gating helps in reducing the power consumption. User can selectively gate
the clocks of unused peripherals.
447 * \if XMC1
448 * fPCLK is the source of clock to various peripherals. Some peripherals support
clock gate. Such a gate blocks
449 * the clock supply for the selected peripheral.
450 * Software can request for individual gating of such peripheral clocks by enabling
the \a SCU_CGATSET0
451 * register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit
protection scheme. Access to protected
452 * bit fields are handled internally.
453 * \endif
454 * \if XMC4
455 * fPERI is the source of clock to various peripherals. Some peripherals support
clock gate. Such a gate blocks
456 * the clock supply for the selected peripheral.
457 * Software can request for individual gating of such peripheral clocks by enabling
one of the \a
458 * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields.
459 *
460 * \endif
461 * Note: Clock gating shall not be activated unless the module is in reset state. So
use \a
462 * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any
peripheral.
464 * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock()
\n\n\n
465 */
466 void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
467
468 /**
469 *
470 * @param peripheral The peripheral for which the clock has to be ungated. \b
Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
471 * to identify the peripheral.
472 *
473 * @return None
474 *
476 * Enables the supply of clock to the selected peripheral.\n\n
477 * By default when the device powers on, the peripheral clock will be gated for the
478 * peripherals that support clock gating.
479 * The peripheral clock should be enabled before using it for any functionality.
480 * \if XMC1
481 * fPCLK is the source of clock to various peripherals. Some peripherals support
clock gate.
482 * Software can request for individual ungating of such peripheral clocks by setting
respective bits
483 * in the \a SCU_CGATCLR0 register.
484 * \endif
485 * \if XMC4
486 * fPERI is the source of clock to various peripherals. Some peripherals support
clock gate.
487 * Software can request for individual ungating of such peripheral clocks by setting
the respective bits in one of \a
488 * SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers.
489 * \endif
490 *
492 * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
493 */
494 void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
495
496 /**
497 *
498 * @param peripheral The peripheral for which the check for clock gating has to be
done.
499 * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify
the peripheral.
500 *
501 * @return bool Status of the peripheral clock gating. \b Range: true if the
peripheral clock is gated.
502 * false if the peripheral clock ungated(gate de-asserted).
503 *
505 * Gives the status of peripheral clock gating.\n\n
506 * \if XMC1
507 * Checks the status of peripheral clock gating using the register CGATSTAT0.
508 * \endif
509 * \if XMC4
510 * Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or
CGATSTAT2 registers.
511 * \endif
512 * It is recommended to use this API before
513 * enabling the gating of any peripherals through \a
XMC_SCU_CLOCK_GatePeripheralClock() API.
514 *
516 * XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
517 */
518 bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral
);
519 #endif
520
521
522 /**
523 * @return uint32_t Status of the register mirror update.\n
524 * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register
for the mirror update event of
525 * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple
update events can be combined
526 * using \a OR operation.
527 *
529 * Provides the status of hibernate domain register update, when the respective
mirror registers are changed. \n\n
530 * The hibernate domain is connected to the core domain via SPI serial communication.
MIRRSTS is a status register
531 * representing the communication of changed value of a mirror register to its
corresponding register in the
532 * hibernate domain. The bit fields of the register indicate
533 * that a corresponding register of the hibernate domain is ready to accept a write
or that the communication interface
534 * is busy with executing the previous operation.\n
535 * Note: There is no hibernate domain in XMC1x devices. This register is retained for
legacy purpose.
536 */
537 __STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void)
538 {
539 return(SCU_GENERAL->MIRRSTS);
540 }
541
542 /**
543 * @param event The event for which the interrupt handler is to be configured. \n
544 * \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
545 * @param handler Name of the function to be executed when the event if detected. \n
546 * \b Range: The function accepts no arguments and returns no value.
547 * @return XMC_SCU_STATUS_t Status of configuring the event handler function for the
selected event.\n
548 * \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully
configured.\n
549 * \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n
551 * Assigns the event handler function to be executed on occurence of the selected
event.\n\n
552 * If the input event is valid, the handler function will be assigned to a table to
be executed
553 * when the interrupt is generated and the event status is set in the event status
register. By using this API,
554 * polling for a particular event can be avoided. This way the CPU utilization will
be optimized. Multiple SCU events
555 * can generate a common interrupt. When the interrupt is generated, a common
interrupt service routine is executed.
556 * It checks for status flags of events which can generate the interrupt. The handler
function will be executed if the
557 * event flag is set.
558 *
560 * XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n
561 */
562 XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t
event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);
563
564 /**
565 * @param sr_num Service request number identifying the SCU interrupt generated.\n
566 * \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so
the value should be 0.\n
567 * But XMC1x devices support 3 interrupt nodes.
568 * @return None
570 * A common function to execute callback functions for multiple events.\n\n
571 * It checks for the status of events which can generate the interrupt with the
selected service request.
572 * If the event is set, the corresponding callback function will be executed. It also
clears the event status bit.\n
573 * \b Note: This is an internal function. It should not be called by the user
application.
574 *
576 * XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
577 */
578 void XMC_SCU_IRQHandler(uint32_t sr_num);
579
580 #ifdef __cplusplus
581 }
582 #endif
583
584 /**
585 * @}
586 */
587
588 /**
589 * @}
590 */
591
592 #endif /* SCU_H */
593

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