Cc1314R10 Simplelink™ High-Performance Sub-1 GHZ Wireless Mcu

CC1314R10
SWRS270A – DECEMBER 2022 – REVISED JUNE 2023
CC1314R10 SimpleLink™ High-Performance Sub-1 GHz Wireless MCU

– ETSI EN 300 220 Receiver Cat. 1.5 and 2, EN
1 Features 303 131, EN 303 204
Wireless microcontroller – FCC CFR47 Part 15
– ARIB STD-T108 and STD-T67
• Powerful 48 MHz Arm® Cortex®-M33 processor
with TrustZone® MCU peripherals
• FPU and DSP extension
• Most digital peripherals can be routed to any GPIO
• 1024 kB flash program memory
• Four 32-bit or eight 16-bit general-purpose timers
• 8 kB of cache SRAM
• 12-bit SAR ADC, 200 ksps, 8 channels
• 256 kB of ultra-low leakage SRAM with parity for
• 8-bit DAC
high-reliability operation
• Two comparators
– 32 kB of additional SRAM is available if parity is • Programmable current source
ADVANCE INFORMATION
disabled • Four UART, four SPI, two I2C, I2S
• Dynamic multiprotocol manager (DMM) driver • Real-time clock (RTC)
• Supports over-the-air upgrade (OTA) • Integrated temperature and battery monitor
Ultra-low power sensor controller Security enablers
• Autonomous MCU with 4 kB of SRAM • Supports secure boot
• Sample, store, and process sensor data • Supports secure key storage and device ID
• Fast wake-up for low-power operation • Arm TrustZone for trusted execution environment
• Software defined peripherals; capacitive touch, • AES 128- and 256-bit cryptographic accelerator
flow meter, LCD • Public key accelerator
Low power consumption • SHA2 accelerator (full suite up to SHA-512)
• True random number generator (TRNG)
• MCU consumption: • Secure debug lock
– 3.4 mA active mode, CoreMark® • Software anti-rollback protection
– 71 μA/MHz running CoreMark
– 0.98 μA standby mode, RTC, 256 kB RAM Development tools and software
– 0.17 μA shutdown mode, wake-up on pin • LP-EM-CC1314R10
• Ultra low-power sensor controller consumption: • LP-XDS110, LP-XDS110ET or TMDSEMU110-U
– 30 μA in 2 MHz mode (with TMDSEMU110-ETH add-on) Debug Probe
– 809 μA in 24 MHz mode • SimpleLink™ LOWPOWER F2 Software
• Radio consumption: Development Kit (SDK)
– 25.8 mA TX at +14 dBm at 868 MHz • SmartRF™ Studio for simple radio configuration
• Sensor Controller Studio for building low-power
Wireless protocol support
sensing applications
• Wi-SUN® • SysConfig system configuration tool
• mioty®
Operating range
• Amazon Sidewalk
• Wireless M-Bus • On-chip buck DC/DC converter
• SimpleLink™ TI 15.4-Stack (Sub-1 GHz) • 1.8 V to 3.8 V single supply voltage
• Proprietary Systems • –40°C to +105°C
High performance radio Package
• Coherent modem, 802.15.4 O-QPSK • 7 mm × 7 mm RGZ VQFN48 (30 GPIOs)
• –121 dBm for 2.5 kbps long-range mode • 8 mm × 8 mm RSK VQFN64 (46 GPIOs)1
• –110 dBm at 50 kbps, 802.15.4, 868 MHz • RoHS-compliant package
Regulatory compliance
• Designed for systems targeting compliance with
these standards:
1 Information for the RSK package (8.00 mm x 8.00 mm) is preview only and subject to change.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
CC1314R10
SWRS270A – DECEMBER 2022 – REVISED JUNE 2023 www.ti.com
– Grid communications – wireless

2 Applications communications – Long-range sensor
• 315, 433, 470 to 510, 868, and 902 to 928 MHz applications
ISM and SRD systems2 with down to 4 kHz of – Other alternative energy – energy harvesting,
receive bandwidth solar inverters
• Building automation • Industrial transport – asset tracking
– Building security systems – motion detector, • Factory automation and control
electronic smart lock, door and window sensor, • Medical
garage door system, gateway • Electronic point of sale (EPOS) – Electronic Shelf
– HVAC – thermostat, wireless environmental Label (ESL)
sensor, HVAC system controller, gateway • Personal electronics
– Fire safety system – smoke and heat detector, – Connected peripherals – consumer wireless
fire alarm control panel (FACP) module
– Video surveillance – IP network camera – Home theater & entertainment – smart
ADVANCE INFORMATION
– Elevators and escalators – elevator main speakers, set-top box

control panel for elevators and escalators – Gaming
• Grid infrastructure – Wearables (non-medical)
– Smart meters – water meter, gas meter,
electricity meter, and heat cost allocators
3 Description
The SimpleLink™ CC1314R10 device is a low power, Sub-1 GHz wireless microcontroller (MCU) targeting
applications needing enhanced security, on-chip over the air update capability, and support for advanced
applications or large wireless protocols. It supports IEEE 802.15.4, IPv6-enabled smart objects (6LoWPAN),
Wireless M-Bus, Wi-SUN, Amazon Sidewalk, mioty and proprietary systems, including the TI 15.4-Stack (Sub-1
GHz). The device is optimized for low-power wireless communication and advanced sensing in building security
systems, HVAC, smart meters, medical, wired networking, gateways and grid communications, home theater &
entertainment, and connected peripherals markets. The highlighted features of this device include:
• Arm TrustZone-based secure key storage, device ID, and trusted functions support.
• Flexible Sub-1 GHz radio supporting industry standard frequency bands (315 MHz, 433 MHz, 868 MHz,
915 MHz, and more) to meet the industrial needs.
• Wide flexibility of protocol stack support in the SimpleLink LOWPOWER F2 Software Development Kit (SDK)
including Wi-SUN, Amazon Sidewalk and SimpleLink 15.4-Stack (Sub-1 GHz).
• Maximum transmit power of +14 dBm at Sub-1 GHz with 25.8 mA current consumption.
• Longer battery life wireless applications with low standby current of 0.98 µA and full RAM retention.
• Industrial temperature ready with lowest standby current of approximately 13 µA at 105 ⁰C (with full RAM
retention).
• Advanced sensing with a programmable, autonomous ultra-low power Sensor Controller CPU with fast
wake-up capability. As an example, the sensor controller is capable of 1 Hz ADC sampling at 1.2 µA system
current.
• Low SER (Soft Error Rate) FIT (Failure-in-time) for long operation lifetime with no disruption for industrial
markets with always-on SRAM parity against corruption due to potential radiation events.
• Dedicated software controlled radio controller (Arm Cortex-M0) providing flexible low-power RF transceiver
capability to support multiple physical layers and RF standards.
• Excellent radio sensitivity (-121 dBm) and robustness (selectivity and blocking) performance for SimpleLink
long-range mode.
The CC1314R10 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the
SimpleLink platform enables you to add any combination of the portfolio’s devices into your design, allowing
100 percent code reuse when your design requirements change. For more information, visit SimpleLink MCU
platform.
2 See RF Core for additional details on supported protocol standards, modulation formats, and data rates.
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: CC1314R10

CC1314R10
www.ti.com SWRS270A – DECEMBER 2022 – REVISED JUNE 2023
In addition to the software compatibility, within the Sub-1 GHz wireless MCUs, there is pin-to-pin compatibility
from 32 kB of flash up to 1 MB of flash in the 7 × 7 mm QFN package for maximum design scalability. For more
information on TIs Sub-1 GHz solutions, visit www.ti.com/sub1ghz
Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
CC1314R106T0RGZ VQFN (48) 7.00 mm × 7.00 mm
CC1314R106T0RSK VQFN (64) 8.00 mm × 8.00 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
12, or see the TI website.
4 Functional Block Diagram
ADVANCE INFORMATION
Figure 4-1. CC1314R10 Block Diagram
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

CC1314R10
Table of Contents
1 Features............................................................................1 8.14 Timing and Switching Characteristics..................... 25
2 Applications..................................................................... 2 8.15 Peripheral Characteristics.......................................31
3 Description.......................................................................2 8.16 Typical Characteristics............................................ 39
4 Functional Block Diagram.............................................. 3 9 Detailed Description......................................................47
5 Revision History.............................................................. 4 9.1 Overview................................................................... 47
6 Device Comparison......................................................... 5 9.2 System CPU............................................................. 47
7 Terminal Configuration and Functions..........................6 9.3 Radio (RF Core)........................................................48
7.1 Pin Diagram – RGZ Package (Top View)....................6 9.4 Memory..................................................................... 50
7.2 Signal Descriptions – RGZ Package...........................7 9.5 Sensor Controller...................................................... 51
7.3 Connections for Unused Pins and Modules – 9.6 Cryptography............................................................ 52
RGZ Package................................................................8 9.7 Timers....................................................................... 53
7.4 Pin Diagram – RSK Package (Top View)....................9 9.8 Serial Peripherals and I/O.........................................54
7.5 Signal Descriptions – RSK Package.........................10 9.9 Battery and Temperature Monitor............................. 54
ADVANCE INFORMATION
7.6 Connection of Unused Pins and Module – RSK 9.10 µDMA...................................................................... 54

Package.......................................................................11 9.11 Debug......................................................................54
8 Specifications................................................................ 12 9.12 Power Management................................................56
8.1 Absolute Maximum Ratings...................................... 12 9.13 Clock Systems........................................................ 57
8.2 ESD Ratings............................................................. 12 9.14 Network Processor..................................................57
8.3 Recommended Operating Conditions.......................12 10 Application, Implementation, and Layout................. 58
8.4 Power Supply and Modules...................................... 12 10.1 Reference Designs................................................. 58
8.5 Power Consumption - Power Modes........................ 13 10.2 Junction Temperature Calculation...........................59
8.6 Power Consumption - Radio Modes......................... 14 11 Device and Documentation Support..........................60
8.7 Nonvolatile (Flash) Memory Characteristics............. 14 11.1 Tools and Software..................................................60
8.8 Thermal Resistance Characteristics......................... 14 11.2 Documentation Support.......................................... 62
8.9 RF Frequency Bands................................................ 15 11.3 Support Resources................................................. 62
8.10 861 MHz to 1054 MHz - Receive (RX)....................16 11.4 Trademarks............................................................. 63
8.11 861 MHz to 1054 MHz - Transmit (TX) .................. 24 11.5 Electrostatic Discharge Caution.............................. 63
8.12 861 MHz to 1054 MHz - PLL Phase Noise 11.6 Glossary.................................................................. 63
Wideband Mode.......................................................... 25 12 Mechanical, Packaging, and Orderable
8.13 861 MHz to 1054 MHz - PLL Phase Noise Information.................................................................... 64
Narrowband Mode.......................................................25 12.1 Packaging Information............................................ 64
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from December 8, 2022 to June 14, 2023 (from Revision * (December 2022) to
Revision A (June 2023)) Page
• Added devices to the Device Comparison table................................................................................................. 5
• Deleted device revision limitation for LQI in Table 9-1 .....................................................................................49
• Updated links in the Reference Designs...........................................................................................................58

CC1314R10
6 Device Comparison
RADIO SUPPORT PACKAGE SIZE
4 × 4 mm VQFN (24)
4 × 4 mm VQFN (32)
5 × 5 mm VQFN (32)
5 × 5 mm VQFN (40)
7 × 7 mm VQFN (48)
8 × 8 mm VQFN (64)
Sub-1 GHz Prop.
Wireless M-Bus
RAM +
Bluetooth® LE
FLASH
Multiprotocol
2.4GHz Prop.
Device Cache GPIO
+20 dBm PA
(kB)
(kB)
Wi-SUN®
Sidewalk
ZigBee
Thread
mioty
CC1310 √ √ √ 32-128 16-20 + 8 10-30 √ √ √
CC1311R3 √ √ √ 352 32 + 8 22-30 √ √
CC1311P3 √ √ √ √ 352 32 + 8 26 √
CC1312R √ √ √ √ 352 80 + 8 30 √
ADVANCE INFORMATION
CC1312R7 √ √ √ √ √ √ 704 144 + 8 30 √
CC1314R10 √ √ √ √ √ √ 1024 256 + 8 30-46 √ √
CC1352R √ √ √ √ √ √ √ √ √ 352 80 + 8 28 √
CC1354R10 √ √ √ √ √ √ √ √ √ 1024 256 + 8 28-42 √ √
CC1352P √ √ √ √ √ √ √ √ √ √ 352 80 + 8 26 √
CC1352P7 √ √ √ √ √ √ √ √ √ √ √ 704 144 + 8 26 √
CC1354P10 √ √ √ √ √ √ √ √ √ √ √ 1024 256 + 8 26-42 √ √
CC2340R2 √ √ √ 256 28 12 √
CC2340R5 √ √ √ √ 512 36 12-26 √ √
CC2340R5-Q1 √ 512 36 19 √
CC2640R2F √ 128 20 + 8 10-31 √ √ √
CC2642R √ 352 80 + 8 31 √
CC2642R-Q1 √ 352 80 + 8 31 √
CC2651R3 √ √ √ 352 32 + 8 23-31 √ √
CC2651P3 √ √ √ √ 352 32 + 8 22-26 √ √
CC2652R √ √ √ √ √ 352 80 + 8 31 √
CC2652RB √ √ √ √ √ 352 80 + 8 31 √
CC2652R7 √ √ √ √ √ 704 144 + 8 31 √
CC2652P √ √ √ √ √ √ 352 80 + 8 26 √
CC2652P7 √ √ √ √ √ √ 704 144 + 8 26 √
CC2674R10 √ √ √ √ √ 1024 256 + 8 31-45 √ √
CC2674P10 √ √ √ √ √ √ 1024 256 + 8 26-45 √ √

CC1314R10
7 Terminal Configuration and Functions

7.1 Pin Diagram – RGZ Package (Top View)
48 VDDR_RF
46 X48M_N
47 X48M_P
43 DIO_30
42 DIO_29
41 DIO_28
40 DIO_27
39 DIO_26
38 DIO_25
37 DIO_24
45 VDDR
44 VDDS
RF_P 1 36 DIO_23
RF_N 2 35 RESET_N
RX_TX 3 34 VDDS_DCDC
X32K_Q1 4 33 DCDC_SW
X32K_Q2 5 32 DIO_22
ADVANCE INFORMATION
DIO_1 6 31 DIO_21
DIO_2 7 30 DIO_20
DIO_3 8 29 DIO_19
DIO_4 9 28 DIO_18
DIO_5 10 27 DIO_17
DIO_6 11 26 DIO_16
DIO_7 12 25 JTAG_TCKC
VDDS2 13
DIO_8 14
DIO_9 15
DIO_10 16
DIO_11 17
DIO_12 18
DIO_13 19
DIO_14 20
DIO_15 21
VDDS3 22
DCOUPL 23
JTAG_TMSC 24
Figure 7-1. RGZ (7 mm × 7 mm) Pinout, 0.5 mm Pitch (Top View)
The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30

CC1314R10
7.2 Signal Descriptions – RGZ Package

Table 7-1. Signal Descriptions – RGZ Package
PIN
I/O TYPE DESCRIPTION
NAME NO.
DCDC_SW 33 — Power Output from internal DC/DC converter(1)
DCOUPL 23 — Power For decoupling of internal 1.27 V regulated digital-supply (2)
DIO_1 6 I/O Digital GPIO
DIO_5 10 I/O Digital GPIO, high-drive capability
ADVANCE INFORMATION
DIO_16 26 I/O Digital GPIO, JTAG_TDO, high-drive capability
DIO_17 27 I/O Digital GPIO, JTAG_TDI, high-drive capability
DIO_23 36 I/O Digital or Analog GPIO, analog capability
EGP — — GND Ground – exposed ground pad(3)
JTAG_TMSC 24 I/O Digital JTAG TMSC, high-drive capability
JTAG_TCKC 25 I Digital JTAG TCKC
RESET_N 35 I Digital Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
RF_P 1 — RF
Positive RF output signal from PA during TX
Negative RF input signal to LNA during RX
RF_N 2 — RF
Negative RF output signal from PA during TX
RX_TX 3 — RF Optional bias pin for the RF LNA
Internal supply, must be powered from the internal DC/DC
VDDR 45 — Power
converter or the internal LDO(2) (4) (6)

CC1314R10
Table 7-1. Signal Descriptions – RGZ Package (continued)

PIN
NAME NO.
VDDR_RF 48 — Power
VDDS 44 — Power 1.8 V to 3.8 V main chip supply(1)
VDDS2 13 — Power 1.8 V to 3.8 V DIO supply(1)
VDDS_DCDC 34 — Power 1.8 V to 3.8 V DC/DC converter supply
X48M_N 46 — Analog 48 MHz crystal oscillator pin N
X48M_P 47 — Analog 48 MHz crystal oscillator pin P
X32K_Q1 4 — Analog 32 kHz crystal oscillator pin 1
ADVANCE INFORMATION
(1) For more details, see technical reference manual listed in Section 11.2.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
7.3 Connections for Unused Pins and Modules – RGZ Package

Table 7-2. Connections for Unused Pins – RGZ Package
PREFERRED
FUNCTION SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1)
PRACTICE(1)
6–12
14–21
GPIO DIO_n NC or GND NC
26–32
36–43
X32K_Q1 4
32.768 kHz crystal NC or GND NC
X32K_Q2 5
DCDC_SW 33 NC NC
DC/DC converter(2)
VDDS_DCDC 34 VDDS VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 µF DCDC capacitor must be kept on the VDDR net.

CC1314R10
7.4 Pin Diagram – RSK Package (Top View)
64 VDDR_RF
49 RESET_N
62 X48M_N
63 X48M_P
52 DIO_25
51 DIO_24
50 DIO_23
59 DIO_47
58 DIO_46
57 DIO_30
56 DIO_29
55 DIO_28
54 DIO_27
53 DIO_26
61 VDDR
60 VDDS
RF_P 1 48 VDDS_DCDC
RF_N 2 47 DCDC_SW
RX_TX 3 46 DIO_45
X32K_Q1 4 45 DIO_44
X32K_Q2 5 44 DIO_43
DIO_1 6 43 DIO_42
ADVANCE INFORMATION
DIO_2 7 42 DIO_41
DIO_32 8 41 DIO_40
DIO_33 9 40 DIO_22
DIO_34 10 39 DIO_21
DIO_35 11 38 DIO_20
DIO_3 12 37 DIO_19
DIO_4 13 36 DIO_18
DIO_5 14 35 DIO_17
DIO_6 15 34 DIO_16
DIO_7 16 33 JTAG_TCKC
VDDS2 17
DIO_8 18
DIO_9 19
DIO_10 20
DIO_11 21
DIO_36 22
DIO_37 23
DIO_38 24
DIO_39 25
DIO_12 26
DIO_13 27
DIO_14 28
DIO_15 29
VDDS3 30
DCOUPL 31
JTAG_TMSC 32
Figure 7-2. RSK (8 mm × 8 mm) Pinout, 0.4 mm Pitch (Top View)
The following I/O pins marked in Figure 7-2 in bold have high-drive capabilities:
• Pin 14, DIO_5
• Pin 15, DIO_6
• Pin 16, DIO_7
• Pin 32, JTAG_TMSC
• Pin 34, DIO_16
• Pin 35, DIO_17
The following I/O pins marked in Figure 7-2 in italics have analog capabilities:
• Pin 50, DIO_23
• Pin 51, DIO_24
• Pin 52, DIO_25
• Pin 53, DIO_26
• Pin 54, DIO_27
• Pin 55, DIO_28
• Pin 56, DIO_29
• Pin 57, DIO_30

CC1314R10
7.5 Signal Descriptions – RSK Package

Table 7-3. Signal Descriptions – RSK Package
PIN
NAME NO.
DCDC_SW 47 — Power Output from internal DC/DC converter(1)
DCOUPL 31 — Power For decoupling of internal 1.27 V regulated digital-supply (2)
ADVANCE INFORMATION

DIO_16 34 I/O Digital GPIO, JTAG_TDO, high-drive capability
DIO_17 35 I/O Digital GPIO, JTAG_TDI, high-drive capability
DIO_30 57 I/O Digital GPIO, analog capability

CC1314R10
Table 7-3. Signal Descriptions – RSK Package (continued)

PIN
NAME NO.
EGP — — GND Ground – exposed ground pad(3)
JTAG_TMSC 32 I/O Digital JTAG TMSC, high-drive capability
JTAG_TCKC 33 I Digital JTAG TCKC
RESET_N 49 I Digital Reset, active low. No internal pullup resistor
ADVANCE INFORMATION
Positive RF input signal to LNA during RX
RF_P_SUB_1GHZ 1 — RF
Positive RF output signal from PA during TX
Negative RF input signal to LNA during RX
RF_N_SUB_1GHZ 2 — RF
Negative RF output signal from PA during TX
RX_TX 3 — RF Optional bias pin for the RF LNA
VDDR 61 — Power
VDDR_RF 64 — Power
VDDS 60 — Power 1.8 V to 3.8 V main chip supply(1)
VDDS_DCDC 48 — Power 1.8 V to 3.8 V DC/DC converter supply
X48M_N 62 — Analog 48 MHz crystal oscillator pin N
X48M_P 63 — Analog 48 MHz crystal oscillator pin P
(1) For more details, see technical reference manual listed in Section 11.2.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
7.6 Connection of Unused Pins and Module – RSK Package

Table 7-4. Connections for Unused Pins – RSK Package
PREFERRED
FUNCTION SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1)
PRACTICE(1)
6–16, 18–29
GPIO DIO_n NC or GND NC
34–46, 50–59
X32K_Q1 4
32.768 kHz crystal NC or GND NC
X32K_Q2 5
DCDC_SW 47 NC NC
DC/DC converter(2)
VDDS_DCDC 48 VDDS VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 µF DCDC capacitor must be kept on the VDDR net.

CC1314R10
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDDS(3) Supply voltage –0.3 4.1 V
Voltage on any digital pin(4) (5) –0.3 VDDS + 0.3, max 4.1 V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P –0.3 VDDR + 0.3, max 2.25 V
Voltage scaling enabled –0.3 VDDS
Vin Voltage on ADC input Voltage scaling disabled, internal reference –0.3 1.49 V
Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9
Input level, RF pins 10 dBm
Tstg Storage temperature –40 150 °C
ADVANCE INFORMATION
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIOs.
(5) Injection current is not supported on any GPIO pin
8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±2000 V
VESD Electrostatic discharge
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) All pins ±500 V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process
8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating ambient temperature(1) (3) –40 105 °C
Operating supply voltage (VDDS) 1.8 3.8 V
Operating supply voltage (VDDS), boost mode VDDR = 1.95 V
2.1 3.8 V
+14 dBm RF output power
Rising supply voltage slew rate 0 100 mV/µs
Falling supply voltage slew rate(2) 0 20 mV/µs
(1) Operation at or near maximum operating temperature for extended durations will result in lifetime reduction.
(2) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22 µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
(3) For thermal resistance characteristics refer to Thermal Resistance Characteristics. For application considerations, refer to SPRA953
8.4 Power Supply and Modules

Over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
VDDS Power-on-Reset (POR) threshold 1.1 - 1.55 V
VDDS Brown-out Detector (BOD) (1) Rising threshold 1.77 V
VDDS Brown-out Detector (BOD), before initial boot (2) Rising threshold 1.70 V
VDDS Brown-out Detector (BOD) (1) Falling threshold 1.75 V
(1) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)
(2) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin

CC1314R10
8.5 Power Consumption - Power Modes

When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled unless
otherwise noted.
PARAMETER TEST CONDITIONS TYP UNIT

Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold 150
Reset and Shutdown nA
Shutdown. No clocks running, no retention 171
RTC running, CPU, 256 kB RAM and (partial) register retention.
0.98 µA
RCOSC_LF
0.88 µA
Standby RCOSC_LF
without cache retention RTC running, CPU, 256 kB RAM and (partial) register retention
1.08 µA
XOSC_LF
ADVANCE INFORMATION
RTC running, CPU, 128 kB RAM and (partial) register retention
0.99 µA
XOSC_LF
2.24 µA
RCOSC_LF
Icore
2.16 µA
Standby RCOSC_LF
with cache retention RTC running, CPU, 256 kB RAM and (partial) register retention.
2.34 µA
XOSC_LF
2.25 µA
XOSC_LF
Supply Systems and RAM powered
Idle 635 µA
RCOSC_HF
MCU running CoreMark at 48 MHz with parity enabled
3.5 mA
RCOSC_HF
Active
MCU running CoreMark at 48 MHz with parity disabled
3.4 mA
RCOSC_HF
Peripheral Current Consumption
Peripheral power
Delta current with domain enabled 62.4
domain
Serial power domain Delta current with domain enabled 5.83
Delta current with power domain enabled,
RF Core 102.0
clock enabled, RF core idle
µDMA Delta current with clock enabled, module is idle 58.0
Timers Delta current with clock enabled, module is idle(3) 97.2
Iperi I2C Delta current with clock enabled, module is idle 9.8 µA
I2S Delta current with clock enabled, module is idle 22.2

SPI Delta current with clock enabled, module is idle(2) 55.8
UART Delta current with clock enabled, module is idle(1) 114.2
CRYPTO (AES) Delta current with clock enabled, module is idle 15.5
PKA Delta current with clock enabled, module is idle 66.6
TRNG Delta current with clock enabled, module is idle 21.0
Sensor Controller Engine Consumption
Active mode 24 MHz, infinite loop, VDDS = 3.0 V 820
ISCE µA
Low-power mode 2 MHz, infinite loop, VDDS = 3.0 V 32
(1) Only one UART running

(2) Only one SPI running
(3) Only one GPTimer running

CC1314R10
8.6 Power Consumption - Radio Modes

When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled unless
otherwise noted.
Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm
setting where this current is already included).
Relevant Icore and Iperi currents are included in below numbers.
PARAMETER TEST CONDITIONS TYP UNIT
Radio receive current, 868 MHz 5.8 mA
0 dBm output power setting
7.5 mA
868 MHz
Radio transmit current
+10 dBm output power setting
16.1 mA
868 MHz
Radio transmit current +14 dBm output power setting
25.8 mA
Boost mode 868 MHz
ADVANCE INFORMATION
8.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 2 kB
Supported flash erase cycles before failure, full bank(1) (5) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector Write
83
erase(3) Operations
Flash retention 105 °C 11.4 Years
Flash sector erase current Average delta current 0.3 mA
Zero cycles 2.1 ms
Flash sector erase time(4)
30k cycles 4000 ms
Flash write current Average delta current, 16 bytes at a time 3.0 mA
Flash write time(4) 16 bytes at a time 21.4 µs
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics

PACKAGE
THERMAL METRIC (1) RGZ (VQFN) RSK(VQFN) UNIT
48 PINS 64 PINS
RθJA Junction-to-ambient thermal resistance 23.4 TBD °C/W(2)
RθJC(top) Junction-to-case (top) thermal resistance 13.3 TBD °C/W(2)
RθJB Junction-to-board thermal resistance 8.0 TBD °C/W(2)
ψJT Junction-to-top characterization parameter 0.1 TBD °C/W(2)
ψJB Junction-to-board characterization parameter 7.9 TBD °C/W(2)
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 TBD °C/W(2)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.

CC1314R10
8.9 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted).
1076 1315
861 1054
Frequency bands 431 527 MHz
359 439
287 351
ADVANCE INFORMATION

CC1314R10
8.10 861 MHz to 1054 MHz - Receive (RX)

When Measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
General Parameters
Digital channel filter programmable receive
4 4000 kHz
bandwidth
Data rate step size 1.5 bps
Spurious emissions 25 MHz to 1 GHz 868 MHz < -57 dBm
Spurious emissions 1 GHz to 13 GHz Conducted emissions measured according to ETSI EN 300 220 < -47 dBm
Wi-SUN, 50 kbps, ±12.5 kHz deviation, 2-GFSK, 78 kHz RX BW, #1a
Sensitivity MRFSK, 866.6 MHz, 10% PER, 250 byte payload -106 dBm
Saturation limit 10% PER, 250 byte payload, 866.6 MHz 10 dBm
ADVANCE INFORMATION
Selectivity, +100 kHz 33 dB

Selectivity, -100 kHz 10% PER, 250 byte payload, 866.6 MHz. Wanted signal 3 dB 31 dB
Selectivity, +200 kHz above sensitivity level. 38 dB
Selectivity, -200 kHz 37 dB
RSSI dynamic range Starting from the sensitivity limit 93 dB
RSSI accuracy Starting from the sensitivity limit across the given dynamic range ±3 dB
Wi-SUN, 50 kbps, ±25 kHz deviation, 2-GFSK, 100 kHz RX BW, #1b
Wi-SUN, 100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX BW, #2a
Selectivity, +800 kHz above sensitivity level, modulated blocker. 52 dB
Wi-SUN, 150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX BW, #3

CC1314R10
8.10 861 MHz to 1054 MHz - Receive (RX) (continued)

Wi-SUN, 200 kbps, ±50 kHz deviation, 2-GFSK, 335 kHz RX BW, #4a
ADVANCE INFORMATION
Selectivity, +1200 kHz above sensitivity level, modulated blocker. 54 dB
Wi-SUN, 300 kbps, ±75 kHz deviation, 2-GFSK, 496 kHz RX BW, #5
802.15.4-2020, 10 kbps, 2-FSK, 26 kHz RX BW, Mode #1a
Sensitivity FSK, 915.0 MHz, 20 byte PSDU < 10% PER -113 dBm
Sensitivity FSK, 868.3 MHz, 20 byte PSDU < 10% PER -113 dBm
Saturation limit PSDU length 20 octets; PER < 10%, 868.3 MHz 10 dBm

CC1314R10

Blocking, +1 MHz 60 dB
PSDU length 20 octets; PER < 10%, 868.3 MHz
Blocking, -1 MHz 59 dB
ADVANCE INFORMATION
Blocking, +1 MHz PSDU length 20 octets; PER < 10%, 868.3 MHz. Wanted signal 58 dB
Blocking, -1 MHz 3 dB above sensitivity level. 58 dB
Blocking + 5% Fc. (45.75 MHz) -15 dBm
10% PER, 20 byte payload, 866.6 MHz 802.15.4g mandatory
Blocking - 5% Fc. (-45.75 MHz) mode, wanted signal -94 dBm. 3 dB above usable sensitivity -15 dBm
limit according to ETSI EN 300 220 V3.1.1 (usable sensitivity -97
Image rejection (image compensation
dBm). Limit is Cat 1.5 requirement. 39 dB
enabled)
PSDU length 20 octets; PER < 10%, 868.3 MHz 39 dB
enabled)
-40 to 125℃, 10% PER, 250 byte payload, 866.6 MHz 39 dB
enabled)
10% PER, 20 byte payload, measured at 10 dB above sensitivity
Frequency error tolerance (ppm) -12 ppm
level. Negative offset
Frequency error tolerance (ppm) 12 ppm
level. Positive offset
Symbol rate error tolerance (ppm) level. -1000 ppm
Negative offset
1% BER, measured at 10 dB above sensitivity level
Symbol rate error tolerance (ppm) 1000 ppm
Positive offset
802.15.4-2020, 20 kbps, 2-FSK, 52 kHz RX BW, Mode #1b
FSK, 20 kbps, ±10 kHz deviation, 2-GFSK, 915.0 MHz, 52 kHz
Sensitivity -110 dBm
RX BW, 20 byte PSDU < 10% PER

CC1314R10

FSK, 20 kbps, ±10 kHz deviation, 2-GFSK, 868.3 MHz, 52 kHz
Sensitivity -110 dBm
RX BW, 20 byte PSDU < 10% PER
Saturation limit 20 byte PSDU < 10% PER, 868.3 MHz 10 dBm
ADVANCE INFORMATION
20 byte PSDU < 10% PER, 868.3 MHz
Blocking, +1 MHz 20 byte PSDU < 10% PER, 868.3 MHz. Wanted signal 3 dB 56 dB
Blocking, -1 MHz above sensitivity level. 55 dB
Blocking + 5% Fc. (45.75 MHz) 20 byte PSDU < 10% PER, 866.6 MHz, wanted signal -94 dBm. -13 dBm
3 dB above usable sensitivity limit according to ETSI EN 300 220
Blocking - 5% Fc. (-45.75 MHz) V3.1.1 (usable sensitivity -97 dBm). Limit is Cat 1.5 requirement. -13 dBm
Image rejection (image compensation 20 byte PSDU < 10% PER, 866.6 MHz. Wanted signal 3 dB
39 dB
enabled) above sensitivity limit.
20 byte PSDU < 10% PER, 866.6 MHz(1) 39 dB
enabled)
-40 to 125℃, 10% PER, 250 byte payload, 866.6 MHz 39 dB
enabled)
20 byte PSDU < 10% PER, measured at 10 dB above sensitivity
level. Negative offset
level. Positive offset
Symbol rate error tolerance (ppm) level. -1000 ppm
Negative offset

CC1314R10

Symbol rate error tolerance (ppm) level. 1000 ppm
Negative offset
802.15.4, 200 kbps, ±50 kHz deviation, 2-GFSK, 311 kHz RX BW
Sensitivity BER = 10–2, 868 MHz –103 dBm
Selectivity, +400 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 45 dB
Selectivity, -400 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 45 dB
Selectivity, +800 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 52 dB
ADVANCE INFORMATION
Selectivity, -800 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 47 dB
Blocking, +2 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 59 dB
Blocking, -2 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 56 dB
Blocking, +10 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 71 dB
Blocking, -10 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 70 dB
Sensitivity 500 kbps 915 MHz, 1% PER, 127 byte payload -95 dBm
Selectivity, ±1 MHz 915 MHz, 1% PER, 127 byte payload. Wanted signal at -88 dBm 34 dB
Selectivity, ±2 MHz 915 MHz, 1% PER, 127 byte payload. Wanted signal at -88 dBm 46 dB
Co-channel rejection 915 MHz, 1% PER, 127 byte payload. Wanted signal at -71 dBm -8 dB
SimpleLink™ Long Range 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity 2.5 kbps, BER = 10–2, 868 MHz -121 dBm
Sensitivity 2.5 kbps, BER = 10–2, 915 MHz -121 dBm
Sensitivity 5 kbps, BER = 10–2, 868 MHz -119 dBm
Sensitivity 5 kbps, BER = 10–2, 915 MHz -119 dBm
Saturation limit 2.5 kbps, BER = 10–2, 868 MHz 10 dBm
Selectivity, +100 kHz 2.5 kbps, BER = 10–2, 868 MHz(1) 49 dB
Selectivity, -100 kHz 2.5 kbps, BER = 10–2, 868 MHz(1) 49 dB
Blocking, +1 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 65 dB
Blocking, -1 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 60 dB
2.5 kbps, BER = 10–2, 868 MHz(1) 47 dB
enabled)
2.5 kbps, 20 kbaud, DSSS=4, ½ K=7 FEC. measured at -110
Frequency error tolerance (ppm) -24/26 ppm
dBm.
2.5 kbps, 20 kbaud, DSSS=4, ½ K=7 FEC. measured at -110
Symbolrate error tolerance (ppm) -90/70 ppm
dBm. Refered to 20 kbaud chip rate.
Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX BW
Sensitivity 1% BER -117 dBm

CC1314R10

1% BER. Wanted signal 3 dB above usable sensitivity limit
Adjacent Channel Rejection 42 dB
(usable sensitivity -104.6 dBm). Interferer ±20 kHz
Alternate Channel Rejection 42 dB
(usable sensitivity -104.6 dBm). Interferer ±40 kHz
Blocking, ±1 MHz 66 dB
(usable sensitivity -104.6 dBm).
ADVANCE INFORMATION
802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 100 kHz RX BW (Legacy)
Saturation limit BER = 10–2, 868 MHz 10 dBm
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz. Wanted signal 3 dB above sensitivity limit.
Blocking + 5% Fc. (43.42 MHz) BER = 10–2, 868 MHz -15 dBm
802.15.4g mandatory mode, wanted signal -94 dBm. 3 dB above
Blocking - 5% Fc. (-43.42 MHz) usable sensitivity limit according to ETSI EN 300 220 V3.1.1 -15 dBm
(usable sensitivity -97 dBm). Limit is Cat 1.5 requirement.
BER = 10–2, 868 MHz. Wanted signal 3 dB above sensitivity limit. 39 dB
enabled)
BER = 10–2, 868 MHz(1) 39 dB
enabled)
-40 to 125℃. BER = 10–2, 868 MHz 41 dB
enabled)

CC1314R10

1% BER, measured at -100 dBm (10 dB above sensitivity level).
Negative offset
1% BER, measured at -100 dBm (10 dB above sensitivity level).
Positive offset
1% BER, measured at-100 dBm (10 dB above sensitivity level).
Symbol rate error tolerance (ppm) -2000 ppm
Negative offset
1% BER, measured at-100 dBm (10 dB above sensitivity level)
Positive offset
Sensitivity 100 kbps 868 MHz, 1% PER, 127 byte payload -103 dBm
ADVANCE INFORMATION
Selectivity, ±200 kHz 38 dB

868 MHz, 1% PER, 127 byte payload. Wanted signal at -96 dBm
Selectivity, ±400 kHz 44 dB
Co-channel rejection 868 MHz, 1% PER, 127 byte payload. Wanted signal at -79 dBm -9 dB
Generic OOK (16.384 kbps, OOK w / Manchester encoding, 100 kHz RX BW)
Sensitivity OOK, 915.0 MHz, 1% BER -114 dBm
Sensitivity OOK, 868.8 MHz, 1% BER -113 dBm
Saturation limit 868.3 MHz 0 dBm
868.3 MHz(1)
868.3 MHz. Wanted signal 3 dB above sensitivity level.
Frequency error tolerance (ppm) Measured at 10 dB above sensitivity level. Negative offset -40 ppm
Frequency error tolerance (ppm) Measured at 10 dB above sensitivity level. Positive offset 40 ppm
Measured at 10 dB above sensitivity level.
Symbol rate error tolerance (ppm) -2000 ppm
Negative offset

CC1314R10

Measured at 10 dB above sensitivity level
Positive offset
(1) Wanted signal 3 dB above usable sensitivity limit according to ETSI EN 300 220 v. 3.1.1.
ADVANCE INFORMATION

CC1314R10
8.11 861 MHz to 1054 MHz - Transmit (TX)

When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.0 V with
path. All measurements are performed conducted. (1)

General parameters
VDDR = 1.95 V
Minimum supply voltage (VDDS ) for boost
Max output power, boost mode 14 dBm
mode is 2.1 V
868 MHz and 915 MHz
Max output power 868 MHz and 915 MHz 12 dBm
Output power programmable range 868 MHz and 915 MHz, 1dB step size. 34 dB
+10 dBm setting
Output power variation over temperature Over recommended temperature operating ±2 dB
ADVANCE INFORMATION
range
+14 dBm setting
Output power variation over temperature Boost mode Over recommended temperature operating ±1.5 dB
range
Spurious emissions and harmonics
+14 dBm setting
< -54 dBm
ETSI restricted bands
30 MHz to 1 GHz
Spurious emissions +14 dBm setting
< -36 dBm
(excluding harmonics) (3) ETSI outside restricted bands
1 GHz to 12.75 GHz +14 dBm setting
< -30 dBm
(outside ETSI restricted bands) measured in 1 MHz bandwidth (ETSI)
30 MHz to 88 MHz
+14 dBm setting < -56 dBm
(within FCC restricted bands)
88 MHz to 216 MHz
216 MHz to 960 MHz
Spurious emissions out- +14 dBm setting < -50 dBm
of-band, 915 MHz (3)
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC restricted +14 dBm setting <-42 dBm
band)
1 GHz to 12.75 GHz
(outside FCC restricted bands)
Below 710 MHz
(ARIB T-108)
710 MHz to 900 MHz
(ARIB T-108)
900 MHz to 915 MHz
Spurious emissions out- +14 dBm setting < -55 dBm
(ARIB T-108)
of-band, 920.6/928 MHz
(3) 930 MHz to 1000 MHz
(ARIB T-108)
1000 MHz to 1215 MHz
(ARIB T-108)
Above 1215 MHz
(ARIB T-108)
+14 dBm setting, 868 MHz < -30
Second harmonic dBm
Third harmonic dBm
Harmonics
Fourth harmonic dBm
Fifth harmonic dBm
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.

CC1314R10
(2) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.0 V.
±10 kHz offset –74 dBc/Hz
Phase noise in the 868- and 915-MHz bands
20 kHz PLL loop bandwidth
ADVANCE INFORMATION
8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.0 V.
Phase noise in the 868- and 915-MHz bands
150 kHz PLL loop bandwith
8.14 Timing and Switching Characteristics

8.14.1 Reset Timing
RESET_N low duration 1 µs
8.14.2 Wakeup Timing

Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
MCU, Reset to Active(1) 850 - 4000 µs
MCU, Shutdown to Active(1) 850 - 4000 µs
MCU, Standby to Active 160 µs
MCU, Active to Standby 39 µs
MCU, Idle to Active 15 µs
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value.

CC1314R10
8.14.3 Clock Specifications
8.14.3.1 48 MHz Clock Input (TCXO)

Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
Clock frequency 48 MHz
TCXO clipped sine output
TCXO clipped sine output, peak-to-peak connected to pin X48M_P 0.8 1.7 V
through series capacitor
TCXO with CMOS output, High input voltage TCXO with CMOS output 1.3 VDDR V
TCXO with CMOS output, Low input voltage directly coupled to pin X48M_P 0 0.3 V
(1) Probing or otherwise stopping the TCXO while the DC/DC converter is enabled may cause permanent damage to the device.
8.14.3.2 48 MHz Crystal Oscillator (XOSC_HF)

ADVANCE INFORMATION
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
Crystal frequency 48 MHz
Equivalent series resistance
ESR 20 60 Ω
6 pF < CL ≤ 9 pF
Equivalent series resistance
ESR 80 Ω
5 pF < CL ≤ 6 pF
Motional inductance, relates to the load capacitance that is used for the crystal (CL in
LM < 3 × 10–25 / CL 2 H
Farads)(5)
CL Crystal load capacitance(4) 5 7(3) 9 pF
Start-up time(2) 200 µs
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations. See the device errata for further details.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.14.3.3 48 MHz RC Oscillator (RCOSC_HF)

Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Frequency 48 MHz
Uncalibrated frequency accuracy ±1 %
Calibrated frequency accuracy(1) ±0.25 %
Start-up time 5 µs
(1) Accuracy relative to the calibration source (XOSC_HF)
8.14.3.4 2 MHz RC Oscillator (RCOSC_MF)

MIN TYP MAX UNIT
Calibrated frequency 2 MHz
Start-up time 5 µs
8.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)

MIN TYP MAX UNIT
Crystal frequency 32.768 kHz

CC1314R10
8.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF) (continued)

MIN TYP MAX UNIT
ESR Equivalent series resistance 30 100 kΩ
CL Crystal load capacitance 6 7(1) 12 pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.14.3.6 32 kHz RC Oscillator (RCOSC_LF)

MIN TYP MAX UNIT
Calibrated frequency 32.8 (1) kHz
Temperature coefficient. 50 ppm/°C
ADVANCE INFORMATION
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
8.14.4 Serial Peripheral Interface (SPI) Characteristics

8.14.4.1 SPI Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
Master Mode
12
1.8 < VDDS < 3.8
fSCLK Slave Mode
SPI clock frequency 8 MHz
1/tsclk 2.7 < VDDS < 3.8
Slave Mode
7
VDDS < 2.7
DCSCK SCK Duty Cycle 45 50 55 %
8.14.4.2 SPI Master Mode

tSCLK_H/ (tSPI/2) - (t /2) +
SCLK High or Low time tSPI / 2 SPI ns
L 1 1
tCS.LEAD CS lead-time, CS active to clock 1 SCLK
CS lag time, Last clock to CS
tCS.LAG 1 SCLK
inactive
CS access time, CS active to
tCS.ACC 1 SCLK
MOSI data out
CS disable time, CS inactive to
tCS.DIS 1 SCLK
MOSI high inpedance
tSU.MI MISO input data setup time(1) VDDS = 3.3V 12.5 ns
tSU.MI MISO input data setup time VDDS = 1.8V 23.5 ns
tHD.MI MISO input data hold time 0 ns
tVALID.M
MOSI output data valid time(2) SCLK edge to MOSI valid,CL = 20 pF (4) 13 ns
O
tHD.MO MOSI output data hold time(3) CL = 20 pF 0 ns
(1) The MISO input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge

CC1314R10
8.14.4.3 SPI Master Mode Timing Diagrams

ADVANCE INFORMATION
Figure 8-1. SPI Master Mode Timing

CC1314R10
8.14.4.4 SPI Slave Mode

tCS.LEAD CS lead-time, CS active to clock 1 SCLK
CS lag time, Last clock to CS
tCS.LAG 1 SCLK
inactive
tCS.ACC VDDS = 3.3V 56 ns
MISO data out
tCS.ACC VDDS = 1.8V 70 ns
MISO data out
tCS.DIS VDDS = 3.3V 56 ns
MISO high inpedance
tCS.DIS VDDS = 1.8V 70 ns
MISO high inpedance
ADVANCE INFORMATION
tSU.SI MOSI input data setup time 30 ns
tHD.SI MOSI input data hold time 0 ns
tVALID.S
MISO output data valid time(1) SCLK edge to MISO valid,CL = 20 pF, 3.3V (4) 50 ns
O
tVALID.S
MISO output data valid time(1) SCLK edge to MISO valid,CL = 20 pF, 1.8V (4) 65 ns
O
tHD.SO MISO output data hold time(2) CL = 20 pF 0 ns
(1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(2) Specifies how long data on the output is valid after the output changing SCLK clock edge

CC1314R10
8.14.4.5 SPI Slave Mode Timing Diagrams

ADVANCE INFORMATION
Figure 8-2. SPI Slave Mode Timing

CC1314R10
8.14.5 UART
8.14.5.1 UART Characteristics
UART rate 3 MBaud
8.15 Peripheral Characteristics

8.15.1 ADC
8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
ADVANCE INFORMATION
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample Rate 200 ksps
Offset Internal 4.3 V equivalent reference(2) –0.24 LSB
Gain error Internal 4.3 V equivalent reference(2) 7.14 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL Integral nonlinearity ±4 LSB
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.8
9.6 kHz input tone
9.8
9.6 kHz input tone, DC/DC enabled
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 10.1
ENOB Effective number of bits Internal reference, voltage scaling disabled, Bits
11.1
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal reference, voltage scaling disabled,
11.3
14-bit mode, 200 kSamples/s, 300 Hz input tone (5)
11.6
15-bit mode, 200 kSamples/s, 300 Hz input tone (5)
–65
9.6 kHz input tone
THD Total harmonic distortion VDDS as reference, 200 kSamples/s, 9.6 kHz input tone –70 dB
–72
60
9.6 kHz input tone
Signal-to-noise
SINAD,
and VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63 dB
SNDR
distortion ratio
68
70
9.6 kHz input tone
SFDR Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73 dB
75
Conversion time Serial conversion, time-to-output, 24 MHz clock 50 Clock Cycles
Current consumption Internal 4.3 V equivalent reference(2) 0.42 mA
Current consumption VDDS as reference 0.6 mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
Reference voltage 4.3(2) (3) V
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1

CC1314R10
8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)

Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.

Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TI-RTOS API in order to include the gain/offset
Reference voltage 1.48 V
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage VDDS as reference, input voltage scaling enabled VDDS V
VDDS /
Reference voltage VDDS as reference, input voltage scaling disabled V
2.82(3)
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance Input impedance depends on sampling frequency and sampling >1 MΩ
ADVANCE INFORMATION
time
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings at all times
(4) No missing codes
(5) ADC_output = Σ(4n samples ) >> n, n = desired extra bits

CC1314R10
8.15.2 DAC
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
General Parameters
Resolution 8 Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON 1.8 3.8
External Load(4), any VREF, pre-charge OFF, DAC charge-pump
VDDS Supply voltage 2.0 3.8 V
OFF
Any load, VREF = DCOUPL, pre-charge ON 2.6 3.8
Buffer ON (recommended for external load) 16 250
FDAC Clock frequency kHz
Buffer OFF (internal load) 16 1000
VREF = VDDS, buffer OFF, internal load 13
Voltage output settling time 1 / FDAC
ADVANCE INFORMATION
VREF = VDDS, buffer ON, external capacitive load = 20 pF(3) 13.8
External capacitive load 20 200 pF
External resistive load 10 MΩ
Short circuit current 400 µA
VDDS = 3.8 V, DAC charge-pump OFF 50.8
VDDS = 3.0 V, DAC charge-pump ON 51.7
Max output impedance Vref =
ZMAX VDDS, buffer ON, CLK 250 VDDS = 2.0 V, DAC charge-pump ON 48.7 kΩ
kHz
VDDS = 1.8 V, DAC charge-pump ON 46.3
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Differential nonlinearity ±1
Comparator
FDAC = 250 kHz
DNL LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Differential nonlinearity ±1.2
Comparator
FDAC = 16 kHz
VREF = VDDS = 3.8 V ±0.64
VREF = VDDS= 3.0 V ±0.81
Offset error(2) VREF = VDDS = 1.8 V ±1.27
Load = Continuous Time LSB(1)
Comparator VREF = DCOUPL, pre-charge ON ±3.43
VREF = DCOUPL, pre-charge OFF ±2.88
VREF = ADCREF ±2.37
VREF = VDDS= 3.8 V ±0.78
VREF = VDDS = 3.0 V ±0.77
Offset error(2) VREF = VDDS= 1.8 V ±3.46
Load = Low Power Clocked LSB(1)
Comparator VREF = DCOUPL, pre-charge ON ±3.44
VREF = VDDS = 3.8 V ±1.53
VREF = VDDS = 3.0 V ±1.71
Max code output voltage
variation(2) VREF = VDDS= 1.8 V ±2.10
LSB(1)
Load = Continuous Time VREF = DCOUPL, pre-charge ON ±6.00
Comparator

CC1314R10
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)

VREF = VDDS= 3.8 V ±2.92
VREF =VDDS= 3.0 V ±3.06
Max code output voltage
variation(2) VREF = VDDS= 1.8 V ±3.91
LSB(1)
Load = Low Power Clocked VREF = DCOUPL, pre-charge ON ±7.84
Comparator
VREF = VDDS = 3.8 V, code 1 0.03
VREF = VDDS = 3.8 V, code 255 3.62
VREF = VDDS= 3.0 V, code 1 0.02
VREF = VDDS= 3.0 V, code 255 2.86
ADVANCE INFORMATION

Output voltage range(2) VREF = VDDS = 1.8 V, code 255 1.71
Load = Continuous Time V
Comparator VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = ADCREF, code 1 0.01
VREF = VDDS= 3.8 V, code 255 3.61
VREF = VDDS= 3.0 V, code 255 2.85
Output voltage range(2) VREF = VDDS = 1.8 V, code 255 1.71
Load = Low Power Clocked V
External Load (Keysight 34401A Multimeter)
VREF = VDDS, FDAC = 250 kHz ±1
INL Integral nonlinearity VREF = DCOUPL, FDAC = 250 kHz ±1 LSB(1)
VREF = ADCREF, FDAC = 250 kHz ±1
DNL Differential nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 LSB(1)
VREF = VDDS= 3.8 V ±0.20
VREF = VDDS= 3.0 V ±0.25
VREF = VDDS = 1.8 V ±0.45
Offset error LSB(1)
VREF = DCOUPL, pre-charge ON ±1.55
VREF = VDDS= 3.8 V ±0.60
VREF = VDDS= 3.0 V ±0.55
Max code output voltage VREF = VDDS= 1.8 V ±0.60

LSB(1)
variation VREF = DCOUPL, pre-charge ON ±3.45

CC1314R10
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)

VREF = VDDS = 3.8 V, code 255 3.61
VREF = VDDS= 3.0 V, code 255 2.85
Output voltage range VREF = VDDS = 1.8 V, code 255 1.71
Load = Low Power Clocked V
ADVANCE INFORMATION
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter

CC1314R10
8.15.3 Temperature and Battery Monitor

8.15.3.1 Temperature Sensor
Resolution 2 °C
Accuracy -40 °C to 0 °C ±4.0 °C
Accuracy 0 °C to 105 °C ±2.5 °C
Supply voltage coefficient(1) 3.6 °C/V
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.15.3.2 Battery Monitor

Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
ADVANCE INFORMATION

Resolution 25 mV
Range 1.8 3.8 V
Integral nonlinearity (max) 23 mV
Accuracy VDDS = 3.0 V 22.5 mV
Offset error -32 mV
Gain error -1 %

CC1314R10
8.15.4 Comparators
8.15.4.1 Low-Power Clocked Comparator
Input voltage range 0 VDDS V
Clock frequency SCLK_LF
Using internal DAC with VDDS as reference voltage,
Internal reference voltage(1) 0.024 - 2.865 V
DAC code = 0 - 255
Offset Measured at VDDS / 2, includes error from internal DAC ±5 mV
Clock
Decision time Step from –50 mV to 50 mV 1
Cycle
(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See DAC Characteristics
ADVANCE INFORMATION
8.15.4.2 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
Input voltage range(1) 0 VDDS V
Offset Measured at VDDS / 2 ±5 mV
Decision time Step from –10 mV to 10 mV 0.78 µs
Current consumption Internal reference 8.6 µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.15.5 Current Source

8.15.5.1 Programmable Current Source
Current source programmable output range (logarithmic
0.25 - 20 µA
range)
Resolution 0.25 µA

CC1314R10
8.15.6 GPIO
8.15.6.1 GPIO DC Characteristics
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 1.56 V
GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.24 V
GPIO VOH at 4 mA load IOCURR = 1 1.59 V
GPIO VOL at 4 mA load IOCURR = 1 0.21 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 73 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 19 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.08 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.73 V
IH = 1, difference between 0 → 1
ADVANCE INFORMATION
GPIO input hysteresis 0.35 V

and 1 → 0 points
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 2.59 V
GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.42 V
GPIO VOH at 4 mA load IOCURR = 1 2.63 V
GPIO VOL at 4 mA load IOCURR = 1 0.40 V
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 282 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 110 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.97 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.55 V
IH = 1, difference between 0 → 1
GPIO input hysteresis 0.42 V
and 1 → 0 points
TA = 25 °C
Lowest GPIO input voltage reliably interpreted as a
VIH 0.8*VDDS V
High
Highest GPIO input voltage reliably interpreted as a
VIL 0.2*VDDS V
Low

CC1314R10
8.16 Typical Characteristics

All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions, Section 8.3, for device limits. Values exceeding these limits are for
reference only.
8.16.1 MCU Current
Running CoreMark, SCLK_HF = 48 MHz RCOSC 256 kB RAM Retention, no Cache Retention, RTC ON SCLK_LF = 32 kHz XOSC
6.5 18
6 15
5.5 12
Current [µA]
Current [mA]
5
9
ADVANCE INFORMATION
4.5
6
4
3
3.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
3 Temperature [°C]
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Voltage [V] Figure 8-4. Standby Mode (MCU) Current vs.
Figure 8-3. Active Mode (MCU) Current vs. Temperature
Supply Voltage (VDDS)
256 kB SRAM Retention, no Cache Retention, RTC ON, SCLK_LF = 32 kHz XOSC, VDDS = 3.6V
16
14
12
10
Current [µA]
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature [°C]
Figure 8-5. Standby Mode (MCU) Current vs.

Temperature (VDDS = 3.6 V)
8.16.2 RX Current
7.6 6
7.5
5.9
7.4
7.3 5.8
7.2 5.7
7.1
Current [mA]
Current [mA]
5.6
7
6.9 5.5
6.8
5.4
6.7
6.6 5.3
6.5 5.2
6.4
5.1
6.3
6.2 5
-40 -25 -10 5 20 35 50 65 80 95 105 -40 -25 -10 5 20 35 50 65 80 95 105
Temperature [°C] Temperature [°C]
Figure 8-6. RX Current vs. Figure 8-7. RX Current vs.

Temperature (50 kbps, 868.3 MHz) Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V)

CC1314R10
11
10.5
10
9.5
Current [mA]
8.5
7.5
6.5
5.5
5
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Voltage [V]
Figure 8-8. RX Current vs.

ADVANCE INFORMATION
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)

CC1314R10
8.16.3 TX Current
15 26
14.75 25
24
14.5
23
14.25
22
14
21
Current [mA]
Current [mA]
13.75 20
13.5 19
13.25 18
17
13
16
12.75
15
12.5
14
12.25 13
12 12
ADVANCE INFORMATION
-40 -25 -10 5 20 35 50 65 80 95 105 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Temperature [°C] Voltage [V]
Figure 8-9. TX Current vs. Figure 8-10. TX Current vs.

Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V) Supply Voltage (VDDS) (50 kbps, 868.3 MHz)

CC1314R10
Table 8-1 shows typical TX current and output power for different output power settings.
Table 8-1. Typical TX Current and Output Power
CC1314R10 at 868 MHz, VDDS = 3.6 V (Measured on CC1312-R7EM-XD7793)
txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA]
0x013F 14 14.6 25
0xB224 12.5 13.0 18.3
0x895E 12 12.6 17.4
0x669A 11 11.6 15.8
0x3E92 10 10.7 14.2
0x3EDC 9 9.7 13.3
0x2CD8 8 9.1 12.4
0x26D4 7 8.2 11.5
ADVANCE INFORMATION
0x20D1 6 7.2 10.6

0x1CCE 5 5.9 9.8
0x16CD 4 5.4 9.4
0x14CB 3 4.1 8.8
0x12CA 2 3.3 8.4
0x12C9 1 2.5 8.0
0x10C8 0 1.5 7.7
0x0AC4 -5 -4.6 6.1
0x0AC2 -10 -10.3 5.4
0x06C1 -15 -14.8 5.0
0x04C0 -20 -19.8 4.7

CC1314R10
8.16.4 RX Performance
-105 -105
-106 -106
-107 -107
-108 -108
Sensitivity [dBm]
Sensitivity [dBm]
-109 -109
-110 -110
-111 -111
-112 -112
-113 -113
-114 -114
-115 -115
ADVANCE INFORMATION
863 864 865 866 867 868 869 870 900 903 906 909 912 915 918 921 924 927 930
Frequency [MHz] Frequency [MHz]
Figure 8-11. Sensitivity vs. Figure 8-12. Sensitivity vs.

Frequency (50 kbps, 868 MHz) Frequency (50 kbps, 915 MHz)
-105 -105
-106 -106
-107 -107
-108 -108
Sensitivity [dBm]
Sensitivity [dBm]
-109 -109
-110 -110
-111 -111
-112 -112
-113 -113
-114 -114
-115 -115
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Figure 8-13. Sensitivity vs. Figure 8-14. Sensitivity vs.

Temperature (50 kbps, 868.3 MHz) Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
80
60
Selectivity [dB]
40
20
-20
-10 -8 -6 -4 -2 0 2 4 6 8 10
Frequency [MHz]
Figure 8-15. Selectivity vs.

Frequency Offset (50 kbps, 868.3 MHz) Figure 8-16. PER vs. Level vs.
Frequency (SimpleLink™ Long Range 5 kbps, 868
MHz)

CC1314R10
ADVANCE INFORMATION
Figure 8-17. PER vs. Level vs.

Frequency (Narrowband, 9.6 kbps, ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX bandwidth)

CC1314R10
8.16.5 TX Performance
14 14
13.8 13.9
13.6 13.8
13.4 13.7
Output Power [dBm]
Output Power [dBm]

13.2 13.6
13 13.5
12.8 13.4
12.6 13.3
12.4 13.2
12.2 13.1
12 13
ADVANCE INFORMATION
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100105 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Figure 8-18. Output Power vs. Figure 8-19. Output Power vs.
Temperature (50 kbps, 868.3 MHz) Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
14 14
13.9 13.9
13.8 13.8
13.7 13.7
Output Power [dBm]
Output Power [dBm]
13.6 13.6
13.5 13.5
13.4 13.4
13.3 13.3
13.2 13.2
13.1 13.1
13 13
863 864 865 866 867 868 869 870 902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz] Frequency [MHz]
Figure 8-20. Output Power vs. Figure 8-21. Output Power vs.
Frequency (50 kbps, 868 MHz) Frequency (50 kbps, 915 MHz)

CC1314R10
8.16.6 ADC Performance
11.4 Vin = 3.0 V Sine wave, Internal reference, F in = Fs ÷ 10

Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode 10.2
11.1
10.15
10.1
10.8
ENOB [Bit]
10.05
ENOB [Bit]
10.5
10
10.2 9.95
9.9
9.9
9.85
9.6
9.8
0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 40 50 70 100
ADVANCE INFORMATION
1 2 3 4 5 6 7 8 10 20 30 40 50 70 100 200
Frequency [kHz] Frequency [kHz]
Figure 8-22. ENOB vs. Figure 8-23. ENOB vs.
Input Frequency Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference, 200 ksps Vin = 3.0 V Sine wave, Internal reference, 200 ksps
1.5 2.5
1 2
0.5 1.5
DNL [LSB]
INL [LSB]
0 1
-0.5 0.5
-1 0
-1.5 -0.5
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000
ADC Code ADC Code
Figure 8-24. INL vs. Figure 8-25. DNL vs.
ADC Code ADC Code
Vin = 1 V, Internal reference, 200 ksps Vin = 1 V, Internal reference, 200 ksps
1.01 1.01
1.009 1.009
1.008 1.008
1.007 1.007
1.006
Voltage [V]
1.006
Voltage [V]
1.005 1.005
1.004 1.004
1.003 1.003
1.002 1.002
1.001 1.001
1 1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100105 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Figure 8-26. ADC Accuracy vs. Figure 8-27. ADC Accuracy vs.
Temperature Supply Voltage (VDDS)

CC1314R10
9 Detailed Description
9.1 Overview
Section 4 shows the core modules of the CC1314R10 device.
Throughout this section, see the Technical Reference Manual listed in Section 11.2 for more details.
9.2 System CPU
The CC1314R10 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M33 system CPU with TrustZone®,
which runs the application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
ADVANCE INFORMATION
Its features include the following:
• ARMv8-M architecture with TrustZone® security extension optimized for small-footprint embedded
applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• 8 regions of non-secure memory protected regions
• 8 regions of secure memory protected regions
• 4 regions of Security Attribute Unit (SAU)
• Single-cycle multiply instruction and hardware divide
• Digital-signal-processing (DSP) extension
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8 kB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation

CC1314R10
9.3 Radio (RF Core)

The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor
that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF core offers a high level, command-based
API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the
main CPU, which reduces power and leaves more resources for the user application. Several signals are also
available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
ADVANCE INFORMATION
even with over-the-air (OTA) updates while still using the same silicon.
Note
Not all combinations of features, frequencies, data rates, and modulation formats described in this
chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and
provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a
specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF
Studio tool with performance numbers of selected formats found in Section 8.

CC1314R10
9.3.1 Proprietary Radio Formats

The CC1314R10 radio can support a wide range of physical radio formats through a set of hardware peripherals
combined with firmware available in the device ROM, covering various customer needs for optimizing towards
parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy
protocols as well as customizing the behavior for specific application needs.
Table 9-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio
formats may be available in the form of radio firmware patches or programs through the Software Development
Kit (SDK) and may combine features in a different manner, as well as add other features.
Table 9-1. Feature Support
Feature Main 2-(G)FSK Mode High Data Rates Low Data Rates SimpleLink™ Long Range
Programmable preamble,
Yes Yes Yes No
sync word and CRC
ADVANCE INFORMATION
Programmable receive
Yes Yes Yes (down to 4 kHz) Yes
bandwidth
Data / Symbol rate(3) 20 to 1000 kbps ≤ 2 Msps ≤ 100 ksps ≤ 20 ksps
2-(G)FSK
2-(G)FSK
Modulation format 2-(G)FSK 4-(G)FSK 2-(G)FSK
4-(G)FSK
SUN-O-QPSK
Dual Sync Word Yes Yes No No
Carrier Sense (1) (2) Yes No No No
Preamble Detection(2) Yes Yes Yes No
Data Whitening Yes Yes Yes Yes
Digital RSSI Yes Yes Yes Yes
CRC filtering Yes Yes Yes Yes
1:2
Direct-sequence spread
No No No 1:4
spectrum (DSSS)
1:8
Forward error correction
No No No Yes
(FEC)
Link Quality Indicator (LQI) Yes Yes Yes Yes
(1) Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance
with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.
(2) Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.
(3) Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a
smaller range might be supported.

CC1314R10
9.4 Memory
The up to 1024 kB nonvolatile (Flash) memory provides storage for code and data. The flash memory is
in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to eight 32 kB blocks and can be used for
both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by
default and included in Standby mode power consumption numbers.Parity checking for detection of bit errors in
memory is built-in, which reduces chip-level soft errors and thereby increases reliability. Parity can be disabled
for an additional 32 kB which can be allocated for general purpose SRAM. System SRAM is always initialized to
zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8 kB cache is enabled by default to cache and prefetch instructions read by the system CPU.
ADVANCE INFORMATION
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
There is a 4 kB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically
used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by
the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,
which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that
can be used for initial programming of the device.

CC1314R10
9.5 Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary
power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby
significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable
state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power
• 2 MHz low-power mode enables lowest possible handling of digital sensors
ADVANCE INFORMATION
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces
C driver source code, which the System CPU application uses to control and exchange data with the Sensor
Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
• Very low-power pulse counting (flow metering)
• Key scan
The peripherals in the Sensor Controller include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital
converter, and a comparator. The continuous time comparator in this block can also be used as a higher-
accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline
tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive
sensing.
• The ADC is a 12-bit 200 ksps ADC with eight inputs and a built-in voltage reference. The ADC can be
triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI master with up to 6 MHz clock speed
The peripherals in the Sensor Controller can also be controlled from the main application processor.

CC1314R10
9.6 Cryptography
The CC1314R10 device comes with a wide set of modern cryptography-related hardware accelerators,
drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit
of being lower power and improves availability and responsiveness of the system because the cryptography
operations runs in a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The
hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128, 192 and 256 bit key lengths
ADVANCE INFORMATION
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available
for an application or stack:
• Key Agreement Schemes
– Elliptic Curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Processing
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
– Edwards-curve Digital Signature Algorithm (EdDSA)
• Curve Support
– Short Weierstrass form, such as:
• NIST-P224 (secp224r1), NIST-P256 (secp256r1), NIST-P384 (secp384r1), NIST-P521 (secp521r1)
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
– Montgomery form, such as:
• Curve25519
– Twisted Edwards form, such as:
• Ed25519
• Message Authentication Codes
– AEC CBC-MAC
– AES CMAC
– HMAC with SHA224, SHA256, SHA384 and SHA512
• Block cipher mode of operation
– AES CCM and AES CCM-Star
– AES GCM
– AES ECB
– AES CBC
– AES CTR
• Hash Algorithm
– SHA224
– SHA256
– SHA384
– SHA512
• True random number generation
Other capabilities, such as RSA encryption and signatures (using keys as large as 2048 bits) as well as other
ECC curves such as Curve1174, can be implemented using the provided public key accelerator but are not part
of the TI SimpleLink SDK for the CC1314R10 device.

CC1314R10
9.7 Timers
A large selection of timers are available as part of the CC1314R10 device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the
Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the
RTC halts when a debugger halts the device.
• General Purpose Timers (GPTIMER)
ADVANCE INFORMATION
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each
edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or
periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as
well as for PWM output or waveform generation.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields
in the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt and reset the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer continues to run in Standby power mode but
pauses when a debugger halts the device.
• Always On Watchdog Timer (AON_WDT)
The Always On Watchdog Timer is used during standby to regain control when the system has failed due to
a software error or failure of an external device to respond in the expected way. It generates a reset when its
configured time-out counter reaches zero and cannot be stopped once started, unless by asserting a device
reset. The Always-on watchdog timer runs in Standby power mode and may pause when a debugger halts
the device.

CC1314R10
9.8 Serial Peripherals and I/O

The SPI interface provides a standardized synchronous serial interface to communicate with devices compatible
with SPI (3 and 4 wire), MICROWIRE and TI Synchronous Serial Format. The SPIs support master/slave
operation up to 12 MHz, programmable clock bit rate with prescaler, as well as configurable phase and polarity.
The UART interface implements universal asynchronous receiver and transmitter functions. The UART supports
flexible baud-rate generation up to a maximum of 3 Mbps with FIFO, multiple data sizes, stop and parity bits as
well as hardware handshake.
The I2S interface provides a standardized interface to exchange digital audio with devices compatible with this
standard, including ADCs, DACs and CODECs. The I2S can also receive pulse-density modulation (PDM) data
from devices such as digital microphones and perform conversion to PCM data.
The I2C interface enables low speed serial communications with devices compatible with the I2C standard. The
I2C interface can handle both standard (100 kHz) and fast (400 kHz) speeds, as well as four modes of operation:
ADVANCE INFORMATION
master transmit/receive and slave transmit/receive.

The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to
any digital pin on the device.
9.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC1314R10 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.11 Debug
The debug subsystem implements two IEEE standards for debug and test purposes:
IEEE 1149.7 Class 4: Reduced-pin and Enhanced-functionality Test Access Port and Boundary-scan
Architecture. This is known by the acronym cJTAG (compact JTAG) and this device uses only two pins to
communicate to the target: TMS (JTAG_TMSC) and TCK (JTAG_TCKC). This is the default mode of operation.
IEEE standard 1149.1: Test Access Port and Boundary Scan Architecture Test Access Port (TAP). This
standard is known by the acronym JTAG and this device uses four pins to communicate to the target: TMS
(JTAG_TMSC), TCK (JTAG_TCKC), TDI (JTAG_TDI) and TDO (JTAG_TDO).

CC1314R10
The debug subsystem also implements a user-configurable firewall to control unauthorized access to debug/test
ports.
ADVANCE INFORMATION

CC1314R10
9.12 Power Management

To minimize power consumption, the CC1314R10 supports a number of power modes and power management
features (see Table 9-2).
Table 9-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES RESET PIN
MODE
ACTIVE IDLE STANDBY SHUTDOWN HELD
CPU Active Off Off Off Off

Flash On Available Off Off Off
SRAM On On Retention Off Off
Supply System On On Duty Cycled Off Off
Register and CPU retention Full Full Partial No No
SRAM retention Full Full Full No No
ADVANCE INFORMATION
48 MHz high-speed clock XOSC_HF or XOSC_HF or

Off Off Off
(SCLK_HF) RCOSC_HF RCOSC_HF
2 MHz medium-speed clock
RCOSC_MF RCOSC_MF Available Off Off
(SCLK_MF)
32 kHz low-speed clock XOSC_LF or XOSC_LF or XOSC_LF or
Off Off
(SCLK_LF) RCOSC_LF RCOSC_LF RCOSC_LF
Peripherals Available Available Off Off Off
Sensor Controller Available Available Available Off Off
Wake-up on RTC Available Available Available Off Off
Wake-up on pin edge Available Available Available Available Off
Wake-up on reset pin On On On On On
Brownout detector (BOD) On On Duty Cycled Off Off
Power-on reset (POR) On On On Off Off
Watchdog timer (WDT) Available Available Paused Off Off
Always-on Watchdog timer
Available Available Available Off Off
(AON_WDT)
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see Table 9-2).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and
the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O
pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.

CC1314R10
The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller
independently of the system CPU. This means that the system CPU does not have to wake up, for example to
perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would
otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,
control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be
controlled by the system CPU.
Note
The power, RF and clock management for the CC1314R10 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in
the TI-provided drivers that are part of the CC1314R10 software development kit (SDK). Therefore,
TI highly recommends using this software framework for all application development on the device.
The complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in
source code.
ADVANCE INFORMATION
9.13 Clock Systems
The CC1314R10 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by
the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator
(RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for
ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after
Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768
kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost.
9.14 Network Processor
Depending on the product configuration, the CC1314R10 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.

CC1314R10
10 Application, Implementation, and Layout

Note
Information in the following Applications section is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC1314R10
ADVANCE INFORMATION
device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
CC1312-R7EM-XD7793 The CC1312-R7EM-XD7793 reference design provides schematic, layout and
Design Files production files for the characterization board used for deriving the performance
number found in this document.
LP-EM-CC1314R10 Design The CC1314R10 LaunchPad Design Files contain detailed schematics and
Files layouts to build application specific boards using the CC1314R10 device.
Sub-1 GHz and 2.4 GHz The antenna kit allows real-life testing to identify the optimal antenna for your
Antenna Kit for LaunchPad™ application. The antenna kit includes 16 antennas for frequencies from 169 MHz
Development Kit and to 2.4 GHz, including:
SensorTag • PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.

CC1314R10
10.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T J = ψJT × P + Tcase (1)
2. From board temperature:

T J = ψJB × P + Tboard (2)
3. From ambient temperature:

T J = RθJA × P + TA (3)
ADVANCE INFORMATION
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Section 8.8.
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the
peak power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current
consumption.

CC1314R10
11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Tools and Software
The CC1314R10 device is supported by a variety of software and hardware development tools.
Development Kit
CC1314R10 The CC1314R10 LaunchPad™ Development Kit enables development of high-
LaunchPad™ performance Sub-1 GHz wireless applications that benefit from low-power operation. The
Development Kit kit features the CC1314R10 Sub-1 GHz SimpleLink Wireless MCU. The kit works with the
LaunchPad ecosystem, easily enabling additional functionality like sensors, display, and
more.
ADVANCE INFORMATION
LP-XDS110 The LP-XDS110 LaunchPad™ Debug Probe enables development of high-performance

LaunchPad™ wireless applications in the entire family of LP-EM LaunchPad™ development boards.
Debug Probe Featuring a seamless connection with the new 20-pin LP-EM Debug connector, it supports
not only multiple standards such as JTAG/cJTAG/SWD but also a UART backchannel
for maximum debugging flexibility. It also features an Arm® 10-pin Debug connector to
perform debugging in any custom board.
LP-XDS110ET The LP-XDS110ET LaunchPad™ Debug Probe enables development of high-performance

LaunchPad™ wireless applications in the entire family of LP-EM LaunchPad™ development boards.
Debug Probe Featuring a seamless connection with the new 20-pin LP-EM Debug connector, it supports
not only multiple standards such as JTAG/cJTAG/SWD but also a UART backchannel
for maximum debugging flexibility. In addition, it also features an Arm® 10-pin Debug
connector to perform debugging in any custom board. This Debug Probe also features
the XDS110 EnergyTrace™ technology, which is a new method for measuring the current
consumption that captures the complete operational profile of the wireless MCU.
TMDSEMU110-U The TMDSEMU110-U Debug Probe enables development of high-performance wireless

Debug Probe applications in the entire family of SimpleLink LaunchPad™ development boards. Featuring
a convenient enclosure, which grants the proper mechanical robustness for field and
production environments, it supports not only multiple standards such as JTAG/cJTAG/SWD
but also a UART backchannel and four GPIOs for maximum debugging flexibility. In
addition, the expansion connector allows using the TMDSEMU110-ETH add-on (sold
separately), which adds the full featured XDS110 EnergyTrace™ technology with variable
supply voltage from 1.8V to 3.6V and up to 800 mA of supply current. The XDS110
EnergyTrace™ technology is a new method for measuring the current consumption that
captures the complete operational profile of the wireless MCU.
Software
SimpleLink™ The SimpleLink LOWPOWER F2 Software Development Kit (SDK) provides a complete
LOWPOWER F2 package for the development of wireless applications on the CC13XX / CC26XX family of
SDK devices. The SDK includes a comprehensive software package for the CC1314R10 device,
including the following protocol stacks:
• Bluetooth Low Energy 4 and 5.3
• Thread (based on OpenThread)
• TI Z-Stack (Zigbee 3.0)
• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and
2.4 GHz

CC1314R10
• EasyLink - a large set of building blocks for building proprietary RF software stacks
• Multiprotocol support - concurrent operation between stacks using the Dynamic
Multiprotocol Manager (DMM)
• TI Wi-SUN FAN Stack
• Matter
The SimpleLink LOWPOWER F2 SDK is part of TI’s SimpleLink MCU platform, offering a
single development environment that delivers flexible hardware, software and tool options
for customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit ti.com/simplelink.
Development Tools
Code Composer Code Composer Studio is an integrated development environment (IDE) that supports TI's
Studio™
ADVANCE INFORMATION
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
Integrated suite of tools used to develop and debug embedded applications. It includes an optimizing
Development C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
Environment other features. The intuitive IDE provides a single user interface taking you through each
(IDE) step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available for
TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
Studio™ Cloud build CCS and Energia™ projects. After you have successfully built your project, you can
IDE download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded IAR Embedded Workbench® is a set of development tools for building and debugging
Workbench® for embedded system applications using assembler, C and C++. It provides a completely
Arm® integrated development environment that includes a project manager, editor, and build
tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box
on most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 kB size-limited version is available through iar.com.
SmartRF™ SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
Studio SimpleLink Wireless MCUs from Texas Instruments. The application will help designers
of RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing
and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device.
Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches

CC1314R10
Sensor Controller Sensor Controller Studio is used to write, test and debug code for the Sensor Controller
Studio peripheral. The tool generates a Sensor Controller Interface driver, which is a set of C
source files that are compiled into the System CPU application. These source files also
contain the Sensor Controller binary image and allow the System CPU application to control
and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
• Ready-to-use examples for several common use cases
• Full toolchain with built-in compiler and assembler for programming in a C-like
programming language
• Provides rapid development by using the integrated sensor controller task testing
and debugging functionality, including visualization of sensor data and verification of
algorithms
UniFlash UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash
ADVANCE INFORMATION
has a GUI, command line, and scripting interface. UniFlash is available free of charge.
11.1.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering
flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
11.2 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC1314R10 . In the upper right corner, click on Alert me to register
and receive a weekly digest of any product information that has changed. For change details, review the revision
history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer
TI Resource Explorer Software examples, libraries, executables, and documentation are available for your
device and development board.
Errata
CC1314R10 Silicon The silicon errata describes the known exceptions to the functional specifications
Errata for each silicon revision of the device and description on how to recognize a device
revision.
Application Reports
All application reports for the CC1314R10 device are found on the device product folder at: ti.com/product/
CC1314R10/technicaldocuments.
Technical Reference Manual (TRM)
CC13x4, CC26x4 SimpleLink™ Wireless The TRM provides a detailed description of all modules and
MCU Technical Reference Manual peripherals available in the device family.
11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

CC1314R10
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
SimpleLink™, LaunchPad™, EnergyTrace™, Code Composer Studio™, and TI E2E™ are trademarks of Texas
Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH.
Arm®, Cortex®, and TrustZone® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Wi-SUN® is a registered trademark of Wi‑SUN Alliance.
mioty® is a registered trademark of Fraunhofer-Gesellschaft.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Arm Thumb® are registered trademarks of Arm Limited (or its subsidiaries).
ADVANCE INFORMATION
is a registered trademark of Arm Limited.
Eclipse® is a registered trademark of Eclipse Foundation.
IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

CC1314R10
12 Mechanical, Packaging, and Orderable Information

12.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Note
The RSK (S-PQVFN-N64) package drawings in this datasheet are preliminary and will change for the
production release of this IC. The change will be related to the exposed thermal pad size of the IC.
The current sample has a 3.7 mm x 3.7 mm thermal ground pad. Production devices will have a 4.7
mm x 4.7mm thermal ground pad. It is recommended to design the thermal ground pad to be 4.7
mm x 4.7 mm, with a stencil opening of 3.7 mm x 3.7mm for pre-production devices. For production
devices, only the stencil will need to change to 4.7 mm x 4.7 mm. No change to the PCB will be
ADVANCE INFORMATION
required.

CC1314R10
PACKAGE OUTLINE
RGZ0048A VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
7.1 A
B 6.9
7.1
PIN 1 INDEX AREA 6.9
ADVANCE INFORMATION
1 MAX
C
SEATING PLANE
0.05 0.08 C
0.00
2X 5.5
5.15±0.1 (0.2) TYP

13 24
44X 0.5
12
25
2X SYMM
5.5
1 36
PIN1 ID 48X 0.30
0.18
48 37
(OPTIONAL)
SYMM 0.1 C A B
48X 0.5
0.3 0.05 C
4219044/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com

CC1314R10
EXAMPLE BOARD LAYOUT

2X (6.8)
( 5.15)
SYMM
48X (0.6) 48 35
48X (0.24)
44X (0.5) 1
34
ADVANCE INFORMATION
SYMM
2X 2X
(5.5) (6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
23
12
21X (Ø0.2) VIA

TYP
13 22
2X (1.26) 2X (1.065)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX 0.07 MIN SOLDER MASK

ALL AROUND ALL AROUND OPENING
EXPOSED METAL EXPOSED METAL

METAL
SOLDER MASK METAL UNDER
OPENING NON SOLDER MASK SOLDER MASK
SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219044/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com

CC1314R10
EXAMPLE STENCIL DESIGN

2X (6.8)
SYMM ( 1.06)
48X (0.6)
48X (0.24)
44X (0.5)
ADVANCE INFORMATION
SYMM
2X 2X
(5.5) (6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
2X
2X (0.63)
(1.26)
2X (5.5)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

CC1314R10
ADVANCE INFORMATION

CC1314R10
ADVANCE INFORMATION

CC1314R10
ADVANCE INFORMATION

PACKAGE OPTION ADDENDUM
www.ti.com 14-Jun-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
XCC1314R106T0RGZ ACTIVE VQFN RGZ 48 260 TBD Call TI Call TI -40 to 105 Samples
XCC1314R106T0RSK ACTIVE VQFN RSK 64 4000 TBD Call TI Call TI -40 to 105 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Jun-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
7.1 A
B 6.9
(0.1) TYP
7.1 SIDE WALL DETAIL

PIN 1 INDEX AREA 6.9 OPTIONAL METAL THICKNESS
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.05 0.08 C
0.00
2X 5.5
5.15±0.1 (0.2) TYP

13 24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
2X SYMM
5.5
1 36
PIN1 ID 48X 0.30
0.18
48 37
(OPTIONAL)
SYMM 0.1 C A B
48X 0.5
0.3 0.05 C
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
2X (6.8)
( 5.15)
SYMM
48X (0.6) 48 37
48X (0.24)
44X (0.5) 1
36
2X SYMM 2X
(5.5) (6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
13 24
2X (1.26) 2X (1.065)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX 0.07 MIN SOLDER MASK

ALL AROUND ALL AROUND OPENING
EXPOSED METAL EXPOSED METAL

METAL
SOLDER MASK METAL UNDER
OPENING NON SOLDER MASK SOLDER MASK
SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
2X (6.8)
SYMM ( 1.06)
48X (0.6) 48 37
48X (0.24)
44X (0.5) 1
36
2X SYMM 2X
(5.5) 2X (6.8)
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
13 2X 24
2X (0.63)
(1.26)
2X (5.5)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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CC1314R10

SWRS270A – DECEMBER 2022 – REVISED JUNE 2023

CC1314R10 SimpleLink™ High-Performance Sub-1 GHz Wireless MCU

– Grid communications – wireless

– Elevators and escalators – elevator main speakers, set-top box

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4 Functional Block Diagram

Figure 4-1. CC1314R10 Block Diagram

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7.6 Connection of Unused Pins and Module – RSK 9.10 µDMA...................................................................... 54

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7 Terminal Configuration and Functions

Figure 7-1. RGZ (7 mm × 7 mm) Pinout, 0.5 mm Pitch (Top View)

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7.2 Signal Descriptions – RGZ Package

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Table 7-1. Signal Descriptions – RGZ Package (continued)

7.3 Connections for Unused Pins and Modules – RGZ Package

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7.4 Pin Diagram – RSK Package (Top View)

Figure 7-2. RSK (8 mm × 8 mm) Pinout, 0.4 mm Pitch (Top View)

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7.5 Signal Descriptions – RSK Package

DIO_7 16 I/O Digital GPIO, high-drive capability

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Table 7-3. Signal Descriptions – RSK Package (continued)

7.6 Connection of Unused Pins and Module – RSK Package

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8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Power Supply and Modules

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8.5 Power Consumption - Power Modes

PARAMETER TEST CONDITIONS TYP UNIT

I2S Delta current with clock enabled, module is idle 22.2

(1) Only one UART running

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8.6 Power Consumption - Radio Modes

8.7 Nonvolatile (Flash) Memory Characteristics

8.8 Thermal Resistance Characteristics

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8.9 RF Frequency Bands

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8.10 861 MHz to 1054 MHz - Receive (RX)