Journal Paper-Design and Development of Compact DC DC Converter

Advancement of Signal Processing and its Applications
Volume 5 Issue 1
DOI: https://doi.org/10.5281/zenodo.6656062
Design and Development of Compact DC-DC Converter Unit

from Air Craft
K. Umesha
Department of Electrical and Electronics Engineering, Jawaharlal College of Engineering
and Technology, Kerala, Karnataka, India
Corresponding Author
E-Mail Id: umesh_nandhini@yahoo.co.in
ABSTRACT
Efficient conversion of Electrical power is becoming a primary concern to aircrafts.
Switching power supplies (SMPS) offer not only higher efficiencies but also offer greater
flexibility to the designer. This paper depicts an overview of all the issues involved in
designing S.M.P.S. It describes the operation of the fly back topology, its relevant
parameters, circuit design tips, and information to select the most suitable semiconductor
and passive components. Regulation of the output is carried out by the feedback concept.
S.M.P.S. operates on a fixed frequency pulse width modulation basis compensates for
changes in the input and output load. The error voltage is used by dedicated control logic to
terminate the drive pulse to the main power switch at the correct instance. Delays in the
control loop are kept to a minimum, Hence, very high speed components must be selected for
the loop. Electronic isolation is achieved by using an opto-isolator S.M.P.S. topology
contains a power transformer provides isolation, voltage scaling through the turns ratio, and
multiple outputs. In this proposed project, dc-dc converter fly back technology is found as
more effective in terms of cost, size & performance. Converter is specially designed and
developed for tight regulation with special considerations to satisfy the operating conditions
of critical loads in aircrafts. The fly back converter switching power supply is the best choice
for output 10 watts to 120 watts with multiple outputs.
Keywords: SMPS, PWM, regulation, flyback, Isolation, duty ratio, actuators
INTRODUCTION (FAA) and military norms, and are lenient

Airplane power systems present an toward most power quality irregularities.
extraordinary arrangement of power
quality issues in a climate that requests Efficiency, size, and cost are the primary
the most elevated level of dependability advantages of switching power converters
of the hardware being controlled. switching power converter efficiencies
can run between 70-80%, The DC-DC
Due to the ever increasing amount of Converter is designed to provide DC
microprocessor-based flight systems, voltages. A power supply is called as
navigation and communications power converter and the power
equipment being incorporated into today’s conditioner. Typical application of power
aircraft, power quality is of the utmost supplies includes
importance.
A SMPS provides the source through low
Hardware intended for use in airplane is loss components such as capacitors,
ordinarily very robust, being planned as inductors, and transformers and solid state
per Federal Aviation Administration switches. The use of switches in one of
HBRP Publication Page 1-29 2022. All Rights Reserved Page 1

Volume 5 Issue 1
two states, ON or OFF leads to least ongoing streaming with high voltage
power dissipation and power conversion across the gadget. This results in a much
can be accomplished with minimal power lower power being dissipated within the
loss, which equates to high efficiency. supply. The typical exchanging power
supply displays efficiencies of between70
Switching regulator is a switching circuit to 90 percent, no matter what the input
that operates in a closed loop system to voltage.
regulate the power output. Switching
power supplies offer greater flexibility to During the "on" period, energy is being
the designer. put away inside the center material of the
inductor as transition. There is adequate
LINEAR VERSUS SWITCHING energy put away to convey the necessities
POWER SUPPLIES of the heap during the following off
The linear regulator operates by reducing period. The following time frame is the
a higher input voltage down to the lower "off" time of the power switch.
output voltage by linearly controlling the
conductivity of a series pass power device When the power switch turns off, the
in response to changes in its load. xdeinput voltage of the inductor flies
below ground and is clamped at one diode
This outcomes in an enormous voltage drop below ground by the catch
being set across the pass unit with the diode.Current presently starts to move
load current moving through it. This loss through the catch diode in this way
(Vdrop xI load) causes the linear regulator to keeping up with the heap current loop.
only be 30 to 50 percent efficient. Each This eliminates the put away energy from
watt delivered to the load, at least a watt the inductor.
has to be dissipated as heat. The cost of
the heat sinks actually makes the linear Yet again this period closes when the
regulator uneconomical above 10 watts power switch is turned on. Guideline is
for small applications. Underneath that achieved by fluctuating the on-to-off the
point, notwithstanding, they are duty cycle of the power switch. The
financially savvy in step-down relationship which approximately
applications. describes its operation is (∂ = ton/ (ton + t
easy way
The exchanging controller works the to comply with the conference paper
power gadgets in the full-on and cutoff. formatting necessities is to involve this
This then brings about either enormous record as a format and basically type your
flows being gone through the power text into it.
gadgets with a low "on" voltage or no
DESIGN OF FLY BACK CONVERTER

Design Specifications
The following are the specifications of the proposed flyback converter
Output voltages: Vo1=15v@3A,Vo2=±5v@2A & Vo3=27v@1A
Output ripple: 1% ofV0
Output current: Io=3A
Switching frequency (under worst case): fs=100 kHz
Supply voltage: 18 to 36v
Diode drop: VD=1.0v

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Resistive drop due to inductor resistance and transformer winding: (Vrl) =10% of Vo
D max: 70%
Window utilization factor: K=0.4
Efficiency: (η) =0.8
V cc min: 18V DC
V cc max: 36V DC
Design Steps
Step 1: To find output power
P02 = ∑ki=1 Voi

′
Ioi - (1)
Where
𝑉𝑜𝑖′ = 𝑉𝑜𝑖 + 𝑉𝐷 (2)
VD =Diode drop in ith secondary winding

VD =1 V (Assumed)
𝐼𝑜𝑖 is the output current of ith winding
P02 = (16 × 3 + 6 × 2 + 28 × 1 + 6 × 2)
P02 = 100 watts
Step 2: To find the transformer peak primary current
It is necessary to calculate the transformer peak primary current first, which is also equal to
transistor peak collector current or (MOSFET’s Drain current).
From the fundamental inductor voltage relationship, the rate of rise is determined by
di
V = L dt (3)
The input voltage may be written as
Ipp
Vin = LP [ t ] (4)
c
Taking
1 f
=D (5)
tc max
Then above eqn becomes

L I f
Vin min = [ DP PP ] (6)
max
Where Vin =dc output voltage in volts

LP =Transformer primary inductance in mH
Ipp =Peak transformer current in Amps
Dmax =Maximum duty cycle in µsecs

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f=Switching frequency in KHz
The output power in complete energy transformer mode is equal to the energy stored per
cycle times the operating frequency,
2
Pout = ½Lp Ipp f (7)
Dividing eqn (2.14) by eqn (2.13) we get
Pout Lp I2pp fDmax

= (8)
Vin min 2Lp Ipp f
The transformer peak primary current is given by

Ipp=Ipmin (Assume)
2Pout
Ipmin = Ic = V (9)
×D
in(min) max
2 × 100
Ipmin = Ic = = 15.87Amps
18 × 0.7
Step 3: To find the primary inductance

For this we can derive the primary inductance necessary to produce that peak current needed
within the allowed time period.
.
Vin(min) ×Dmax
Lp(max) = (10)
Ipp(min) ×f
18 × 0.7
Lp(max) =
15.87X90 × 103
(Worst case f=90 kHz)

𝐿𝑝(𝑚𝑎𝑥) =8.822µ H
This calculation is performed at the is recommended that a small amount of

lowest specified input voltage and the full voltage margin be included in the above
rated load. If the secondary requires the calculation so that we can guarantee
balance of time to empty the power, the regulation while including the tolerances
fly back converter will fall out of in the construction of the transformer.
regulation just below this input voltage. It
Step4: To find minimum and maximum duty cycles
Relate minimum and maximum duty cycles. In fly back converter, regulation is accomplished
by varying the duty cycle of the switch through pre-determined limits, which is designated as
D min and D max. If the converter input voltage varies from Vin min to Vin max the
Dmax
Dmin = V (11)
Dmax +(1−Dmax ) ccmax
Vccmin

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Dmin = 0.538 & Dmax=0.7 (worst case assumed)
0.7
Dmin =
36
0.7 + (1 − 0.7) 18
Therefore the converter will operate over the duty ratio range of 0.538<D<0.7 for the input
voltage range of 36 Vdc > V in > 18Vdc.
Now we can select a core and start the design of physical transformer.
Step5: Selection of Core

The area product for the converter configuration is given by
1 4D 4(1−D)
P02 [ √ +√ ]
n 3 3
Ap = (12)
KW JBmax fs
Where
fs=switching frequency=90 kHz
Kw=0.2(Window factor)
B max=maximum flux density=0.2 Tesla=0.2wb/m2
D max=0.7
J=current Density=4Amp/mm2=4x10-6 Amp/mt2
1 4x0.7 4(1 − 0.7)

100 [0.7 √ 3 + √ ]
3
Ap =
0.2x4x10−6 x0.2x90x103
=1.333 mm4
For this value of Ap, from Appendix EE 42/15 core is selected. For this core the cross
sectional area is Ac=1.82x100=182 mm2 Window area Aw =2.56×100mm2=256
Step 6: Calculation of Core Air Gap Length Lg
The fly back converter is operating single thus lowering the working flux density for
ended; that is the transformer-choke uses the same dc bias.
just half the flux capacity. Since the
current and flux never go negative. This If an EE type core or similar type is used
fact may drive core into saturation. To to construct the transformer- choke, the
handle this problem two solutions are counter legs may be gapped to the air gap
possible, first use a core with very large length Lg or Lg may be equally divided
volume or second introduce an air gap in between the outside legs of the core if a
the flux path to flatten the hysteresis loop, spacer is used.
Now the estimated air gap should be calculated by

µ0 N2t AC
Lg = (13)
Lpri
H
µ0 = 4π × 10−7
mt

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Ac = 182mm2
4πx10−7 x8x8x182x10−6
Lg =
9x10−6
Lg=1.626mm
Step 7: Turns Ratio for Each Winding

(V +V ) [(1−D )]
Turns ratio n= V01 D [ D max ] (14)
ccmin max
For 27V:n1
(27 + 1.0) [(1 − 0.7)]
n1 = [ ] = 0.667
18 0.7
For 15V:n2
(15 + 1.0) [(1 − 0.7)]
n2 = [ ] = 0.381
18 0.7
For ±5V; n3 =n4
(5 + 1.0) [(1 − 0.7)]
n3 = [ ] = 0.143
18 0.7
Step 8: Calculation of primary number of turns

The number of turns needed for primary winding, can be obtained by
V ×Dmax
Npri = ccmax (15)
A B f
c m c
36 × 0.7
Npri = = 7.69 ≅ 8turns
182 × 0.2 × 10−6 × 90 × 103
At this point, it is always advisable to Step 9: Calculation of Secondary Number

double check peak excursion of the flux of Turns
density at the input voltage at which the
supply is expected to operate most during The turns required for the secondary must
its life. The B max should not exceed 50% remove all the stored energy from the core
of the saturation flux density. If it exceeds prior to the beginning of the next power
65 to 70 % then it is advised to increase switch conduction period, so the
the air gap and recalculate the needed minimum time period for this to happen is
turns. Operating with too high B max will once again at the minimum specified
lead to problems at the upper end of the input voltage line when the power
specified input voltage and at high switches conduction period is at its
temperature maximum.
So the number of secondary turns can be obtained by

[Npri (Vo ut +VD )(1−Dmax )]
Nsec(max) = [Vin(min) ×Dmax ]
(16)
Where 𝑉𝐷 =forward voltage drop of the rectifier
[8(27+1.0)(1−0.7)]
Nsec(max) = [18×0.7]
= 5.333
Nsec(max) ≅ 6turns

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If the calculation result in Non-integer number of turns round off to the closest integer
number.
The secondary turns can also be found by the following steps

a) Find turns ratio for each secondary winding.
b) Multiply turn’s ratio of each secondary winding by primary number turns to get the actual
secondary number of turns.
Now actual secondary of turns is given by

N2(1) = n1 × Npri = 0.667 × 8 ≅ 6turns
N2(1) ≅ 6turns
N2(2) = n2 × Npri = 0.381 × 8 ≅ 3 turns
N2(2) ≅ 3 turns
N2(3) = N2(4) = n3 × Npri = 0.143 × 8 ≅ 1.1446turns
For bias winding 12 V is required to operate IC3842 therefore 3 turns are taken on secondary
side bias winding.
Step 10: Wire Gauge Selection

Choose a design current density value of J=400 circular mills/A for winding the magnetic
wires. We know that
2Pout
Ipp = Imin = V (17)
in(min) ×Dmax
2 × 100
Ipp = = 15.87Amps
18 × 0.7
Then 400Cm/AX15.87A=6348C.m (Circular mills)

A = d2
36 − n 2
An = (5 × 92 )
39
An is the circular mil area for the AWG size n =12

Which corresponds to approximately AWG NO.12 which has a diameter of 0.0847 inches,
which is, of course, is impractically large in diameter. Therefore a number of a smaller
diameter wires in parallel with an equal circular mill area would be used.
To minimize the losses due to skin effect, eight wires of AWG-21(1290C.m) are used in
parallel which corresponds to above 6348C.m to carry 15.37 Amps.
For secondary winding

Taking Irms= 1.5 Idc (out)
For 27 V output: S1=AWG- 23 (for I avg =1.5A)
For 15 V output: S2=AWG-18 (for Iavg =4.5A)
For 5V output: S3&S4=AWG-20 (for Iavg =3.0A)
For bias output: S5=AWG- 20 (for Iavg =3.0A)

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Conclusion from Transformer Design

Selected core: EE 42/15 Ferrite core
Primary inductance: 8.5uH
Length of air gap : 1.62 mm
Number of primary turns: 8
Number of bias turns: 3
Number of secondary turns (+27volt output):6
Number of secondary turns (15volt output):3
Number of secondary turns (±5volt output):1
Wire gauge selection:
For primary winding: AWG-21
Note: EE 42/15 bobbin contains total Design of Power MOSFET

16pins. The pins are properly chosen for Step.1. Calculation of MOSFET
input, bias & secondary windings keeping maximum drains to source voltage
in mind that it suits for the PCB design The voltage rating of the MOSFET is
(Layout). chosen by estimating the worst case
voltage it would see during its operation
Therefore after the PCB design only, the plus safety margin. This is done as
transformer pins are chosen so that it fits follows.
in to the PCB board properly.
N
Vds(MOSFET) > Vin(max) + N pri (Vout + VD ) + Vspike(est) (18)
sec
8
Vds(MOSFET) > 36 + (27 + 1.0) + 35
6
𝑉𝑑𝑠(𝑀𝑂𝑆𝐹𝐸𝑇) = 109𝑣𝑜𝑙𝑡𝑠
For an additional margin let’s use 200V rating MOSFET
Step.2. Calculation of MOSFET stand 3 times their average current rating

Maximum Drain to Source Current. in a non-repetitive situation. At minimum
It helps in selecting a MOSFET with an input voltage Vinmin, MOSFET on times
adequate current and also choosing will be 80% on a half period and since
primary wire size from corresponding rms there is one pulse for each half period, the
current. The current rating of MOSFET is duty cycle of the pulses will be 0.8 at V
dictated by FBSOA curve of the in(min).
MOSFET. Typical MOSFET can with
So a good consecutive current rating is

Ids › 1.5(Ian low-line) (19)
Assuming worst case efficiency of 70 %

Since Pout=100W
P 100
Pin = out = = 143watts (20)
η 0.7
Pin 143
Iavg(low−line) = V = = 7.95A ≅ 8Amps (21)
in(min) 18
IDS > 1.5(8) > 12Amps

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For additional margin let’s use greater than 20A rating MOSFET
The selected MOSFET was IRFP250A which has the following features.
Voltage rating= 27V (VCs)
Current rating=32A (ID)
Power rating =204W (Po)
RDS (on)=0.085Ω@VGS=10V
Low gate charge (typical 95nc)
Low Cress (typical75pf)
𝑑𝑣
Fast switching 100% avalanche tested, & improved 𝑑𝑡
Gate Drive Considerations of the metal-oxide gate structure, from gate to

MOSFET drain (CGD) &gate to source (CGS).Thus,
In order to turn a MOSFET on, a gate to the driving voltage source impedance
source voltage pulse is needed to deliver must be very low in order to achieve high
sufficient current to charge the input transistor speeds. Away of estimating the
capacitor in the desired time. The approximate driving generator impedance,
MOSFET input capacitance Ciss is the plus the required driving current is given
sum of the capacitance formed by the in the following equations
[𝑡𝑟 𝑜𝑟𝑡𝑓 ]
𝑅𝑔 = (22)
2.2𝐶𝑖𝑐𝑠
dv
Ig = Ciss dt
Where 𝑅𝑔 =generator impedance in ohms, 𝐶𝑖𝑠𝑠 = MOSFET input capacitance, in PF

dv
=generator voltage rate of change V/ns
dt
[240×10-9 ]
Rg = = 41.958 Ω
2.2×2600 ×10-12
×5.5
𝐼𝑔 =× 2600 × 10−12 30 𝑉 ⁄𝑛𝑠
𝐼𝑔 =0.0143uA
Design Consideration for Driving the frequencies. First minimize all lead
Power MOSFET lengths going to the MOSFET terminals,
There are basically two very simple especially the gate lead. If short leads are
design rules associated with MOSFET not possible, we may use a ferrite bead or
application which will prevent the switch a small resistor R1 in series with the
from oscillating when used in high MOSFET as shown in fig (1)
Fig. 1: Gate Drive ckt for MOSFET.

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Second because of the extremely high The resistor R2 in the circuit is used to
input impedance of the MOSFET, the assist transistor turn-off. The rise and fall
driving source impedance must be low in times of the MOSFET depend on the
order to avoid positive feedback which driving generator impedance. An
may lead to oscillations. approximation of the rise and fall times is
given by the following equation:
t r ort f = 2.2Cics R g (23) Where

𝑡𝑟 =MOSFET rise time in ns, 𝑡𝑓 = MOSFET fall time in ns,
𝑅𝑔 =generator impedance in ohms &𝐶𝑖𝑠𝑠 = MOSFET input capacitance in PF
Snubber Design for MOSFET

Step1: To find capacitance
CV2DS [ID VDS (tr +tf )]
E= = (24)
2 2
Where, 𝐼𝐷 =Drain current,𝑉𝐷𝑆 =Drain to source voltage,𝑡𝑟 =Rise time,𝑡𝑓 =Fall time.
Solving equation for capacitance C we get
I (t +tf )
C = [ D Vr ] (25)
DS
𝑉𝐷𝑆𝑚𝑎𝑥 =113
8(240 + 195)
=[ ] = 30nFor0.03µF
113
Step 2: To find discharge resistor

Assuming that the capacitor will be essentially discharged at the end of thrice the time
constants (T=RC), the following expression may be derived for maximum discharge resistors.
t
on 4.98×10−6
R = 3C = 3×0.03×10−6 = 55.3Ω (26)
With value calculated for R above, we must check the capacitor discharge current through the
switch at turn-on and restrict to about 0.25Ic using the following formula.
Discharge current
𝑉𝐷𝑆 113
𝐼𝑑𝑖𝑠 = =
𝑅 55.3
Idis =2.04 (27)
If the resistor is too low &𝐼𝑑𝑖𝑠 >0.25ID the R may be arbitrarily raised to fulfill the constraint
𝐶𝐸 𝑉
𝑅 = 0.25𝐼 (28)
𝐷
Step.3: to find drain current &drain to source voltage
For 𝐼𝐷(𝑚𝑎𝑥) = 12𝐴𝑚𝑝𝑠 &𝑉𝐷𝑆(𝑚𝑎𝑥) = 113𝑉

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Select an ultra-fast recovery power diode which has voltage rating of 200V &current rating of
20A.The selected diode was BYV-32-200(Philips)
Conclusion: Snubber capacitor C=30nF (y2-class)

Resistor R=56 Ω(2W)
Diode D=BYV-32-200(Philips)
Design of Drive Circuit

Step 4: To find charge current
The charge current Icharge is given
C ×V
Icharge = GSt GS (29)
r
CGS = Ciss − Crss = (2600 − 75)PF (30)
Ciss &Crss From the data sheet of MOSFET =2525PF
2525 × 10−12 × 10
Icharge =
240 × 10−9
Icharge = 0.105Amps
Where
CGS =gate to source capacitance PF,Ciss =input capacitance, PF, Crss =reverse transfer
capacitance, PF,VGS =gate to source voltage, V & t r =input pulse rise time, ns
Step5: To find discharge current

If we assure that the gate to drain capacitance dis-charges at the same time, then t r =t f and the
discharge current is given by
C ×V
Idischarge = rsst DS (31)
r
75 × 10−12 × 28
Idischarge = = 8.75mA
240 × 10−9
Crss =75PF (typical)
VDS =28V (typical)
Step 6: To calculate the power dissipation

In order to calculate the power dissipated in each of buffer transistors, the following is used:
P = VCE IC t r f (32)
P = 8 × 0.294 × 240 × 10−9 × 100 × 103
= 0.056 watts
Conclusion: The selected transistors for driving the MOSFETS are mps 2907(NPN) & mps
2222A (PNP)
Design of Output Rectifiers

Current rating:
For 27Voutput: Iout =1A
2I
IFM = 1−δout (33)
max
IFM = 3.6Iout (34)
IFM (27) = 3.6 × 1 = 3.6A

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For 15v output: [Iout = 3A]

IFM (15) = 3.6 × 3 = 10.8A
For 5voutput: [Iout = 2AIFM (15) = 3.6 × 2 = 7.2A
Voltage rating of diodes

The voltage rating of the rectifier should be greater than the total worst case voltage the diode
N
will see in its operation.VD > Vout + N s Vin(max) (35)
p
6
For 27v outputVD > 27 + 8 (36)
VD > 54volts.
3
For±15V output: VD > 15 + 8 (36)
VD >28.5 volts
For 5voutput
1
VD > 5 + (36)
8
VD > 9.5volts.
Conclusion:
For 27v output, choose a diode with voltage rating of 100V & current rating 2Amps
For 15v output, choose a diode with voltage rating of 50V & current rating 5Amps
For ±5V output, choose a diode with voltage rating of 50V & current rating 3Amps
Design of Output Power Inductor

Step 1: To calculate the required inductance
𝑉𝑜𝑢𝑡 ×𝑡𝑜𝑢𝑡
𝐿 = 0.25𝐼 (36)
𝑜𝑢𝑡
27 × 2.5 × 10−6
L= = 90uH
0.25 × 3
In order to keep low inductor peak current and good output ripple, it is recommended that I2
shall not exceed 0.25 Iout & Toff=2.5uSec.
Step2: Selection of core

2E
Ap = Aw Ac = K K JB (36)
W C m
Where
1 2
E = 2 LIm (37)
2
J=current density in A/mm
Take Bm=0.2TESLAfor ferrite core, J=3A/mm2, Kc=1 for square wave& Kw=0.6
Now
1
E = 2 × 90 × 10−6 × 9 =0.000405
2(0.000405)
Ap = Aw Ac = 0.6×1×3×106 ×0.2
Ap=2.25X10 -9m4=225252.525mm4
Now choose the core from appendix-I which has Ap higher than the value calculated above,
From the appendix-I the selected core is P 26/16

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The corresponding Ac=0.94×100mm2, Aw=0.53×100 mm2,

Ac=94mm2 and Ac=53mm2
Step3: Number of turns
The equation for number of turns is given by

LI
N = A Bm (38)
c m
90 × 10−6 × 3
N= ≅ 15turns
94 × 10−6 × 0.2
Step 4: Selection of wire gauge
The gauge of wire can be calculated form equation given below. Taking J=3A/mm2
A=I/J where I=Iout, A=3/3= 1mm2
Now choose the wire guage form to output capacitance C0And or

appendix-8 which has a cross section area integrating away the thin spike with a
greater than the value calculated above a small LC circuit.
swg19 is a proper choice
Choose 47uF/50V film or electrolytic or
Design of Output Filter Capacitor use tantalum capacitors in series to get the
Step 1: To find Output filter capacitor desired voltage rating and to get low
Output filter capacitor is chosen on the ripple voltage. Since these capacitors have
basis of specified output ripple. At very low ESR rating (high voltage rating
maximum output current during the capacitors are not available in tantalum
MOSEFET on time of 4.98usec.the filter type)
carries the corresponding secondary
current for 5.02 uSec.it slopes in voltages For 15 volts (allowing a ripple of 100mV)
an amount Output capacitor
I(T−ton ) 1(10−4.98)×10−6
V= (39) C0 = = 50.2uF
C0 100×10−3
Then
Iout(max) ×Toffmax For 5 volts (allowing a ripple of 50mV)
C0 = (40)
Vripple(max) Output capacitor
For 27 volts (allowing a ripple of 150mV) 1(10−4.98)×10−6

C0 = = 100.4uF
Output capacito 50×10−3
Use 220uF/20V tantalum capacitors.
1(10 − 4.98) × 10−6
C0 = = 33.467µF For 5 volts (allowing a ripple of 50mV)
150 × 10−3
Output capacitor Use 220uF/20V
Choose higher value than the calculated tantalum capacitors.
above sine RESR is inversely proportional

Volume 5 Issue 1
Conclusion:
In general output ripple is limited by the ESR of the capacitors and +the actual capacitance. If
low output ripple is required, an output filter may be a better choice than simply using large
output capacitor.
For 27 volts output C0 =33.467uF
For 15 volts output C0 =50.2uF
For ±5 volts output C0 =100.4uF
K. DESIGN OF OPTO COUPLER
Design step to calculate the current limiting resistor R

V −V 2.5−0.7
R = inI F = 0.926 = 1.942KΩ ------------ (41)
F
In figure (2) R3=R7=2𝐾Ω/2W
Design Step for selection of voltage divider

The voltage divider is selected as follows Vin into error amplifier is 2.5V selecting the branch
current of 0.926mA
R lower=2.5V/0.926mA=2.7K,R4=R5=2.7k/0.5W
Therefore Rl must be equal to 2.7 KΩ
Fig. 2: Regulation control, isolation circuit using optocoupler.
Design of Current Limit Circuit

Assuming converters efficiency of 75%
The estimated input power=output power (estimated)>efficiency=100/0.75=133 watts
Estimated input primary current=133/28V=4,76A
Limiting the primary current to 4Amps, we can load the output of converter upto85watts
thus the
VBE 0.7
R sc = = = 0.175Ω (42)
IP 4
Watt agerating=I2 R = 42 × 0.175Ω = 2.8 watts (43)
Use0.175/5w resistor
Selection of Optimum PWM Controller

Design Steps
UC3842 Implementation
Step 1: To find RT oscillator frequency

Volume 5 Issue 1
The first step in designing the oscillator components is to determine the required circuit dead
time .once obtained graphs on data sheets of PWM IC is used to pinpoint the nearest standard
value of Ct for the given dead time.
Calculate RT and CT from the graphs on the data sheet [at 100 KHz and at required dead
time] from graph at 2uS dead time, the value of CT=2.2nF
Next the approximate RT value is interpolated using parameters for CT and oscillator
frequency.
1.72
Fosc(KHZ) = [R (K)×C (uF)] (44)
T T
1.72
R T (K) = [ ] = 7.81
100 × 103 × 2.2 × 10−9
Step2: To find Start-up resistor
The value of start-up resistor should be

VDC(min)
R start−up =
5mA
18V
R start−up = = 3.6KΩ
5mA
VDC(max)
Formaximumcurrent =
3.6KΩ
VDC(max) 36
Formaximumcurrent = = = 10mA
3.6KΩ 3.6KΩ
wattage Rating = I2 × R = (10 × 10−3 )2 × 3.6 × 103 = 0.36 watt
Use Rstart-up=3.9K/1/2 w
Step 3: To find R sense for Pin no3

From the MOSFET data book, the current-sensing resistor for the current-sensing MOSFET
average current trip threshold 0.7V (Vsense)
[−Vsense ×RDM ]
R sense = [V --------------------- (45)
sense −IPK ×RDS(on) ]
[−0.7 × 288]
R sense = = 421
[0.7 − 13.87 × 0.085]
R DS(on) &R DM are from data sheet
Step 4: To find filter capacitance

A light filter is added to the current-sensing resistor to reduce the leading edge spike that
sometimes appears on the current waveforms. This spike causes erratic operation of the
current-mode controller.
Choose for 27VCo=470PF

For 15V Co= 33uf/35V (Tantalum capacitor)
For ±5𝑉 output Co= 220uF/20V (Tantalum capacitor)
SIMULATION AND TESTING OF FLY BACK CONVERTER

Volume 5 Issue 1
Specifications Used for Hardware Testing

Specification used for Simulation of continuous mode fly back dc-dc converter is as follows;
Input voltage : Vin min=18Volts & Vin max=36 volts
Nominal voltage : 28 volts
Output voltage& current: 27v@1A, 15V@ 3A & ±5V@2A
Pulse supply voltage : 16 V
Pulse width : 8uS
Period : 10usec
Primary inductance : 10uH
Output capacitors : Co=470PF for 27 volts
Co= 33uf/35V (Tantalum capacitor)
for 15 volts : Co= 220uF/20V (Tantalum capacitor) for±5𝑉
Testing of Fly Back Converter–Hardware Results

Line regulation
Vout(high) −Vout(low)
%Line Regulation = × 10 (46)
Vout(ideal)
Table1: Tabulation of Hardware Results for Line regulation

Vin +5 V -5V +15V 27V
Vin min=18 4.98 -4.98 14.99 26.9
Vin nom=28 4.98 -4.98 14.99 26.9
Vin max=36 5.04 -5.04 15.14 27.21
(i) For ±5v

Vout(high) − Vout(low)
%Line Regulation = × 100
Vout(ideal)
5.04−4.98
%Line Regulation = × 100 = 1.2%
5
(ii) For 15v

Vout(ideal)
15.14 − 14.99
%Line Regulation = × 100 = 1%
15
(iii) For 27V

Vout(ideal)
27.21 − 26.99
%Line Regulation = × 100 = 1.148%
27

Volume 5 Issue 1
Fig. 3: Testing circuit for full load and half load.
Load regulation: At the nominal input voltage of 28Vdc

Vout(high) −Vout(low)
%Load Regulation = × 100---------(47)
Vout(ideal)
Table 2: Load regulation tabulation

Iout +5 V -5V +15V 27V
At 50% of rated load current 5.03 -5.03 15.09 27.07
At 100% of rated load current 4.98 -4.98 14.99 26.9
(i) For 27v

27.07 − 26.90
%Load Regulation = × 100
27
% Load regulation = 0.63
(ii) For 15v

Vout(ideal)
15.09 − 14.99
15
%Load regulation = 0.67
(iii) For ±5𝑉

Vout(ideal)
5.03 − 4.98
5
%Load regulation = 1%
Table 4: Hardware result for efficiency calculation.

For 5volts ,2A@ nominal input voltage for full load
Vin Iin Vout Iout RL
28v 0.455 A 4.98v 1.95A 2.5
For15volts ,3A@ nominal input voltage for full load
28v 2.0.A 14.99 2.88 5
For27volts ,1A@ nominal input voltage for full load
28 1.2 26.90 0.98 27

Volume 5 Issue 1
Vout ×Iout
η=V (48)
in(nominal) ×Iin
(i) For 5v
4.98 × 1.95
η= x100 = 76.2%
28 × 0.455
(ii)For 15v
14.99 × 2.88
η= x100 = 77%
28 × 1.2
(iii)For 27v
26.90 × 0.98
η= x100 = 78.45%
28 × 1.2
SIMULATION TECHNIQUES  A Tool for Managers: Fast response

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manually to produce the best diode means forward drop losses.
product performance.

Volume 5 Issue 1
Switching Loss: Switching losses of a One reason for the fame of Pspice is the
diode means the sum of reverse recovery accessibility and the ability to share its
losses and reverse leakage current assessment adaptation openly at no
losses. expense. This assessment rendition is
extremely strong for power electronics
Fringing & Leakage Flux Loss: Losses simulations.
of a magnetic component divided into
three part, core losses means the total ac PSpice, presently created towards more
losses including the hysteresis and eddy mind boggling industry necessities, is
current losses. “Conduction losses” coordinated in the total systems
means the dc copper losses. Fringing & configuration stream from OrCAD and
leakage flux losses means the sum of all Cadence Allegro.
ac losses in the copper, e.g. ac losses
caused by skin and proximity effect, It also supports many additional
eddy current losses caused by fringing features, such as analysis with automatic
flux, etc. optimization of a circuit, encryption, a
Model Editor, support of parameterized
Waveform Analysis: Waveform analysis models, several internal solvers, auto-
typically plots voltage and current of convergence and checkpoint restart,
important components at a specific magnetic part editor and Tabrizi core
operating condition model for non-linear cores.
PowerEsim is simulation software Comparisons between powerEsim and

specifically designed for Simulation of Pspice
switch mode power supplies. With fast  PSpice permits the client to choose
simulation and friendly user interface, explicit parts with industry standard
PowerEsim provides a powerful part numbers and determinations.
simulation environment for SMPS of 48 Searching for these components can
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and design tools for research and  PSpice is a significantly more
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and power conversion and control  The setting of the recreation
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do to keep away from numerical
Pspice Student Version 9.2 convergence issues
SPICE is an abbreviation for Simulation  PSpice does not allow data
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electrical and electronic recreation. The simulation. It is like having a virtual
expanded usage of PCs has prompted test bench running on your
the creation of PSPICE, a generally computer.
accessible PC form disseminated by the  We can design and simulate switch
MicroSim Corporation. mode power supplies using
PowerEsim’s Digital Control

Volume 5 Issue 1
Module. The digital control can be  The components used for fabrication
implemented in either block diagram purpose were not available in the
or custom C code. EDA software library.
 PowerEsim has a built-in C  The different types of simulations
compiler which allows you to enter were required for the comprehensive
your own C code into PowerEsim analysis of proposed technology.
without compiling. This makes it  As the actual circuit poses driving
very easy and flexible to implement circuit problem for multiple outputs.
your own function or control The combined simulation analysis
methods. was not possible.
 We can use the Thermal Module to  The conventional EDA freeware
calculate semiconductor device software was not flexible to use it for
losses (conduction losses and multiple output analysis. For
switching losses) based on the instance, in loop analysis various
device information from compensation techniques are not
manufacturers' datasheet. available. Only there is a limited
scope for temperature based analysis
SELECTION OF CIRCUIT in conventional
STRUCTURE  Hence the proposed project was
The schematic arrangement shown in fig analyzed with the help of
(4.2) has been choosen for simulation POWERESIM software, which has
purpose is emphasized with the reasons been developed exclusively for
highlighted as given below. SMPS analysis.
 The actual circuit is fabricated for an
ac input, but the design requirement
allows us to use dc input directly.
Circuit Diagram Used For Simulation

Volume 5 Issue 1
Fig. 4: Circuit diagram of fly back converter for multiple outputs.
COMPARISON OF SIMULATION PWM based Primary side controller

AND EXPERIMENTAL RESULTS operating at 90 kHz to obtain four output
The proposed dc-dc converter of fig (4) is voltages. The ‘±5V’, ‘15V’and 27v output
studied by using “POWERESIM” can supply a maximum load current of
simulation tool. Analysis of the circuit 2A, 3A and 1A respectively. Table 4
shown in fig (4) with each component loss shows the efficiency measurement with
is tabulated shown in appendix-2.A schottky diodes as output rectifier diodes.
prototype of the proposed flyback The average active mode efficiency of the
converter as shown in fig (5) has been converter is77.2167% at 28v dc input.
built for the aircraft applications. The
prototype has the different circuit The experimental wave forms of the
parameters as compared with the output voltage ripples, frequency response
simulation circuit. The converter (Bode plot), output voltage, field
efficiency at full load is more or less 78% response, duty cycle, output current,
as shown in table (4).The hardware values switching waveforms and Transient
tabulated in appendix-2 gives the same waveforms at respective full load currents
efficiency. Laboratory evaluation is are shown in figs (6to 21). They have
conducted on a Flyback converter to good agreement with the expected results.
assess the performance benefits of The fly back operation of the proposed
Synchronous Rectification using schottky converter is proved under all load
diodes. The converter is built around a conditions.

Volume 5 Issue 1
C7 R10
1n 1k coil
D2
FUSE/SM D5 C1
11kv
R3 100uf/35v
C3 D3 R11 C10
3
100E/2w C16 10uf/63v o/p
1kpf 100uf/400v C8 2k D5
-
C4
mov 4 2 220pf/1kv
I/p
D5 C17
+
1n
47k
1
R1
47k
C2 1kv
1kpf
R2
1kv
PI48
R5 M1
TOP3
22E or
TO220
R7
100k
R4
R6 3W
1k
D4
R8 D5
1k R9
330PF/35V C15 1k L1
C14 10uf/63v C5
1n
R18
C21
10k
UC3842 102
D12 C22
I mode PWM IC BA157 R13
1n
8 1 C19 1k
Vref Comp
7 2 104 C9
VCC VFB 104 4 1
3
6 Isense PC817
GATE
4 3 2
C23 5 GND RTCT
104
C20 102
R17
27k R14
2k
R16
20k
D13 C12
LM135A/TO 1uf/63v
C26
1pf/1kv
R15 R12
2k 2k
Fig. 5: Fabricated circuit.
Working of the Circuit power switch is varied on a cycle by cycle

Input of 18to 36 v is obtained from bridge basis. This compensates for changes in the
rectifier connected to AC input of 180 to input supply and output load. The output
240 volts from the distribution system of voltage is compared to an accurate
aircraft. This input is fed to the high reference supply, and the error voltage
frequency ferrite core transformer, which produced by the comparator is used by
is operated by high frequency MOSFET dedicated control logic to terminate the
(IRF540) switch in the range of 90 to 100 drive pulse to the main power switch
KHZ. The switching action is controlled (MOSFET) at the correct instance.
by PWM current mode controller Correctly designed S.M.P.S will provide a
(UC3842). The output is extracted from very stable dc output supply. It is essential
the output filter section consisting of that delays in the control loop are kept to
output choke and capacitors. The outputs a minimum, otherwise stability problems
and the input is isolated by using the would occur. Hence, very high speed
optocoupler (PC817).Regulation of the components must be selected for the loop.
output to provide a stabilized dc supply’s In transformer-coupled supplies, in order
carried out by the control or feedback to keep the isolation barrier intact, some
block as shown in fig (4.3).The proposed type of electronic isolation is required in
S.M.P.S is operated on a fixed frequency the feedback. This is usually achieved by
pulse width modulation basis, where the using an opto-isolator.
duration of the ON time of the drive to the
Waveform - Fly Back DC-DC Converter

Volume 5 Issue 1
Fig. 6: Ch1-M1 drain source voltage waveformCh2-M1 drain current waveform Time Base-4
us/Div [Ta=25 Deg,.Vo1=12.63 V; Vo2=3.875 V; Vo3=23.41 V; Vin=18 V Io1=3 A; Io2=2 A;
Io3=1 A;].
Here is a typical plot of a Flyback condition. The prototype testing photos

converter circuit with component M1. In are enclosed as evidence of test bench
the dual traces channel 1 (CH1) and setup as an integral part of test facilities
channel 2 (CH2). Vertical resolutions are available at NAL. The readings obtained
quoted inside the square brackets while for ±5V, 15V and 27V with input voltages
the horizontal resolution resides on the 18V, 28V (nominal) and 36 volts are
bottom right. tabulated and used to compute the line
regulation.
Fig.6 depicts Primary MOSFET switching
waveform @ peak bulk voltage on the The results so obtained are well agreed
‘Control’ MOSFET as the circuit with design specification considered in
traverses from Continuous Conduction chapter 2. Similarly it has been extended
(CCM) into Discontinuous Conduction to test the project on the same test bench
(DCM) Mode operation with decreasing for dynamic condition. While doing so,
loads. different load conditions have been set to
match on-line load conditions as
When the MOSFET current was high to applicable to different stages of aircraft
obtain a low resistance at 100% loading. operation.
The gate enhancement then eases off
gradually, as the Drain current through the With this set up the readings are tabulated
MOSFET decreases, ensuring a quick to compute load regulation .The result
turn-on of the MOSFET. At turn off, the obtained has been compared with design
Drain-Source voltage across the ‘Control’ specification and found that load
MOSFET to drop the turn-off threshold regulation is met by a proposed project as
drives the gate off. As the secondary a major requirement of control system in
winding current fall time is limited by the on- line applications.
winding leakage inductance (Fig 4.4), the
controller drives off the ‘Control’ Output Voltage Ripples
MOSFET safely. The negative feedback In the steady-state operation, the proposed
mechanism helps to prevent the converter generated the output voltage
MOSFETs from being turned off pre- ripples about 20mv, 5mv and 10mv for
maturely. the outputs Vo1=15 V; Vo2=5V; &
Vo3=27V; respectively @ Vin=18 V; &
The line regulation has been calculated 100% load as shown in figures (7), (8)
using the table 2 for steady state and (9).

Volume 5 Issue 1
The ripple of prototype is shown in photographic view which is enclosed in appendix part.
Fig. 7:Ch1-O/P 1 ripple voltage waveform Time Base-4 us/Div.
Fig. 8:Ch1-O/P 2 ripple voltage waveform Time Base-4.
Fig. 9:Ch1-O/P 3 ripple Voltage waveform Time Base-4 us/Div.
Loop Analysis points of expected gain or expected

Fig10.The Bode Plot Of The Proposed phase, by pressing “Automatic
System. Loop analysis is a tool to let Compensation” button, the coefficient of
user arbitrary draw a transfer function by the transfer function or components will
vary the coefficient or component from be changed to fit those points. Loop
the feedback block. On the other way, Analysis with power supply initialized -
curve fitting can be done by entering Generic transfer function analyser
The Loop Analysis provides the interface The Bode plot of the proposed system is
to customize the transfer function and plotted and the results are depicted as
shows the gain and phase of the transfer shown in figure (10).The point of
function G(s) intersection of 0dB line with magnitude
plot is called as gain cross over point

Volume 5 Issue 1
which is projected to meet frequency axis gives the phase cross over frequency. In
referred as gain cross over frequency. The the proposed plot the phase crossover
gain cross over frequency of the proposed frequency is 68.72 kHz .The line
converter is 8174.5 Hz. The intersecting projected vertically upwards to meet the
point of -180 degree line to phase plot gain plot at some point say X.
Fig. 10: Gain Cross-over Freq=8174.54 Hz Gain Margin=40 dB, Phase cross over
frequency=68.72 kHz Phase Margin=60.05 Deg.
The difference in gain measured in dB phase margin are positive then the system
between X and 0dB line is taken as gain is said to be stable. If any one of them is
margin .In the proposed plot the gain negative (either gain margin or phase
margin is 40dB.The line projected margin), the system is said to be unstable.
vertically downwards to meet the phase In contrast of the aforesaid conditions the
plot at some point say Y, the difference in proposed system depicts the second
phase between the point Y and the 0 dB condition hence the system is stable. In
line is treated as phase margin in the the due course of the stability analysis
proposed plot it is found as 60degrees.The exercise, the system stability was found
conditions of bode plot says that If gain marginally stable but later it was
cross over frequency is equal to phase compensated in terms of gain to obtain
cross frequency then the system is said to stable system.
be marginally stable. If gain margin and
Power Dissipation
Fig. 11: Power dissipation versus input voltage.
The plot of power dissipation versus input obvious from the plot that there is more
voltage shown in figure (11) reveals that power dissipation at lesser input voltage
as the input voltage varies the dissipation and less dissipation at greater voltage. It is
will linearly descend about 1 watt. It is the fact that, initially greater power is

Volume 5 Issue 1
required to accelerate the devices to steady state condition.
Efficiency (η)
Fig. 12: Efficiency V/S Input Voltage.
The plot of efficiency (η) versus input voltage increases more steadily indicating
voltage shown in figure (12) depicts the improved efficiency. It is true that the
information of closed loop performance converter draws more power to accelerate
under different load conditions. The it from initial stage. It is concluded from
efficiency increases steadily as a mirror above discussion that the converter
image of dissipation curve such that becomes more efficient at higher input
initially converter operates at lesser voltages as it does not require more power
efficiency say 84%. Later as the input to maintain in steady state condition.
Magnetic Field Analysis
Fig. 13: Flux density v/s input voltage.
The plot of flux density (B) in tesla versus the step (8) of design procedure that the
input voltage shown in figure (13) reveals selection of core is made to maintain the
that, once the field is established by field constant and more susceptible. Thus
minimum input supply voltage will the field is constant for change in input
remain undisturbed throughout the twice that of the specified input.
operating conditions .It is evident from
Frequency versus input voltage
Fig. 14: Switching frequency versus Input voltage.

Volume 5 Issue 1
The plot of frequency versus input voltage evident from step (5) in the design
shown in figure (14) leads to the procedure that ferrite core meant for high
following citation. The switching frequency applications exhibit the
frequency remain constant even the input property of greater tolerance in core
voltage varies between Vccmin and Vccmax saturation which is most suitable for
set in the design consideration. It is SMPS .
Duty cycle versus input voltage
Fig. 15: Duty cycle versus Input voltage.
To emphasize the role of duty cycle for worst case and proportionately decreases
wide variation in input voltage from 18 for greater input voltages to set the output
volts to 36 volts, the simulation has been completely regulated .Step no (4) in
performed and the plot is shown vide design procedure support the above
figure (15).The proposed converter illustration.
requires duty cycle around 70% under
Fig. 16: (a) Simulation for input harmonic.
Simulation for input harmonic analysis Total Harmonic Distortion is found to be

has been carried out and the result is 0(%).The load harmonics were not traced
tabulated as cited below .The as it requires nonlinear simulation tool
corresponding plot is shown in figure, 16 which is still under construction.
(a)
Simulated harmonic

Volume 5 Issue 1
Fig. 16: (b).Input Harmonic Vrms=18 (V), Ii-rms=4.56 (A),I-peak=4.56(A), Crest Factor=1,
I-fund=0.013(A), VA=82.08 (W), Input Power=82.08 (W) Power Factor=1 & THD=0(%)
Load Analysis load current is due to the switching action

Loading waveform of figure (17) depicts of MOSFET as the circuit traverses from
that @ normal temperature with multiple Continuous Conduction (CCM) into
outputs configuration the step loading at Discontinuous Conduction (DCM) Mode
different time intervals occur between t0 operation with decreasing loads. When
& t7. @t1=116.8uS load draws 3A rated the MOSFET current was high to obtain a
value but @t1=233.6uS the current low resistance at 100% loading. The
substantially reduces to 0.3A represents Drain current through the MOSFET
almost off state it will remain in the same decreases, ensuring a quick turn-on of
state to t2 .Later @ time t2 current sharply primary MOSFET.
raises to the steady state value .the dip in
Vo1 for Analysis Transient Simple Forward DC-DC Ta=25 Deg.Vo1=15 V; Vo2=5.097 V;
Vo3=27.2 V; Vin=18 VIo1=3 A; Io2=2 A; Io3=1 A; Period=0.001s Step
loadingt0=116.8usI0=3 At1=233.6usI1=0.3 At2=584.1usI2=0.3 At3=595.8usI3=3
At4=788.6usI4=3 At5=876.2usI5=3 At6=963.8usIFig4.15. Loading wave form
Output Current & Voltage Transient
Fig. 17: load characteristics.

At turn off, the current rise in primary winding current fall time is limited by the
MOSFET forces the Drain-Source voltage winding leakage inductance (see Fig18),
across the ‘Control’ MOSFET to drop the controller drives off the ‘Control’
down to the turn-off threshold value MOSFET safely and minimizes the
drives the gate off. As the secondary possibility of damage.

Volume 5 Issue 1
Fig. 18: Transient O/P Waveform Ch1 - Output Loading Current 1 A/DivCh2 - Output ac
Transient Voltage - 100 V/Div, Time Base - 400 us/Div.
Voltage Regulation Analysis initially up to nominal voltage it will raise

Fig.18.depicts the information of response gradually later maintains constant It is due
of output voltage with respect to input the greater resistance offered by
voltage at temperature 40 deg.it is obvious conductive path .
from the plot that voltage drop is more
Fig. 19: Output voltage v/s input voltage.
Prototype of Flyback DC-DC Converter
Fig. 20: Four output prototype of flyback converter.
CONCLUSIONS designed and developed for multiple

In this paper, DC-DC converter of outputs. At rated load this converter
flyback converter topology has been possess the efficiency almost equal to

Volume 5 Issue 1
the bench mark set by military Springer Science & Business

standards. Media.
3. Metev, S. M., & Veiko, V. P.
Tight regulation of both voltage and (2013). Laser-assisted
current as well with least transient microtechnology (Vol. 19). Springer
effect. PWM current control scheme is Science & Business Media.
proved to be more effective than voltage 4. Baranovski, A. L., Mogel, A.,
mode feedback control scheme. Schwarz, W., & Woywode, O.
Optoisolator provides good electrical (2000, May). Chaotic control of a
isolation between input and output DC-DC-converter. In 2000 IEEE
prevent harmonics gives very high International Symposium on
reliability. Therefore this Fig10source of Circuits and Systems (ISCAS) (Vol.
power found suitable for aircrafts 2, pp. 108-111). IEEE.
5. Clementi, S., Pelly, B. R., & Isidori,
A. (1981, October). Understanding
REFERENCES power MOSFET switching
1. Kumar, P. S. (2016, February). performance. In Proc. IAS (pp. 763-
Design of high frequency power 776).
transformer for switched mode
power supplies. In 2016 Cite as
International Conference on K. Umesha. (2022). Design and
Emerging Trends in Engineering, Development of Compact DC-DC
Technology and Science (ICETETS) Converter Unit from Air Craft.
(pp. 1-5). IEEE. Advancement of Signal Processing and
2. Baliga, B. J. (2010). Fundamentals Its Applications, 5(1), 1–29.
of power semiconductor devices. https://doi.org/10.5281/zenodo.6656062

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Advancement of Signal Processing and its Applications

Design and Development of Compact DC-DC Converter Unit

Keywords: SMPS, PWM, regulation, flyback, Isolation, duty ratio, actuators

INTRODUCTION (FAA) and military norms, and are lenient

HBRP Publication Page 1-29 2022. All Rights Reserved Page 1

DESIGN OF FLY BACK CONVERTER

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P02 = ∑ki=1 Voi

𝑉𝑜𝑖′ = 𝑉𝑜𝑖 + 𝑉𝐷 (2)

VD =Diode drop in ith secondary winding

Step 2: To find the transformer peak primary current

The input voltage may be written as

Then above eqn becomes

Where Vin =dc output voltage in volts

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f=Switching frequency in KHz

Dividing eqn (2.14) by eqn (2.13) we get

Pout Lp I2pp fDmax

The transformer peak primary current is given by

Step 3: To find the primary inductance

(Worst case f=90 kHz)

This calculation is performed at the is recommended that a small amount of

Step4: To find minimum and maximum duty cycles

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Dmin = 0.538 & Dmax=0.7 (worst case assumed)

Step5: Selection of Core

1 4x0.7 4(1 − 0.7)

Now the estimated air gap should be calculated by

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Step 7: Turns Ratio for Each Winding

Step 8: Calculation of primary number of turns

At this point, it is always advisable to Step 9: Calculation of Secondary Number

So the number of secondary turns can be obtained by

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The secondary turns can also be found by the following steps

Now actual secondary of turns is given by

Step 10: Wire Gauge Selection

Then 400Cm/AX15.87A=6348C.m (Circular mills)

An is the circular mil area for the AWG size n =12

For secondary winding

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Conclusion from Transformer Design

Note: EE 42/15 bobbin contains total Design of Power MOSFET

For an additional margin let’s use 200V rating MOSFET

Step.2. Calculation of MOSFET stand 3 times their average current rating

So a good consecutive current rating is

Assuming worst case efficiency of 70 %

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Gate Drive Considerations of the metal-oxide gate structure, from gate to

Where 𝑅𝑔 =generator impedance in ohms, 𝐶𝑖𝑠𝑠 = MOSFET input capacitance, in PF

Fig. 1: Gate Drive ckt for MOSFET.

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t r ort f = 2.2Cics R g (23) Where

Snubber Design for MOSFET

Step 2: To find discharge resistor

Idis =2.04 (27)

Step.3: to find drain current &drain to source voltage

For 𝐼𝐷(𝑚𝑎𝑥) = 12𝐴𝑚𝑝𝑠 &𝑉𝐷𝑆(𝑚𝑎𝑥) = 113𝑉

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