● What is CMOS Technology?

● Why NMOS technology is preferred more than PMOS technology?

● What are the steps involved in manufacturing of IC?

● What are the processes involved in photo lithography?

● What are the steps involved in twin-tub process?

● What is Latch – up?

● What are the other alternative software apart from xillinx used for VLSI design?

● What is RTL ?

● What happens when the PMOS and NMOS are interchanged with one another in an inverter?

● What’s the difference between Testing & Verification?

● Explain why present VLSI circuits use MOSFETs instead of BJTs?

● VHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn, stands for “Very
High Speed Integrated Circuit,” which was a U.S. Department of Defense program.
● Which Is The Default Delay In Vhdl?
A5: delta delay.
● List Out The Objects Of Vhdl?
A7: Signal, Variable, Constant.

● What can be the various uses of VHDL ?

A11: The VHDL language can be used for several goals like –

● i) To synthesize digital circuits

ii) To verify and validate digital designs
iii) To generate test vectors to test circuits
iv) To simulate circuits

● What is the difference between Concurrent & Sequential Statements ?

A13: Concurrent statements define interconnected processes and blocks that together describe a
design’s overall behavior or structure. They can be grouped using block statement. Groups of
blocks can also be partitioned into other blocks. At the same level, a VHDL component can be
connected to define signals within the blocks It is a reference to an entity A process can be a
single signal assignment statement or a series of sequential statements (SS) Within a process,
procedures and functions can partition the sequential statements
 ● The structural code for 4-bit adder is given below.

● COMPONENT adder IS

● GENERIC (n : INTEGER := 3);

● PORT(input : IN BIT_VECTOR(n DOWNTO 0);

● output : OUT BIT_VECTOR(n DOWNTO 0));

● END COMPONENT;

● If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a)n
b)input
c)output
d) component
●

What Do We Need To Generate Hardware From Vhdl Model?

A9: We need following tools

● Simulation tool.

● Synthesis tool.

● Implementation tool.

● Tell me some of constraints you used and their purpose during your design?

There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx constraints
a) Translate on and Translate off: the Verilog code between Translate on and Translate off is
ignored for synthesis.
b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through
combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify
what input pin or internal net is the real clock signal. This constraint allows you to define the
clock net.
c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be
collapsed into a single XOR.
For more constraints detailed description refer to constraint guide.
●
Suppose for a piece of code equivalent gate count is 600 and for another code equivalent
gate count is 50,000 will the size of bitmap change?in other words will size of bitmap change
it gate count change?
The size of bitmap is irrespective of resource utilization, it is always the same,for Spartan
xc3s5000 it is 1.56MB and will never change.

What are different types of FPGA programming modes?what are you currently using ?how
to change from one to another?

Before powering on the FPGA, configuration data is stored externally in a PROM or some other
nonvolatile medium either on or off the board. After applying power, the configuration data is
written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes
Mode selecting pins can be set to select the mode, refer data sheet for further details.

Tell me some of features of FPGA you are currently using?

I am taking example of xc3s5000 to answering the question .

Very low cost, high-performance logic solution for

high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 6 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
• Eight global clock lines and abundant routing

Can you list out some of synthesizable and non synthesizable constructs?

not synthesizable->>>>
initial
ignored for synthesis.
delays
ignored for synthesis.
events
not supported.
real
Real data type not supported.
time
Time data type not supported.
force and release
Force and release of data types not supported.
fork join
Use nonblocking assignments to get same effect.
user defined primitives
Only gate level primitives are supported.

synthesizable constructs->>
assign,for loop,Gate Level Primitives,repeat with constant value...

Difference between FPGA and CPLD?

FPGA:
a)SRAM based technology.
b)Segmented connection between elements.
c)Usually used for complex logic circuits.
d)Must be reprogrammed once the power is off.
e)Costly

CPLD:
a)Flash or EPROM based technology.
b)Continuous connection between elements.
c)Usually used for simpler or moderately complex logic circuits.
d)Need not be reprogrammed once the power is off.
e)Cheaper

What are dcm's?why they are used?

Digital clock manager (DCM) is a fully digital control system that

uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in operating
temperature and voltage.
That is clock output of DCM is stable over wide range of temperature and voltage , and also skew
associated with DCM is minimal and all phases of input clock can be obtained . The output of
DCM coming form global buffer can handle more load.
what is slice,clb,lut?

I am taking example of xc3s500 to answer this question

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing
synchronous as well as combinatorial circuits.
CLB are configurable logic blocks and can be configured to combo,ram or rom depending on
coding style
CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-
LUT.

Can a clb configured as ram?

YES.

The memory assignment is a clocked behavioral assignment, Reads from the memory are
asynchronous, And all the address lines are shared by the read and write statements.

What is purpose of a constraint file what is its extension?

The UCF file is an ASCII file specifying constraints on the logical design. You create this file
and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints
Editor to create constraints within a UCF(extention) file. These constraints affect how the logical
design is implemented in the target device. You can use the file to override constraints specified
during design entry.

How many global buffers are there in your current fpga,what is their significance?

There are 8 of them in xc3s5000

An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which
directly accesses the global clock network or an Input Buffer (IBUF). Clock signals within the
FPGA drive a global clock net using a Global Clock Multiplexer Buffer (BUFGMUX). The
global clock net connects directly to the CLKIN input.

Why is map-timing option used?

Timing-driven packing and placement is recommended to improve design performance, timing,

and packing for highly utilized designs.

What are different types of timing verifications?

Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between different timing domains.

Suggest some ways to increase clock frequency?

· Check critical path and optimize it.

· Add more timing constraints (over constrain).
· pipeline the architecture to the max possible extent keeping in mind latency req's.

What is DFT ?

DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a
design works properly after manufacturing, which later facilitates the failure analysis and false
product/piece detection
Other than the functional logic,you need to add some DFT logic in your design.This will help you
in testing the chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ
testing etc are all part of this. (this is a hot field and with lots of opportunities)

There are two major FPGA companies: Xilinx and Altera. Xilinx tends to promote its hard
processor cores and Altera tends to promote its soft processor cores. What is the difference
between a hard processor core and a soft processor core?

A hard processor core is a pre-designed block that is embedded onto the device. In the Xilinx
Virtex II-Pro, some of the logic blocks have been removed, and the space that was used for these
logic blocks is used to implement a processor. The Altera Nios, on the other hand, is a design that
can be compiled to the normal FPGA logic.

The contamination delay of the data path in a sequential circuit is critical for the hold time at the
flip flop where it is exiting, in this case R2.
mathematically, th(R2) <= tcd(R1) + tcd(CL2)
Contamination delay is also called tmin and Propagation delay is also called tmax in many data
sheets.

When are DFT and Formal verification used?

DFT:
 · manufacturing defects like stuck at "0" or "1".
· test for set of rules followed during the initial design stage.

Formal verification:
· Verification of the operation of the design, i.e, to see if the design follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.

What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your Verilog code
into gates - and that's putting it very simply! First of all, the Verilog must be written in a
particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't
actually produce gates - it will output a netlist of the design that you have synthesised that
represents the chip which can be fabricated through an ASIC or FPGA vendor.

● The structural code for 4-bit adder is given

below.
● COMPONENT adder IS

● GENERIC (n : INTEGER := 3);

● PORT(input : IN BIT_VECTOR(n
DOWNTO 0);
 ● output : OUT BIT_VECTOR(n DOWNTO
0));
● END COMPONENT;
These are very Basic VHDL Interview Questions and Answers for freshers and experienced both.

Q1: What Is Vhdl?

A1: VHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn, stands for “Very
High Speed Integrated Circuit,” which was a U.S. Department of Defense program.

Q2: What Are Generics?

A2: Generics are a way to provide static information to the VHDL program. Immediately after
writing entity name, we will mention the generics, this generics will provide the data for entire
program. Generics basically allow a design entity to be described so that,for each use of that
component,its structure and behavior can be changed by generic values.In general they are
used to construct parameterized hardware components.Generics can be of any type.but mostly
we will give the timing details there.

E.g. :- generic ( width : integer := 7 );

Generic is a great asset when you use your design at many places with slight change in the
register sizes,input sizes etc. But if the design is very unique then,you need not have generic
parameters. Also, Generic’s are synthesizable.

Q3: Are Verilog/vhdl Concurrent Or Sequential Language In Nature?

A3: Verilog and VHDL both are concurrent languages. Any hardware descriptive language is
concurrent in nature.

Q4: What Is A D-latch?

A4: D latch is a device it simply transfers data from input to output when the enable is
activated.its used for the forming of d flip flops.

Q5: Which Is The Default Delay In Vhdl?

A5: delta delay.

Q6: What Is An Alias And Write Its Syntax?

A6: Alias is an alternative name assigned to part of an object. alias alias_name : subtype isname

Q7: List Out The Objects Of Vhdl?

A7: Signal, Variable, Constant.
Q8: List Out The Levels Of Abstractions In Vhdl?
A8: Data flow level, Structural Level, Behavioral Level.

Q9: What Do We Need To Generate Hardware From Vhdl Model?

A9: We need following tools

● Simulation tool.
● Synthesis tool.
● Implementation tool.

Q10: How The Signal Acts Within A Process And Outside The Process?
A10: Signal assignment is concurrent outside the process and sequential within a process.

Q11: What can be the various uses of VHDL ?

A11: The VHDL language can be used for several goals like –

i) To synthesize digital circuits

ii) To verify and validate digital designs
iii) To generate test vectors to test circuits
iv) To simulate circuits

Q12: What is Synthesis?

A12: Synthesis represents the transformation of an abstract description into a more detailed
descrition. In general, the term “synthesis” is used for the automated transformation of RT level
descriptions into gate level representations. This transformation is mainly influenced by the set
of basic cells that is available in the target technology. While simple operations like
comparisons and either/or decisions are easily mapped to boolean functions, more complex
constructs like mathematical operators are mapped to a tool specific macro cell library first.
This means that a number of adder, multiplier, etc. architectures are known to the synthesis
tool and these designs are treated as if they were designed by the user.

Q13: What is the difference between Concurrent & Sequential Statements ?

A13: Concurrent statements define interconnected processes and blocks that together describe
a design’s overall behavior or structure. They can be grouped using block statement. Groups of
blocks can also be partitioned into other blocks. At the same level, a VHDL component can be
connected to define signals within the blocks It is a reference to an entity A process can be a
single signal assignment statement or a series of sequential statements (SS) Within a process,
procedures and functions can partition the sequential statements

Q14: What are VHDL Subtypes ?

A14: VHDL subtypes are used to constrain defined types. Constraints take the form of range
constraints or index constraints. However, a subtype may include the entire range of the base
type. Assignments made to objects that are out of the subtype range generate an error at run
time. The syntax and an example of a subtype declaration is shown below :-

SUBTYPE First_ten IS INTEGER RANGE 0 to 9;

Q15: Mention what is the difference between the TTL chips and CMOS chips?
A15:

TTL Chips CMOS Chips

● CMOS stands for Complementary

● TTL chips for transistor transistor Metal Oxide Semi-conductor. It is
logic. It uses two Bi-polar Junction also an integrated chip but used field
Transistors in the design of each logic effect transistors in the design
gate ● CMOS has greater density for logic
● TTL chips can consist of a substantial gates. In a CMOS chip, single logic
number of parts like resistors gate can comprise of as little as two
● TTLS chip consumes lot more power FETs
especially at rest. A single gate in TTL ● CMOS chips consume less power. A
chip consumes about mW of power single CMOS chip consume about
● TTL chips can be used in computers 10nW of power
● CMOS chip is used in Mobile phones

Q16: Explain what is a sequential circuit?

A16: A sequential circuit is a circuit which is created by logic gates such that the required logic
at the output depends not only on the current input logic conditions, but also on the sequences
past inputs and outputs.

Q17: In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

A17: In Verilog code, the unit of time is 1 ns and the accuracy/precision will be upto 1ps.

Q18: Explain what is the depletion region?

A18: When positive voltage is transmitted across Gate, it causes the free holes (positive charge)
to be pushed back or repelled from the region of the substrate under the Gate. When these
holes are pushed down the substrate, they leave behind a carrier depletion region.

Q19: Explain what is the use of defpararm?

A19: With the keyword defparam, parameter values can be configured in any module instance
in the design.

Q20: Explain what is multiplexer?

A20: A multiplexer is a combination circuit which selects one of the many input signals and
direct to the only output.
VHDL Conclusion Interview FAQs

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