Am335x Pru
Am335x Pru
Am335x Pru
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4.1 Introduction
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs), shared, data, and
instruction memories, internal peripheral modules, and an interrupt controller (INTC). The programmable
nature of the PRU, along with its access to pins, events and all SoC resources, provides flexibility in
implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces,
and in offloading tasks from the other processor cores of the system-on-chip (SoC).
Figure 4-1 shows the PRU-ICSS details.
The PRUs have access to all resources on the SoC through the Interface/OCP Master port, and the
external host processors can access the PRU-ICSS resources through the Interface/OCP Slave port. The
32-bit interconnect bus connects the various internal and external masters to the resources inside the
PRU-ICSS. The INTC handles system input events and posts events back to the device-level host CPU.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level
host CPU. This interaction between processors is determined by the nature of the firmware loaded into the
PRU’s instruction memories.
PRU-ICSS
Data Mem0
PRU0 Core (8KB)
(8KB Program)
Data Mem1
EGP IO MAC (8KB)
32-Bit Interconnect Bus
IEP
INTC UART0
CFG
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4.1.1 Features
The PRU-ICSS includes the following main features:
• Two PRUs each with:
– 8KB program memory
– 8KB data memory
– High Performance Interface/OCP Master port for accessing external memories
– Enhanced GPIO (EGPIO) with async capture and serial support
– Multiplier with optional accumulation (MPY/MAC)
• One scratch pad (SPAD) memory
– 3 Banks of 30 32-bit registers
• Broadside direct connect between PRU cores within subsystem
• 12 KB general purpose shared memory
• One Interrupt Controller (INTC)
– Up to 64 input events supported
– Interrupt mapping to 10 interrupt channels
– 10 Host interrupts (2 to PRU0 and PRU1, 8 output to chip level)
– Each system event can be enabled and disabled
– Each host event can be enabled and disabled
– Hardware prioritization of events
• 16 software events generated by 2 PRUs
• One Ethernet MII_RT module with two MII ports and configurable connections to PRUs*
• One MDIO Port*
• One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
– One Industrial Ethernet timer with 10 capture* and eight compare events
– Two Industrial Ethernet sync signals*
– Two Industrial Ethernet 16-bit watchdog timers*
– Industrial Ethernet digital IOs
• One 16550-compatible UART with a dedicated 192-MHz clock, supporting up to 12Mbaud for
PROFIBUS DP
• One Enhanced Capture Module (ECAP)
• Flexible power management support
• Integrated 32-bit interconnect bus for connecting the various internal and external masters to the
resources inside the PRU-ICSS
• Interface/OCP Slave port for external masters to access PRU-ICSS memories
• Optional address translation for PRU transaction to External Host
• All memories within the PRU-ICSS support parity
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4.2 Integration
The device includes a Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem (PRU-ICSS) consisting of two independent Programmable Real-time Units (PRUs). Each PRU
is a 32-bit Load/Store RISC processor with dedicated memories. The PRU-ICSS integration is shown in
Figure 4-2.
pr1_mii_mr0_clk
Async
Interface/ pr1_mii0_rxdv
L4 Fast
OCP Slave port pr1_mii0_rxd3
pr1_mii0_rxd2
pr1_mii0_rxd1
pr1_mii0_rxd0
pr1_mdio_data
OCP_HP0 MII_RT pr1_mdio_mdclk
Bridge
Async
PRU0 Core
L3 Fast (Interface/OCP pr1_mii_mt1_clk
(8KB Program RAM) pr1_mii1_rxlink
Master port)
Data RAM0 pr1_mii1_crs
(8KB) pr1_mii1_col
pr1_mii1_rxer
pr1_mii1_txen
pr1_pru0_pru_r31[16:0] Enhanced pr1_mii1_txd3
MAC Data RAM1
pr1_pru0_pru_r30[15:0] GPIO pr1_mii1_txd2
32-bit Interconnect Bus (8KB) pr1_mii1_txd1
Scratch pr1_mii1_txd0
ocp_clk Pad pr1_mii_mr1_clk
Shared RAM pr1_mii1_rxdv
uart_clk (12KB)
PRCM iep_clk Clocks/Reset pr1_mii1_rxd3
rst_main_arst_n pr1_mii1_rxd2
pr1_mii1_rxd1
CFG pr1_mii1_rxd0
pr1_edio_sof
OCP_HP1 Industrial pr1_edio_latch_in
Bridge
Async
For the availability of all features, see the device features in Chapter 1, Introduction.
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PRU-ICSS
pr1_mii0_rxd[3:0]
0
mii0_rxd[3:0]
pr1_pru1_pru_r31[8:11]
1
pin_mux_sel[0]
pru1_r31_status[8:11]
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PRU-ICSS
pr1_pru1_pru_r30[5:0]
pru1_r30[5:0]
1
pr1_pru0_pru_r30[13:8]
pru0_r30[13:8]
0
pin_mux_sel[1]
pr1_pru1_pru_r31[5:0]
0
pru1_r31[5:0]
pr1_pru0_pru_r31[13:8]
1
pin_mux_sel[1]
pru0_r31[13:8]
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Attribute Value
IO Architecture Load / Store
Data Flow Architecture Register to Register
Core Level Bus Architecture
4-Bus Harvard (1 Instruction, 3 Data)
Type
32-Bit
Instruction I/F
32-Bit
Memory I/F 0
32-Bit
Memory I/F 1
Execution Model
Scalar
Issue Type
None (Purposefully)
Pipelining
In Order
Ordering
Unsigned Integer
ALU Type
Registers
30 (R1 – R30)
General Purpose (GP)
1 (R31)
External Status
1 (R0)
GP / Indexing
Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer
Addressability in Instruction
Addressing Modes
16-bit Immediate
Load Immediate
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The processor is based on a four-bus architecture which allows instructions to be fetched and executed
concurrently with data transfers. In addition, an input is provided in order to allow external status
information to be reflected in the internal processor status register. Figure 4-5 shows a block diagram of
the processing element and the associated instruction RAM/ROM that contains the code that is to be
executed.
Op4 iram_XXX
i_data[31:0]
R0 Decode and Control
R0
op1 Mux
R1 Instruction
... Output RAM/ROM
Shifter (Clocked)
R1 R30 Shift/Mask
R31 Program i_addr[31:0]
Counter
R2
R0
Destination Selector
const_base_sel[4:0]
op2 Mux
R1 ALU Constants
... Shift/Mask Data
... I/F Constants Table
Path
R30 const_base[31:0]
R31
R29
R0 Memory mem0_XXX
Shift/Mask
I/F
op3 Mux
R30 R1 mem1_XXX
...
R30
R31(Status) Coprocessor I/F regs_XXX
R31
Register Execution Unit
File
R31(Event)
Output
Multiplexers PRU Core PRU
status_in[31:0] events_out[31:0]
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NOTE: Addresses in constants entries 24–31 are partially programmable. Their programmable bit
field (for example, c24_blk_index[3:0]) is programmable through the PRU CTRL register
space. As a general rule, the PRU should configure this field before using the partially
programmable constant entries.
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PRU<n>
i
R30 GPO Content PR1_PRU<n>_PRU_R30[ i:0 ]
INTC INTC j
GPI Content
R31(R) status status PR1_PRU<n>_PRU_R31[ j:0 ]
(bits 29:0)
(bit 31) (bit 30)
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PRU0
R31(W) 5 3 2 1 0
4
D Q
EN
see
R31(W) 5 3 2 1 0
4
D Q
EN
Simultaneously writing a '1' to pru<n>_r31_vec_valid (R31 bit 5) and a channel number from 0-15 to
pru<n>_r31_vec[3:0] (R31 bits 3:0) creates a pulse on the output of the corresponding
pr1_pru_mst_intr[x]_intr_req INTC system event (Table 4-22). For example, writing '100000' will generate
a pulse on pr1_pru_mst_intr[0]_intr_req, writing '100001' will generate a pulse on
pr1_pru_mst_intr[1]_intr_req, and so on to where writing '101111' will generate a pulse on
pr1_pru_mst_intr[15]_intr_req and writing '0xxxxx' will not generate any system event pulses. The output
values from both PRU cores in a subsystem are ORed together.
The output channels 0-15 are connected to the PRU-ICSS INTC system events 16-31, respectively. This
allows the PRU to assert one of the system events 16-31 by writing to its own R31 register. The system
event is used to either post a completion event to one of the host CPUs (ARM) or to signal the other PRU.
The host to be signaled is determined by the system event to interrupt channel mapping (programmable).
The 16 events are named as pr1_pru_mst_intr<15:0>_intr_req. For more details, see Section 4.4.2,
Interrupt Controller (INTC).
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NOTE: Some devices may not pin out all 30 bits of R31. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
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Figure 4-8. PRU R31 (GPI) Direct Input Mode Block Diagram
PRU<n>_R31
0
1
PRU<n>_GPI [0:29] …
30 28
29
Figure 4-9. PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram
PRU<n>_R31
16
PRU<n>_DATAIN 0
1
PRU<n>_CLOCKIN …
14
ocp_clk 15
Sync Flop 16
ocp_clk ocp_clk
Sync Flop Sync Flop
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The shift rate is controlled by the effective divisor of two cascaded dividers applied to the ocp_clk. These
cascaded dividers can each be configured through the PRU-ICSS CFG register space to a value of {1,
1.5, …, 16}. Table 4-14 lists sample effective clock values and the divisor values that can be used to
generate these clocks.
PRU<n>_R31
PRU<n>_DATAIN 0
27 …
27
28 (CNT_16)
28-bit shift register 29 (SB)
Bit Bucket
Bit 0 Bit 27
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NOTE: Some devices may not pin out all 32 bits of R30. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
NOTE: R30 is not initialized after reset. To avoid unintended output signals, R30 should be
initialized before pinmux configuration of PRU signals.
Figure 4-11. PRU R30 (GPO) Direct Output Mode Block Diagram
PRU<n>_R30
0
PRU<n>_GPO[0:31]
1
… 32
31
Shift out mode uses two 16-bit shadow registers (gpo_sh0 and gpo_sh1) to support ping-pong buffers.
Each shadow register has independent load controls programmable through pru<n>_r30[29:30]
(PRU<n>_LOAD_GPO_SH [0:1]). While PRU<n>_LOAD_GPO_SH [0/1] is set, the contents of
pru<n>_r31[0:15] are loaded into gpo_sh0/1.
NOTE: If any device-level pins mapped to pru<n>_r30 [2:15] are configured for the pru<n>_r30
[2:15] pinmux mode, then these pins will reflect the shadow register value written to
pru<n>_r30. Any pin configured for a different pinmux setting will not reflect the shadow
register value written to pru<n>_r30.
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The data shift will start from the lsb of gpo_sh0 when pru<n>_r30[31] (PRU<n>_ENABLE_SHIFT) is set.
Note that if no new data is loaded into gpo_shn<n> after shift operation, the shift operation will continue
looping and shifting out the pre-loaded data. When PRU<n>_ENABLE_SHIFT is cleared, the shift
operation will finish shifting out the current shadow register, stop, and reset.
Figure 4-12. PRU R30 (GPO) Shift Out Mode Block Diagram
GP_SH0
16 16
PRU<n>_R30
0
1
… 16
PRU<n>_DATAOUT
15
… GP_SH1
29 (gp_sh0_load)
30 (gp_sh1_load)
31 (enable_shift)
16 16
NOTE: Until the shift operation is disabled, the shift loop will continue looping and shifting out the
pre-loaded data if no new data has been loaded into gpo_sh<n>.
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4.4.1.3.1 Features
• Configurable Multiply Only and Multiply and Accumulate functionality via PRU register R25
• 32-bit operands with direct connection to PRU registers R28 and R29
• 64-bit result (with carry flag) with direct connection to PRU registers R26 and R27
• PRU broadside interface and XFR instructions (XIN, XOUT) allow for importing multiplication results
and initiating accumulate function
XIN R27
Upper 32 bit product R27
Upper product
R28 Auto-sampled
R28 32-bit operands:
Operand Sampled every clock.
In MAC mode, the product
R29 Auto-sampled of R28*R29 will be added
R29 to the accumulator on
Operand
every XOUT of R25.
MPY/MAC
The XFR instructions (XIN and XOUT) are used to load/store register contents between the PRU core and
the MAC. These instructions define the start, size, direction of the operation, and device ID. The device ID
number corresponding to the MPY/MAC is shown in Table 4-18.
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The PRU register R25 is mapped to the MAC_CTRL_STATUS register (Table 4-19). The MAC’s current
status (MAC_mode and ACC_carry states) is loaded into R25 using the XIN command on R25. The PRU
sets the MAC’s mode and clears the ACC_carry using the XOUT command on R25.
The two 32-bit operands for the multiplication are loaded into R28 and R29. These registers have a
direction connection with the MAC, and the MAC samples these registers every clock cycle. Note, XOUT
is not required to load the MAC. In multiply and accumulate mode, the product of R28*R29 is added to the
accumulator on every XOUT of R25.
The product from the MAC is linked to R26 (lower 32 bits) and R27 (upper 32 bits). The product is loaded
into register R26 and R27 using XIN.
32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
Multiply mode :
sampled every clock cycle XIN
MAC
The following steps are performed by the PRU firmware for multiply-only mode:
1. Enable multiply only MAC_mode.
(a) Clear R25[0] for multiply only mode.
(b) Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Load operands into R28 and R29.
3. Delay at least 1 PRU cycle before executing XIN in step 4.
4. Load product into PRU using XIN instruction on R26, R27.
Repeat steps 2 through 4 for each new operand.
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32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
The following steps are performed by the PRU firmware for multiply and accumulate mode:
1. Enable multiply and accumulate MAC_mode.
(a) Set R25[1:0] = 1 for accumulate mode.
(b) Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Clear accumulator and carry flag.
(a) Set R25[1:0] = 3 to clear accumulator (R25[1]=1) and preserve accumulate mode (R25[0]=1).
(b) Store accumulator to MAC using XOUT instruction on R25.
3. Load operands into R28 and R29.
4. Multiply and accumulate, XOUT R25[1:0] = 1
Repeat step 4 for each multiply and accumulate using same operands.
Repeat step 3 and 4 for each multiply and accumulate for new operands.
5. Load the accumulated product into R26, R27 and the ACC_carry status into R25 using the XIN
instruction.
Note: Steps one and two are required to set the accumulator mode and clear the accumulator and carry
flag.
4.4.1.4.1 Features
The PRU-ICSS scratch pad supports the following features:
• Three scratch pad banks of 30, 32-bit registers (R29:0)
• Flexible load/store options
– User-defined start byte and length of the transfer
– Length of transfer ranges from one byte of a register to the entire register content (R29 to R0)
– Simultaneous transactions supported between PRU0 ↔ Bank<n> and PRU1 ↔ Bank<m>
– Direct connection of PRU0 → PRU1 or PRU1 → PRU0 for all registers R29–R0
• XFR instructions operate in one clock cycle
• Optional XIN/XOUT shift functionality allows remapping of registers (R<n> → R<m>) during load/store
operation
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Bank0
R0
R1
R2
…
R28
R29
broadside interface
broadside interface
PRU0 Bank1 PRU1
R0 R0 R0
R1 R1 R1
R2 R2 R2
… … …
R28 R28 R28
R29 R29 R29
Bank2
R0
R1
R2
…
R28
R29
A collision occurs when two XOUT commands simultaneously access the same asset or device ID.
Table 4-21 shows the priority assigned to each operation when a collision occurs. In direct connect mode
(device ID 14), any PRU transaction will be terminated if the stall is greater than 1024 cycles. This will
generate the event pr1_xfr_timeout that is connected to INTC.
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Table 4-21. Scratch Pad XFR Collision & Stall Conditions (continued)
PRU<m> XIN (←) PRU<n> Direct Connect mode requires the transmitting core (PRU<n>) to
execute XOUT and the receiving core (PRU<m>) to execute
XIN. If PRU<m> executes XIN before PRU<n> executes XOUT,
then PRU<m> will stall until either PRU<n> executes XOUT or
the stall is greater than 1024 cycles.
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PRU0/1 Sys_event 1
R31 bit 30 Host-0 Channel-0
PRU0/1 Sys_event 2 Peripheral A
Host-1 Channel-1
R31 bit 31
Host-2 Channel-2
Host-3 Channel-3
Host-4 Channel-4
Host-6 Sys_event 31
Channel-6
Host-8 Channel-8
Peripheral Z
Host-9 Channel-9
Sys_event 58
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(1)
MII_RT mode is selected through the MII_RT register in the PRU-ICSS0 CFG register space.
(2)
Signals 63-56 and 31-0 for MII_RT Mode are the same as for Standard Mode.
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The INTC encompasses many functions to process the system events and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, and host interfacing. Figure 4-18 illustrates the flow of system events through the functions
to the host. The following subsections describe each part of the flow.
System
Status Enabling Processing
Interrupts
Prioritization
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4.4.3.2.1 Features
The industrial ethernet timer supports the following features:
• One master 32-bit count-up counter with an overflow status bit
– Runs on iep_clk or ocp_clk
– Write 1 to clear status
– Supports a programmable increment value from 1 to 16 (default 5)
– An optional compensation method allows the increment value to apply a compensation increment
value from 1 to 16, counting up to 2^24 iep_clk/ocp_clk events
• Ten 32-bit capture registers (CAPR[5:0], CAPR[7:6], CAPF[7:6])
– Eight capture inputs with optional synchronous or asynchronous mode
• Six rise-only capture inputs (CAPR[5:0])
• Two rise-and-fall capture inputs:
• CAPR[7] and CAPF[7]
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4.4.3.4.1 Features
The industrial ethernet sync block supports the following features:
• Two synchronize generation signals (SYNC0, SYNC1)
– Activation time synchronized with IEP Timer
• CMP[1] triggers SYNC0 activation time
• CMP[2] triggers SYNC1 activation time (only valid in the independent mode)
– Pulse width defined by registers or ack mode (remain asserted until software acknowledged)
– Cyclic or single-shot operation
– Option to enable or disable sync generation
• Programmable number of clock cycles between the start of SYNC0 to the start of SYNC1
Cyclic generation
SYNC0
Defined by SYNC_START
Single shot
SYNC0
Acknowledge
Cyclic generation
with acknowledgement
SYNC0
Acknowledge
Single shot
with acknowledgement
SYNC0
In SYNC1 dependent mode (SYNC_CTRL.sync1_ind_en = 0), SYNC1 depends on SYNC0 and the start
time of the SYNC1 can be defined by the SYNC1_DELAY register. Figure 4-21 shows different examples
when changing the value in the SYNC1_DELAY register. Note if the SYNC1 delay time is 0, SYNC1
reflects SYNC0.
Cyclic generation cannot be used for network time synchronized applications because only the
CMP1/CMP2 hit occurs in the compensated time domain.
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Cyclic generation
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 1
SYNC0_ACK_EN 1
SYNC_START SYNC0_PERIOD
Single shot
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 0
SYNC0_ACK_EN 1
SYNC_START
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4.4.3.5.1 Features
The industrial ethernet watchdog timer supports the following features:
• One 32-bit pre-divider for generating a WD clock (default 100μs) based on iep_clk input
• Two 16-bit Watchdog Timers:
– PDI_WD for Sync Managers WD, used in conjunction with digital input/output (DIGIO)
– PD_WD for data link layer user WD, used in conjunction with data link layer or application layer
interface actions
4.4.3.6.1 Features
The industrial ethernet digital I/O supports the following features:
• Digital data output
– 32 channels (pr1_edio_data_out[31:0])
– Five event options for driving output data output:
• End of frame event (PRU0/1_RX_EOF)
• SYNC0 events
• SYNC1 events
• Watchdog trigger
• Software enable
• Digital data out enable (optional tri-state control)
• Digital data input
– 32 channels (pr1_edio_data_in[31:0])
– DIGIO_DATA_IN_RAW supports direct sampling of pr1_edio_data_in
– DIGIO_DATA_IN supports four event options to trigger sampling of pr1_edio_data_in:
• Start of frame event in start of frame (SOF) mode
• pr1_edio_latch_in event
• SYNC0 events
• SYNC1 events
NOTE: Some devices may not pin out all 32 data I/O signals. For which data pins are available on
this device, see Table 4-3, PRU-ICSS Pin List.
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SYNC0 EN
SYNC_PWIDTH
SYNC0_PERIOD SYNC1
SYNC1_DELAY
SYNC0/1
(1) Register
(2) Internal signal wire
(3) External pin input/output
(1) Register
(2) External pin input/output
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Figure 4-23 shows the signals and registers for driving the DIGIO data out. The pr1_edio_data_out is
immediately forced to zero when OUTVALID_MODE = 1, pr1_edio_oe_ext = 1, and PD_WD_EXP = 1, or
the next update hardware post PD_WD_EXP. Delay assertion of pr1_edio_outvalid from
pr1_edio_data_out update events are controlled by software (SW_OUTVALID).
OUTVALID_OVR_EN
Delay function pr<k>_edio_outvalid
SW_OUTVALID
OUTVALID_DLY
OUT_MODE
RX_EOF
PRU<0/1> pr<k>_edio_data_out
SYNC0 DATA_OUT D Q
SYNC_PWIDTH
SYNC0_PERIOD EN
SYNC1
SYNC1_DELAY
SYNC0/1
SW_DATA_OUT_UPDATE
OUTVALID_MODE
WatchDog Timer
pr1_edio_oe_ext
32-bit WD_PREDIV
pd_wd_exp
16-bit PD_WD Timing
DATA_OUT_EN pr<k>_edio_data_out_en
16-bit PDI_WD WD_MODE Function
(1) Register
(2) Internal signal wire
(3) External pin input/output
(1) Register
(2) External pin input/output
Follow these steps to configure and write to the DIGIO Data Output.
1. Pre-configure DIGIO by setting DIGIO_EXP.OUTVALID_OVR_EN and
DIGIO_EXP.SW_DATA_OUT_UPDATE
2. Write to DIGIO_DATA_OUT to configure output data
3. To Hi-Z output, set DIGIO_DATA_OUT_EN (clear DIGIO_DATA_OUT_EN to drive value stored in
DIGIO_DATA_OUT)
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4.4.4.1 Introduction
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S
e
l 8 Receiver 8
e FIFO
8
c
t
16
Receiver
Line Timing and
Control Control
Register
Divisor
Latch (LS) 16 Baud
Divisor Generator
Latch (MS)
Line Transmitter
Status Timing and
Register Control
8 Transmitter 8 S
FIFO e
l
Transmitter 8 e 8 Transmitter UARTn_TXD
Holding c Shift
t Register signal
Register
Modem
8 Control
Control
Logic
Register
Interrupt 8 Interrupt/
Enable Event Interrupt to CPU
Register Control
Logic
Event to DMA controller
Interrupt 8
Identification
Register Power and
Emulation
Control
FIFO Register
Control
Register
NOTE: The value n indicates the applicable UART where there are multiple instances. For the PRU-ICSS, there is
only one instance and all UART signals should reflect this (e.g., UART0_TXD instead of UARTn_TXD).
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Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most
significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about
these register fields, see the UART register descriptions. These divisor latches must be loaded during
initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor
latches results in two wait states being inserted during the write access while the baud generator is loaded
with the new value.
Figure 4-26 summarizes the relationship between the transferred data bit, BCLK, and the UART input
clock. Note that the timing relationship depicted in Figure 4-26 shows that each bit lasts for 16 BCLK
cycles . This is in case of 16x over-sampling mode. For 13× over-sampling mode each bit lasts for 13
BCLK cycles .
Example baud rates and divisor values relative to a 192-MHz UART input clock and 16× over-sampling
mode are shown in Table 4-24.
PRU-ICSS
UART
Receiver
DLH:DLL timing and
control
Transmitter
timing and
control
Other logic
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Figure 4-26. Relationships Between Data Bit, BCLK, and UART Input Clock
n UART input clock cycles, where n = divisor in DLH:DLL
BCLK
BCLK
UARTn_TXD,
D1 D2
UARTn_RXD
D0
Table 4-24. Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 5000 2400 0.00
4800 2500 4800 0.00
9600 1250 9600 0.00
19200 625 19200 0.00
38400 313 38338.658 -0.16
56000 214 56074.766 0.13
128000 94 127659.574 -0.27
300000 40 300000 0.00
Table 4-25. Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 6154 2399.940 -0.0025
4800 3077 4799.880 -0.0025
9600 1538 9602.881 0.03
19200 769 19205.762 0.03
38400 385 38361.638 -0.10
56000 264 55944.056 -0.10
128000 115 128428.094 0.33
300000 49 301412.873 0.47
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4.4.4.2.4.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
4.4.4.2.4.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the
UART line control register (LCR). Based on the settings chosen in LCR, the UART receiver accepts the
following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
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1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2)
It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1, 1.5, or 2 STOP bits, depending on the STOP bit selection.
The UART receives in the following format:
1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + 1 STOP bit
It receives 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1 STOP bit.
The protocol formats are shown in Figure 4-27.
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4.4.4.2.5 Operation
4.4.4.2.5.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
THR receives data from the internal data bus, and when TSR is ready, the UART moves the data from
THR to TSR. The UART serializes the data in TSR and transmits the data on the UARTn_TXD pin.
In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled in the interrupt
enable register (IER), an interrupt is generated. This interrupt is cleared when a character is loaded into
THR or the interrupt identification register (IIR) is read. In the FIFO mode, the interrupt is generated when
the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or IIR is
read.
4.4.4.2.5.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16× receiver
clock. Receiver section control is a function of the UART line control register (LCR). Based on the settings
chosen in LCR, the UART receiver accepts the following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
RSR receives the data bits from the UARTn_RXD pin. Then RSR concatenates the data bits and moves
the resulting value into RBR (or the receiver FIFO). The UART also stores three bits of error status
information next to each received character, to record a parity error, framing error, or break.
In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled
in the interrupt enable register (IER), an interrupt is generated. This interrupt is cleared when the character
is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level
selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the
trigger level.
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Device Off-chip
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UARTn_RTS
Start Bits0−7 Stop Start Bits 0−7 Stop Start Bits 0−7 Stop
UARTn_TXD
UARTn_CTS
(1) When UARTn_CTS is active (low), the transmitter keeps sending serial data out.
(2) When UARTn_CTS goes high before the middle of the last STOP bit of the current byte, the transmitter
finishes sending the current byte but it does not send the next byte.
(3) When UARTn_CTS goes from high to low, the transmitter begins sending data again.
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4.4.4.2.7 Initialization
The following steps are required to initialize the UART:
1. Perform the necessary device pin multiplexing setup (see your device-specific data manual).
2. Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers
(DLL and DLH).
3. If the FIFOs will be used, select the desired trigger level and enable the FIFOs by writing the
appropriate values to the FIFO control register (FCR). The FIFOEN bit in FCR must be set first, before
the other bits in FCR are configured.
4. Choose the desired protocol settings by writing the appropriate values to the line control register
(LCR).
5. If autoflow control is desired, write appropriate values to the modem control register (MCR). Note that
all UARTs do not support autoflow control; see your device-specific data manual for supported
features.
6. Choose the desired response to emulation suspend events by configuring the FREE bit, and enable
the UART by setting the UTRST and URRST bits in the power and emulation management register
(PWREMU_MGMT).
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IER(ERBI)
RTOINT Arbiter UART interrupt
request to CPU
Receiver time-out
Overrun error
Parity error RLSINT
Framing error IER(ELSI)
Break
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4.4.5 ECAP
The PRU ECAP module within the PRU-ICSS is identical to the ECAP module in the AM335x PWMSS.
For additional details about the ECAP module, see Section 15.3, Pulse-Width Modulation Subsystem
(PWMSS).
4.4.6 MII_RT
4.4.6.1 Introduction
The Real-time Media Independent Interface (MII_RT) provides a programmable I/O interface for the PRUs
to access and control up to two MII ports. The MII_RT module can also be configured to push and pull
data independent of the PRU cores.
NOTE: To ensure the MII_RT IO timing values published in the device data manual, the ocp_clk
must be configured for 200 MHz (default value) and TXCFG<n>_TX_CLK_DELAY must be
set to 6h (non-default value).
4.4.6.1.1 Features
The PRU-ICSS MII_RT module supports:
• Two MII ports
– Each MII port has:
• 32-byte RX L1 FIFO
• 64-byte RX L2 buffer
• 64-byte TX L1 FIFO
– Rate decoupling on TX L1 FIFO
– Configurable pre-amble removal on RX L1 FIFO and insertion on TX L1 FIFO
– Configurable TX L1 FIFO trigger (10 bits with 40 ns ticks)
• MII port multiplexer per direction to support line/ring structure
– Link detection through RX_ERR
• Cyclic redundancy check (CRC)
– CRC32 generation on TX path
– CRC32 checker on RX path
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PRU0
PRU1
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Bank 0
32 bytes of data XFR
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
PRU
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
Bank 0
32 bytes of data XFR Memory
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
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The data following the SFD is formatted in a 4-bit nibble structure. Figure 4-37 illustrates the nibble order.
The MSB arriving first is on the LSB side of a nibble. When receiving data, the MII_RT receive logic will
wait for the next nibble to arrive before constructing a byte and delivering to the PRU.
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D0 D1 D2 D3
Constructing a byte and LSB MSB LSB MSB
sent to PRU and TX L1 FIFO
First Nibble Second Nibble
R30 (W):
TX Interface Data
R31 (R):
Data
RX Interface
R31 (W):
RX & TX cmd Interface
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pop push
(R31 cmd) (R31 cmd)
FIFO 32 bytes
FIFO 64 bytes
RX L1 TX L1
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This submodule also keeps track of a running count of receive error events within a 10 μs error detection
window, as shown in Figure 4-44. The INTC is notified when 32 or more events have occurred in a 10 μs
error detection window. The error detection window is not a sliding window but a non-overlapping window
with no specific initialization time with respect to incoming traffic. The timer starts its 10 μs counts
immediately after de-assertion of reset to the MII_RT module.
(A)
10 μs
(B)
A There are fewer than 32 consecutive error events in the 10 μs window. The detection module will not forward to the
interrupt controller (INTC).
B There are more or equal to 32 error events in the 10 μs window. The detection module will notify the interrupt
controller (INTC).
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Once the PRU has received RX data, the PRU can both manipulate received data or send data to the TX
MII Interface.
PRU
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
When the new data is received, the PRU is provided with up to two bytes at a time in the R31 register, as
shown in Figure 4-46. Once the PRU processes the incoming data, it instructs the MII_RT by writing to the
R31 command interface bits to pop one or two bytes of data from the 32-byte RX FIFO. The pop operation
causes current contents of R31 to be refreshed with new data from the incoming packet. Each time the
data is popped, the status bits change to indicate so. If the pop is completed and there is no new data, the
status bits immediately change to indicate no new data. Note the current R31 content, including data, will
be lost after issuing the pop operation. If this information needs to be accessed later, the PRU should
store the existing R31 content before popping new data.
RESERVED
<ERR> bits
FIFO ERROR_CRC
ERROR_NIBBLE
RX_SOF
MII RX_DV
RX_SFD
MII RX_CLK
RX_EOF
RX_ERROR
WORD_RDY
BYTE_RDY
DATA_RDY
Table 4-32 describes the receive interface data and status contents provided by the R31 register. These
contents are available when R31 is read. To configure this register, the PRU GPI mode should be set for
MII_RT mode in the CFG register space. Note the following:
1. If the data from the receive path is not read in time, it could cause an overflow event because the data
is still continuously provided to the 32-byte receive FIFO. Due to the receive FIFO overflow, the data
gets automatically discarded to avoid lack of space in the FIFO. At the same time, an interrupt is raised
to the INTC through a system event (PRU<n>_RX_OVERFLOW). To detect an overflow condition, the
PRU should poll for this system event condition, and a RX RESET command through the R31
command interface is required to clear out from this condition. The received Ethernet frame is
corrupted and should not be used for further processing, as bytes have been dropped due to the
overflow condition. A FIFO reset is recommended.
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2. The receive data in the R31 register is available following synchronization to the PRU clock domain.
So, there is a finite delay (120 ns) when data is available from MII interface and it is accessible to the
PRU.
3. The receive FIFO also has the capability to be reset through software. When reset, all contents of
receive FIFO are purged and it may result in the current frame not being received as expected. When
a frame is being received and the PRU resets the RX FIFO, the remaining frame is not placed into the
RX FIFO. However, any new frame arriving on the receive MII port will be stored in the FIFO.
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Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode)
Bits Field Name Description
31:30 RESERVED In case of register interface, these bits are provided to PRU by other
modules in PRU-ICSS. From the MII_RT module point of view, these
bits are always zero.
29 RX_MIN_FRM_CNT_ERR RX_MIN_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is less than the value defined by RX_MIN_FRM_CNT.
RX_MIN_FRM_CNT_ERR is cleared by RX_ERROR_CLR.
28 RX_MAX_FRM_CNT_ERR RX_MAX_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is more than the value defined by
RX_MAX_FRM_CNT_ERR. RX_MAX_FRM_CNT_ERR is cleared by
RX_ERROR_CLR.
27 RX_EOF_ERROR RX_EOF_ERROR is set to 1 when an RX_EOF event or RX_ERROR
event occurs. RX_EOF_ERROR is cleared by RX_ EOF_CLR and/or
RX_ ERROR_CLR.
26 RX_MAX_PRE_CNT_ERR RX_MAX_PRE_CNT_ERR is set to 1 when the number of nibbles
equaling 0x5 before SFD event (0x5D) is more than the value defined by
RXPCNT0/1 [RX_MAX_PRE_CNT]. RX_MAX_PRE_CNT_ERR is
cleared by RX_ERROR_CLR.
25 RX_ERR RX_ERR is set to 1 when pr1_mii0/1_rxer is asserted while
pr1_mii0/1_rxdv bit is set. RX_ERR is cleared by RX_ERROR_CLR.
24 ERROR_CRC ERROR_CRC indicates that the frame has a CRC mismatch. This bit is
valid when the RX_EOF bit is set. It should be noted that ERROR_CRC
bit is ready in early status, which means it is calculated before data is
available in RXL1 FIFO. ERROR_CRC is cleared by RX_ERROR_CLR.
23 ERROR_NIBBLE ERROR_NIBBLE indicates that the frame ended in odd nibble. It should
be considered valid only when the RX_EOF bit and pr1_mii0/1_rxdv are
set. Nibble counter is enabled post SFD event. It should be noted that
ERROR_NIBBLE bit is ready in early status, which means it is
calculated before data is available in RXL1 FIFO. ERROR_NIBBLE is
cleared by RX_ERROR_CLR.
22 RX_SOF RX_SOF transitions from low to high when the frame data starts to
arrive and pr1_mii0/1_rxdv is asserted. Note there will be a small sync
delay of 0ns – 5ns. The PRU must write one to this bit through the R31
command interface to clear it. The recommended time to clear this bit is
at the end of frame (EOF). It should be noted that RX_SOF bit is ready
in early status, which means it is calculated before data is available in
RXL1 FIFO.
21 RX_SFD RX_SFD transitions from low to high when the SFD sequence (0x5D)
post RX_SOF is observed on the receive MII data. The PRU must write
one to this bit through the R31 command interface to clear it. The
recommended time to clear this bit is at the end of frame (EOF). It
should be noted that RX_SFD bit is ready in early status, which means it
is calculated before data is available in RXL1 FIFO.
20 RX_EOF RX_EOF indicates that the frame has ended and pr1_mii0/1_rxdv is de-
asserted. It also validates the CRC match bit. Note there will be a small
sync delay of 0ns – 5ns. The PRU must write one to clear this bit in the
R31 command interface at the end of the frame. It should be noted that
RX_EOF bit is ready in early status, which means it is calculated before
data is available in RXL1 FIFO.
19 RX_ERROR RX_ERROR indicates one or more of the following errors occurred:
• RX_MAX/MIN_FRM_CNT_ERR
• RX_MAX/MIN_PRE_CNT_ERR
• RX_ERR
RX_ERROR is cleared by RX_ERROR_CLR.
18 WORD_RDY WORD_RDY indicates that all four nibbles in R31 have valid data. There
is a 2 clock cycle latency from the command RX_POP16 to
WORD_RDY update. Therefore, firmware needs to insure it does not
read WORD_RDY until 2 clock cycles after RX_POP16.
17 BYTE_RDY BYTE_RDY indicates that the lower two nibbles in R31 have valid data.
There is a 2 clock cycle latency from the command RX_POP8 to
BYTE_RDY update. Therefore, PRU firmware needs to insure it does
not read BYTE_RDY until 2 clock cycles after RX_POP8.
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Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode) (continued)
Bits Field Name Description
16 DATA_RDY DATA_RDY indicates there is valid data in R31 ready to be read. This
bit goes to zero when the PRU does a POP8/16 and there is no new
data left in the receive MII port. This bit is high if there is more receive
data for PRU to read. There is a 2 clock cycle latency from the
command RX_POP16/8 to WORD_RDY/BYTE_RDY update. Therefore,
PRU firmware must einsure it does not read BYTE_RDY/WORD_RDY
until 2 clock cycles after RX_POP16/8.
15:8 BYTE1 Data Byte 1. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
7:0 BYTE0 Data Byte 0. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
PRU
RX L2
Bank 0 R2
32 bytes of data XFR …
R13
Bank 1
32 bytes of data R18
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
The 64-byte RX L2 buffer is divided into two 32 byte banks, or ping/pong buffers. When the RX L2 is
enabled, the incoming data from the MII RX port will transmit first to the 32 byte RX L1 FIFO. RX L1
pushes data into RX L2, starting when the first byte is ready until the final EOF marker. The RX L2 buffer
does not apply any backpressure to the RX L1 FIFO. Therefore, it is the PRU firmware’s responsibility to
fetch the data in RX L2 before it is overwritten by the cyclic buffer. The RX L1 will remain near empty, with
only one byte (nibble) stored.
Each RX L2 bank holds up to 32 bytes of data, and every four nibbles (or 16 bits) of data has a
corresponding 8-bit status. The data and status information are stored in packed arrays. In each bank, R2
to R9 contains the data packed array and R10 to R13 contains the status packed array. Figure 4-48
shows the relationship of the data registers and status registers. The RX L2 status registers record status
information about the received data, such as ERROR_CRC, RX_ERROR, STATUS_RDY, etc. The RX L2
status register details are described in Table 4-33. Note RX_RESET clears all Data and Status elements
and resets R18.
Data Register R2 R3 R4 R5 R6 R7 R8 R9
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Bank 0 and Bank 1 are used as ping/pong buffers. RX L2 supports the reading of a write pointer in R18
that allows software to determine which bank has active write transactions, as well as the specific write
address within packed data arrays.
The PRU interacts with the RX L2 buffer using the high performance XFR read instructions and broadside
interface. Table 4-34 shows the device XFR ID numbers for each bank.
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XFR read transactions are passive and have no effect on any status or other states in RX L2. The
firmware can also read R18 to determine which bank has active write transactions, and the location of the
transaction. With this information, the firmware can read multiple times the stable preserved data. When
RX L1 data is written to RX L2, the next status byte gets cleared at the same time the current status byte
gets updated. The rest of the status buffer is persistent. When the software accesses any register of the
ping/pong buffer, the software must issue an XFER read transaction to fetch the latest or current state of
the ping/pong buffer. The PRU registers do not reflect the current snapshot of L2 unless an XFER is
issued by the software.
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PRU
R30
R31
TX L1
TX_DATA
FIFO 64 bytes MII TX port
TX_EN
Figure 4-50 shows the R30 transmit interface. The lower 16 bits of the R30 (or FIFO transmit word)
contain transmit data nibbles. The upper 16 bits contain mask information. The operation to be performed
on the transmit interface is controlled by PRU writes to the R31 command interface. Table 4-35 describes
the TXMASK and TXDATA bit fields of the R30 transmit interface.
TX MASK[15:8]
MII TX DATA
TX MASK[7:0]
Using the TX mask, the PRU can send a mix of R30 and RX L1 FIFO data to the TX L1 FIFO. Note the
TX mask is only available when the PRU is fed one word or byte at a time by the RX L1 FIFO. It is not
applicable when the RX L2 buffer is enabled. To disable TX mask, set TXMASK to 0xFFFF.
As shown in Figure 4-51, the PRU drives the MII transmit interface through its R30 register. The contents
of R30 and RX data from the receive interface are taken and fed into a 64 byte transmit FIFO.
Before transmission, a mask is applied to the data portion of the R30 register. By using the mask, the
PRU firmware can control whether received data from the RX L1 FIFO is sent to transmit, R30 data is sent
to transmit, or a mix of the two is sent. The Boolean equation that is used by MII_RT to compose TX data
is:
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) | (RXDATA[7/15:0] & ~MASK [7/15:0])
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PRU 0/1
R30
R31
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) |
(RXDATA[7/15:0] & ~MASK [7/15:0])
TX L1
RX L1 TX_DATA
RX_DV FIFO 64 bytes MII TX port
MII RX port FIFO 32 bytes TX_EN
RX_CLK
1. Push
2. Pop
Mask
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On the transmit side, the order of the two data bytes and mask bytes in TX R30 are configurable through
the TX_BYTE_SWAP bit in the TXCFG0/1 registers, as shown in Table 4-38. Note the Nibble0 is the first
nibble received.
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There are two receive multiplexer instances to enable selection of RX MII path for each PRU. The select
lines of the RX multiplexers are driven from the PRU-ICSS programmable registers (RXCFG0/1).
TX_DATA[3:0]
TX_DATA[3:0]
TX MII
TX_PRU1 TX_EN
TX_EN Multiplexer TX_MII1/0
(Port 0/1)
TX_SOF
TX_DATA[3:0]
RX_MII0/1
TX_EN
The transmit multiplexers enable the PRU-ICSS to either operate in a bypass mode where the PRU is not
involved in processing MII traffic or use of one of the PRU cores for transmitting data into the MII interface.
There are two instances of the TX MII multiplexer and the select lines for each TX multiplexer are
provided by the PRU-ICSS. The select lines are common between register and FIFO interface. It is
expected that the select lines will not change during the course of a frame so that can avoid data
exchange error.
Bank 0 PRU
32 bytes of data XFR R0
…
Bank 1 R31
32 bytes of data
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4.4.7 MDIO
The MDIO module within the PRU-ICSS is identical to the MDIO module in Section 14.3.8.
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4.5 Registers
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352 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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354 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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356 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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358 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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360 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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362 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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364 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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366 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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368 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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370 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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372 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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374 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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376 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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378 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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380 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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382 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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384 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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386 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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388 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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390 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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392 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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394 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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396 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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398 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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400 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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402 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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404 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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406 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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408 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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410 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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412 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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414 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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416 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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418 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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420 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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422 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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424 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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426 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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428 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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430 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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432 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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434 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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436 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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438 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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440 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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442 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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3 RESERVED R 0h
2 SYNC1_EN R/W 0h SYNC1 generation enable
0: Disable
1: Enable
1 SYNC0_EN R/W 0h SYNC0 generation enable
0: Disable
1: Enable
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444 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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446 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 447
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448 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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450 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PRE_DIV
R/WtoClr-4E20h
7 6 5 4 3 2 1 0
PRE_DIV
R/WtoClr-4E20h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
452 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PDI_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PDI_WD_TIME
R/WtoReset-3E8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PD_WD_TIME
R/WtoReset-3E8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
454 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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23 22 21 20 19 18 17 16
Reserved PDI_WD_STAT
R-0h R-1h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_STAT
R-0h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_EXP_CNT
R/WtoClr-0h
7 6 5 4 3 2 1 0
PDI_EXP_CNT
R/WtoClr-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
456 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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23 22 21 20 19 18 17 16
Reserved PDI_WD_EN
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_EN
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 457
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458 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 459
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460 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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462 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 463
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all accesses read or modify DLH. DLH can also be accessed with address offset 24h.
• IIR and FCR share one address. Regardless of the value of the DLAB bit, reading from the address
gives the content of IIR, and writing modifies FCR.
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15 8 7 0
Reserved DATA
R-0 R-0
LEGEND: R = Read only; -n = value after reset
466 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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15 8 7 0
Reserved DATA
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
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15 4 3 2 1 0
Reserved Rsvd ELSI ETBEI ERBI
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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15 8 7 6 5 4 3 1 0
Reserved FIFOEN Reserved INTID IPEND
R-0 R-0 R-0 R-0 R-1
LEGEND: R = Read only; -n = value after reset
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CAUTION
For proper communication between the UART and the EDMA controller, the
DMAMODE1 bit must be set to 1. Always write a 1 to the DMAMODE1 bit, and
after a hardware reset, change the DMAMODE1 bit from 0 to 1.
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15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RXFIFTL Reserved DMAMODE1 (1) TXCLR RXCLR FIFOEN
W-0 R-0 W-0 W1C-0 W1C-0 W-0
LEGEND: R = Read only; W = Write only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
(1)
Always write 1 to the DMAMODE1 bit. After a hardware reset, change the DMAMODE1 bit from 0 to 1. DMAMODE = 1 is required for
proper communication between the UART and the DMA controller.
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15 8 7 6 5 4 3 2 1 0
Reserved DLAB BC SP EPS PEN STB WLS
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 4-237. Relationship Between ST, EPS, and PEN Bits in LCR
ST Bit EPS Bit PEN Bit Parity Option
x x 0 Parity disabled: No PARITY bit is transmitted or checked
0 0 1 Odd parity selected: Odd number of logic 1s
0 1 1 Even parity selected: Even number of logic 1s
1 0 1 Stick parity selected with PARITY bit transmitted and checked as set
1 1 1 Stick parity selected with PARITY bit transmitted and checked as cleared
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15 6 5 4 3 2 1 0
Reserved AFE (1) LOOP OUT2 OUT1 RTS (1) Rsvd
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
All UARTs do not support this feature, see your device-specific data manual for supported features. If this feature is not available, this bit
is reserved and should be cleared to 0.
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15 8 7 6 5 4 3 2 1 0
Reserved RXFIFOE TEMT THRE BI FE PE OE DR
R-0 R-0 R-1 R-1 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
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476 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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15 8 7 6 5 4 3 2 1 0
Reserved CD RI DSR CTS DCD TERI DDSR DCTS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 0
Reserved SCR
R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 0
Reserved DLL
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
15 8 7 0
Reserved DLH
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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15 8 7 0
Reserved REVID2
R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 14 13 12 1 0
Rsvd UTRST URRST Reserved FREE
R/W-0 R/W-0 R/W-0 R-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-247. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 Reserved 0 Reserved. This bit must always be written with a 0.
14 UTRST UART transmitter reset. Resets and enables the transmitter.
0 Transmitter is disabled and in reset state.
1 Transmitter is enabled.
13 URRST UART receiver reset. Resets and enables the receiver.
0 Receiver is disabled and in reset state.
1 Receiver is enabled.
12-1 Reserved 1 Reserved
0 FREE Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When
halted, the UART can handle register read/write requests, but does not generate any
transmission/reception, interrupts or events.
0 If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the
UART halts after completion of the one-word transmission.
1 Free-running mode is enabled; UART continues to run normally.
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15 1 0
Reserved OSM_SEL
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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484 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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486 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 487
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488 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 489
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490 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 491
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492 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 493
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494 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 495
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496 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 497
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498 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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500 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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502 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 503
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504 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 505
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506 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 507
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508 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 509
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510 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 511
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512 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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514 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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SPRUH73P – October 2011 – Revised March 2017 Programmable Real-Time Unit Subsystem and Industrial Communication 515
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516 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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518 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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520 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73P – October 2011 – Revised March 2017
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