Wa0011.
Wa0011.
Wa0011.
CO.02: Compare and choose appropriate Microprocessor (8085/ 8086) and Microcontroller
(8051/ARM) to meet specified performance requirements for a system design.
CO.03: Apply knowledge for interfacing memory devices and DMA with processor as well as
controller.
CO.06: Develop concepts on virtual memory and cache memory by identifying architecture of
advanced Coprocessors (286, 486, Pentium).
Sl Questions Marks CO
No. No.
1. A stack is 1 1
a. 6 bits b. 8 bits
c.12 bits d.16 bits.
26. Describe the function of the following pins in 8085 MPU – READY, 5 1,3
HOLD, INTR, SOD, TRAP
Sl Questions Marks CO
No. No.
1. How does the microprocessor know what operation to perform first 1 1
a. Read/Write memory
b. Opcode fetch
c. Read/Write I/O
d. none.
2. How many I/O ports can be accessed by direct method of 8085 μP 1 1
a. 8 b.256 c.32 K d.64 K.
3. What is the addressing mode used in instruction MOV M, C? 1 1,2,5
a. Direct b. Indirect
c. Induced d. Immediate
4. When a subroutine is called, the address of the instruction following the 1 1
Call instruction is stored in/on the
a. stack pointer c.accumulator
b. program counter d.stack.
5. When the RET instruction at the end of a subroutine is executed, 1 1
a. the information where the stack is initialized is transferred to the
stack pointer.
b. the memory address of the RET instruction is transferred to the PC.
c. two data bytes stored in the top two locations of the stack are
transferred to the PC.
d. two data bytes stored in the top two locations of the stack are
transferred to the SP.
6. Whenever the POP H instruction is executed, 1 1
a. data bytes in the HL pair are stored on the stack.
b. two data bytes at the top of the stack are transferred to the HL reg.
Pair.
c. two data bytes at the top of the stack are transferred to the PC.
d. two data bytes from the HL register that were previously stored on
the stack are transferred back to the HL registers.
7. The addressing modes used in PUSH B is 1 1
i)direct ii) register
iii) immediate iv) register indirect
8. Which instruction is equivalent to 1 byte unconditional jump instruction? 1 1
i) SPHL ii) XTHL
iii) PCHL iv) none of these
9. Recursive subroutine is 1 1
i)multiple calling subroutine ii) multiple ending subroutine
iii)nested subroutine iv)re-entrant subroutine
10. Apart from certain arithmetic operations, RAR/RAL is useful for 1 1,3
i)DMA controlling ii) Serial data transfer
iii)Decimal adjust operations iv) Prioritizing interrupts
11. For the 8086 instruction MOV AX, [BP+SI], the default segment used is 1 1,2,5
i)CS ii) DS iii) SS iv) ES
12. The instruction ‘MOV AX, 04 [BP] [DI]’ is a best example for which 1 1,2,5
one of the following addressing modes?
a) register addressing b) immediate addressing,
c) based indexed memory addressing d) none of these
13. What are the conditions that BIU to suspend fetching instructions? 1 1
a) Current instruction requires access to memory or I/O port
b) A transfer control (Jump or call) instruction occurs.
c)Instruction queue is full
d) All of these.
14. Which one of the following segments is used by the ‘CMPSB’ string 1 1,2,5
instruction for the destination?
a) CS b) DS c) ES d) SS
15. Briefly explain about different flags available in 8085 microprocessor. 5 1
17. Discuss the functions performed by SIM instruction. Also draw the bit 5 1
pattern.
18. Draw pin diagram of 8085 µp. Explain the function of the pins of Intel 6 1
8085A microprocessor.
19. Discuss with diagram how various control signals are generated in 8085 4 1
microprocessor.
20. Sketch the internal functional block diagram of architecture of the 8085 8 1
and discuss the function of all the blocks.
22. What is the difference between level sensitive and edge sensitive 3 1
interrupts.
23. What is subroutine? What is the difference between CALL & JMP 5 1
instructions?
24. How does ALE signal demultiplex the AD0-AD7 bus? Explain with diagram. 5 1,2,5
28. Briefly explain the function of RST instruction. Also write down the 5 1
restart addresses of different interrupts.
31. Discuss ODD and EVEN Bank Memory Organization of 8086. 5 1,2,5
35. What do you mean by addressing mode? What are the different addressing 5 1
modes supported by 8086 microprocessor? Explain each of them with suitable
examples.
36. What is the function of TEST, LOCK and MN/MX pin in 8086? 5 1
37. What is the purpose of the Queue?How many words do the queue store in the 5 1
8086?
38. Discuss the functions performed by BX, BP, and CX in addition to the function 5 1
of general-purpose register? What are the functions of IP &SP?
39. What is the Off-set Address and Physical Address? How is Physical Address 5 1,2,5
computed in case of 8086?
40. Explain the concept of segmented memory.What is the purpose of memory 5 1,2,5
segmentation and its advantages?
41. What do you mean by interrupt I/O? Briefly explain about different interrupts 5 1
available in 8086 microprocessor.
42. What is the role of execution unit of 8086 microprocessor? Explain the working 4 1,2,5
of its each section.
43. Explain the differences between I/O mapped I/O and memory mapped I/O. 2+3 1,3
Discuss the differences between absolute decoding and partial decoding with
example.
Sl Questions Marks CO
No. No.
1. Whenever the instruction LHLD is executed, number of T-States 1 1,2,5
required are
a. 10 b.13 c.16 d.12.
2. If the crystal with 8085 is 2 MHz, the time required to execute an 1 1,2,5
instruction of 20 T states is?
i) 20µs ii) 10µs iii) 40µsiv) 5µs
3. What is the width of data bus and address bus for 4096 X 8 memory? 1 1,3
i)16 and 12 ii) 8 and 12
iii)12 and 32 iv) 32 and 16
4. In a partial decoding scheme using 8 bit addressing, two address lines 1 1,3
A1&A0 are not connected to the decoding NAND gate. Which addresses
are made redundant?
i)00H,01H,03H,04H ii)00,02,13,14
iii)13,05,03,04 iv)00,01,02,03
5. What is the vector location for INT3 0f 8086? 1 1
a) 0006H b) 0008H c) 0012H d) 0014H
6. An 8255 is interfaced with 8086 the port A address is 070H. What will 1 1,4
be the address of port C?
a) 074H b) 0744H c) 0745H d) 0746H
7. What physical address is represented by 4370: 561EH? 1 1,2,5
a) 4370EH b) 0561EH c) 48D1E d) 5A550H
8. Specify the register contents and the flag status (S, Z, CY) after the instruction 4 1,2,5
ORA A is executed.
MVI A, A9H
MVI B, 57H
ADD B
ORA A
RST 1
9. Explain how many times the following loop will be executed. 5 1,2,5
LXI B, 0007H
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
HLT
10. The following sequences of instructions are executed by 8085μP 5 1,2,5
C000 LXI SP, D050
POP H
XRA A
MOV A, H
ADD L
MOV H, A
PUSH H
PUSH PSW
HLT
What are the contents of SP, PC registers, Accumulator, HL pair?
11. Calculate the COUNT for the following program to obtain 100 microsecond 3 1,2,5
loop delay, and express the value in HEX. Use the clock of your system
T state
MVI B, COUNT
LOOP: NOP 4
NOP 4
DCR B 4
JNZ LOOP 10/7
12. Read the following program and answer the questions. 5 1,2,5
Line No. Mnemonics
1 LXI SP,0400H
2 LXI B,2055H
3 LXI H,22FFH
4 LXI D,2090H
5 PUSH H
6 PUSH B
7 MOV A, L
. .
. .
. .
20 POP H
What is stored in SP after the execution of line 1?
What is memory location of stack where the first data byte will be stored?
What is stored in memory location 03FE H when line 5 is executed?
After the execution of line 6, what is address of the SP register, and what is
stored in stack memory location 03FD H?
Specify the contents of register pair HL, after the execution of line 20?
13. Write an ALP for 8086 for the addition of a series of 8 bit numbers. The series 5 1
contains 100 numbers.
14. Determine the memory address accessed by each of the following instructions 5 1,2,5
in real
mode operation, if DS=1000H, SS= 2000H, BP= 1000H, BX= 0200H &
DI=0100H.
i)MOV AL,[BP+DI]
ii)MOV CX,[DI]
iii)MOV AL,[1234H]
iv)MOV DL,[BX+1000H]
15. What is the function of Type-2 interrupt in 8086 microprocessor? If an 8086 4 1,2,5
Type-2 interrupt service routine starts from 5000H:0100H memory, how will
this address be stored in interrupt vector table?
17. From memory location 00490H successively 0AH, 9CH, B2H, 78H are stored 4 1,2,5
respectively. What does AX contain after the execution of each following
instructions. Assume that SI contains 00490H and BP contains 0002H.
MOV AX, (SI)
MOV AX, (SI+1)
MOV AX, (SI) (BP)
18. Write an assembly language program to add 10 bytes of data in the DS starting 5 1,2,5
from 2000H:2000H and store the result in 3000H:2000H.
19. The memory address of the last location of an 8K byte memory chip is FFFFH 5 1,3
then finds the starting address. How many address lines are used to identify an
I/O port in the I/O mapped I/O and in the memory mapped I/O methods.
20. If the memory chip size is 2048 * 8 bits, how many chips are required to make 2 1,3
up 16K byte memory?
21. If the memory address range of 6116 R/W memory chip(2048X8) is 8800H - 6 1,3
8FFFH, draw the interfacing scheme of the same using 74LS138 3to 8 decoder
with 8085 MPU. Assume output line of the decoder is identified as MSEL.
Module: II Peripherals Interfacing
Bloom’s Taxonomy Level: I
6. Draw the block diagram of 8254 timer and describe its different section. 5 4
8. Specify the bit of a control word for the 8255A, which differentiates between the I/O 5 4,5
mode and BSR mode.
9. What is USART? Why is USART used?what are the functions of command word and 5 4,5
status word in 8251?Differentiate between synchronous and asynchronous serial data
transfer.
1. In BSR mode of 8255 if the control word is initialized with 0FH, then which bit of port 1 4,5
C is set or reset?
a)Only PC0 is set,others are reset b) PC0 is reset
c)Only PC7 is set,others are reset d)All are set
2. An 8255 is interfaced with 8086 the port A address is 070H. What will be the address 2 4
of port C?
a) 074H b) 0744H c) 0745H d) 0746H
3. Set up the 8254A as a square-wave generator with 1ms period, if the i/p frequency is 1 5 4,5
MHz.
5. In mode 1 operation of 8255 PPI, what are the control signals when ports A&B act as 5 4,5
output ports? Discuss the control signals.
6. List the necessary conditions to generate INTR when port A of the 8255A is set up as 5 4,5
an o/p port in Mode 1.
Figure 1
Discuss your answer.
9. With the help of a block diagram explain a microprocessor-based system point out the 5 2,4
role of microprocessor and other peripheral blocks.
Module: III Coprocessor and microcontroller
Bloom’s Taxonomy Level: I
25. Briefly discuss the functions of TMOD, TCON, PCON, SBUF, SCON registers. 5 1,2
27. Enlist the various flags in PSW register & discuss them. 5 1,2
Module: III Coprocessor and microcontroller
Bloom’s Taxonomy Level: II
1.1. How can port 0 (P0) of 8051 microcontroller be used as input output port? 2 1,2
i) MOV A, #0FFH & Then MOV P0, A iii) MOV A, #00H & Then MOV P0, A
ii) MOV A, @0FFH &Then MOV A,P0 iv) MOV A, @00H &Then MOVA,P0
2. The 80286 CPU operates in 1 6
i)Real address mode ii)all of these
iii) Protected virtual address mode iv) none of these
3. The salient feature of Pentium is 1 6
i) superscalar architectureii) super pipelined architecture
iii) superscalar and super pipelined architectureiv) none of the mentioned
4. The number of stages of the integer pipeline, U, of Pentium is 1 6
i) 2 ii) 4 iii) 3 iv) 6
5. The speed of integer arithmetic of Pentium is increased to a large extent by 1 6
i) on-chip floating point unit iii) superscalar architecture
ii) 4-stage pipelines iv) all of the mentioned
6. In the real mode, the memory that is reserved for system initialization is 1 6
i) from 004FFH to 0FFFFH iii) from 004FFH to 05FFFH
ii) from FFFF0H to FFFFFH iv) from FFF00H to FFFFFH
7. Draw and discuss the internal block diagram of 80286. 5 6
10. What is the use of register banks in 8051? How bank switching be done? 5 1,2
12. Is the 8051 stack a LIFO or FIFO stack? Explain with example. What is the value of SP 2 1,2
on reset?
13. Draw the internal data memory organization of 8051 family of micro-controllers 5 1,2,4
indicating the areas of registers banks, bit addressable RAM, general purpose RAM &
code memory.
14. With suitable illustration, discuss various addressing modes supported by 8051. 2 1,2,5
19. What is the difference between LJMP, SJMP, AJMP instructions in 8051? 5 1,2,5
1. What will be the contents of registers A & B and overflow flag after execution of the 2 1,2
following codes by the 8051:
MOV A, #0FEH
MOV B, #02H
MUL AB
i)A=FCH, B=01H, OV=1 iii)A=FCH, B=00H, OV=1
ii)A=FFH, B=01H, OV=1 iv)A=FCH, B=01H, OV=0
2. Determine the operation performed by the following codes in 8051: 2 1,2
MOV A, 90H
ORL A, 0A0H
i)OR the contents of port 1 and port 2 iii)OR the contents of A and port 2
ii)OR the contents of port 1 and A iv)OR the contents of A and immediate data
3. Write a program to obtain logical AND of (A) and any (SFR) and with a byte of data 5 1,2,5
indicated by the string
4. What is the addressing mode that is suitable for look up table access in 8051? 5 1,2,5
5. State the addressing mode used in each of the following instructions: 5 1,2,5
i) MOV A, #0ADH ii) MOVX @DPTR, A iii) ORL 34H, #34H iv) DEC R2
6. What would be the content of accumulator after executing the following sequence? 5 1,2,5
10. What do you mean by cache memory? How does it speed up the program execution? 5 6
Module: IV Advance Microcontroller
Bloom’s Taxonomy Level: I
Sl Questions Marks CO
No. No.
Sl Questions Marks CO
No. No.
3. Name two aspects in the design of ARM which has made it a processor with ‘low- 5 1
power dissipation’.
4. List out the important features that make ARM ideal for embedded applications. 5 1
5. Explain the function of the load and store instructions of ARM with examples. 5 1
Module: IV Advance Microcontroller
Bloom’s Taxonomy Level: III
Sl Questions Marks CO
No. No.
1. Now-a-days high performance embedded systems use either an RISC processor or a 5 1,2
processor with an RISC core with a code-optimized CISC instruction set. Why?
Explain.
3. Design the interfacing circuit to display different patterns of LEDs using ARM. 5 1,4