03 Intruction Exec

CS209 Computer Architecture
Instruction Execution(RTL)
Somanath Tripathy
IIT Patna
This Class
• Instruction Execution
– Micro operation
• Register Transfer Language (RTL)
Software Abstraction
int sum(int x, int y) 0x401040 <sum>: 0x55
{ 0x89
int t = x+y; C
0xe5
return t; 0x8b
} 0x45
_sum: 0x0c
assembly 0x03
pushl %ebp
movl %esp,%ebp 0x45
movl 12(%ebp),%eax 0x08
addl 8(%ebp),%eax 0x89
movl %ebp,%esp 0xec
popl %ebp machine 0x5d
ret code 0xc3
3
How to perform a Task?
• Task/ Program is a sequence of steps
– For each step, an arithmetic or logical operation is done
• For each operation, a different set of control signals is
needed
• Hardwired
– Connect to a particular hardware component
– Hardwired systems are inflexible
• Micro-program
– General purpose hardware can do different tasks, given
correct control signals
– Instead of re-wiring, supply a new set of control signals
Example of Program Execution
Ex. Let The processor has
a single data register AC
Let the PC content is 300
16-bit Instruction has 4-bit
opcode and 12-bit operand field
Let: Stored code

300: LDA [940], AX
ADD [941], AX
STA AX, [941]
Opcode meaning
0x1 Load AC from memory

0x2 Store AC to memory
0x5 Add AC and memory

ADD [941],AX
STA AX, [941]

Hardware Abstraction
CPU Memory
Addresss Instructions
PC MAR 0000
0001 I1
IR MBR
0002 I2
Acc IOAR 0003
IOBR
Decode&Exec
IO
Data
Buffers d1
-- d2
--
--
------
Different types of Actions
• Data Transfer
– processor-memory
– Processor I/O
• Data processing
– Arithmetic or logical operation on data
• Control
– Alteration of sequence of operations
– e.g. jump
• Combination of above
Register Transfer Language
• Digital systems are composed of modules
– constructed from digital components,
• registers, decoders, arithmetic elements, and control logic
• MICROOPERATION:
– Elementary operation performed during a single clock pulse, on
the information stored in one or more registers
• operation ex.: shift, count, clear, load, add,...
RTL:
• A symbolic language for describing
the internal organization of digital
computers with
• The set of registers it contains
and their functions Registers ALU
• The sequence of (R) (f)
microoperations performed on
the binary information stored
• The control that initiates the
sequence of microoperations 1 clock cycle
RTL
• RTL:
– Can also be used to facilitate the design process of digital systems
Register Showing individual bits

R1 7 6 5 4 3 2 1 0
15 0 15 8 7 0
R2 PC(H) PC(L)
Representation of a transfer(parallel) R2  R1
Load
R2 Clock
n
R1
• The outputs of the source must have a path to the inputs of the destination
• The destination register has a parallel load capability
Hardware Implementation
Representation of a controlled(conditional) transfer P: R2  R1
Condition(p=1) which determines when the transfer is to occur
If (p=1) then (R2  R1)
Implementation of controlled transfer P: R2  R1
Control P Load
Block diagram R2 Clock
Circuit
n
R1
t t+1
Clock
Timing diagram
Load
Transfer occurs here
Bus and Memory Transfer
• Bus is a path(of a group of wires) over which
information is transferred, from any of several
sources to any of several destinations.
From a register to bus: BUS <- R
Register A Register B Register C Register D
Bus lines
Bus lines
From bus to a register : R <- BUS
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
z D0 D1 D2 D3
Select 2x4 E (enable)
w
Decoder
Memory Transfer
Memory Read
AR
unit Write
DR
Memory read micro-op: DR  M ( DR  M[AR] )

Memory write micro-op: M  DR ( M[AR]  DR )
Summary of Register Transfer Microoperations
A B Transfer content of reg. B into reg. A
AR  DR(N) Transfer content of N bits portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS  R1, Transfer content of R1 into bus A and, at the same time,
R2  ABUS transfer content of bus A into R2
M[AR] Memory word specified by reg. AR

DR  M[AR] Memory read operation: transfers content of
memory word specified by AR into DR
M[AR]  DR Memory write operation: transfers content of
DR into memory word specified by AR
Arithmetic Operation
• Four types of microoperations
– Register transfer microoperations
– Arithmetic microoperations
– Logic microoperations
– Shift microoperations
* Summary of Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
Instruction Cycle
• Instruction cycle constitutes of two steps:
• Fetch
• Execute
Fetch Cycle
• Program Counter (PC) holds address of next instruction to
fetch
• Processor fetches instruction from memory location
pointed to by PC
• Increment PC
– Unless specified.
• Load Instruction into Instruction Register (IR)
• Processor decodes instruction and

performs required actions
RTL:?
Instruction Cycle State Diagram
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CS209 Computer Architecture

Let: Stored code

0x1 Load AC from memory

0x5 Add AC and memory

STA AX, [941]

Register Showing individual bits

Implementation of controlled transfer P: R2  R1

Register A Register B Register C Register D

Memory read micro-op: DR  M ( DR  M[AR] )

M[AR] Memory word specified by reg. AR

* Summary of Arithmetic Micro-Operations

• Processor decodes instruction and

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