Practical 1

Aim: To Study And Perform Sampling Theorem And Reconstruction.

Theory:

The aim of any communication system is to transmit information from one

Location to another. In case of voice communication, this information will be
speech.

Signal sampling is a technique which can be used to transmit analog information. such as continuous
speech or data. It is a system in which continuous waveforms are sampled at regular intervals and hence
the information signal is transmitted only at sampling instants. This sampled signal is further used to
recover the original signal receiving end, only when the sampling is done frequently enough. It is very
necessary to follow sampling theorem (Nyquist criteria) while using signal sampling schemes to transmit
information.

Nyquist Criteria:

Sampling can be defined as measuring the value of an information signal at predetermined time intervals.
The rate at which the signal is sampled is known as the sampling rate or sampling frequency. It is the
major parameter which decides the quality of the reproduced signal. If the signal is sampled quite
frequently (whose limit is specified by Nyquist Criteria), then it can be reproduced exactly at the receiver
with no distortion

Nyquist Criteria defines (set limit) to sampling frequency used during transmission of any analog signal.
The sampling theorem (Nyquist criteria) states if the sampling rate in any pulse modulation system
exceeds twice the maximum signal frequency, the original signal can be reconstructed at the receiver with
minimal distortion

Pulse Amplitude Modulation:

Pulse amplitude modulation is a technique in which the characteristics of the pulse train that is varied is
its amplitude. As shown in figure I, the train of pulses (carrier signal) is applied to the controlling end of an
ideal switch and the modulating signal.

i.e. the information signal (to be modulated) is applied to the input end of the switch. Here the switch is
nothing but a multiplier which multiplies the two signals: the train of pulses and the information signal.
The resultant signal is the pulse train which is amplitude modulated with respect to the information signal.

Let the pulse amplitude varies from 0V to 1V and the information signal has an amplitude of 10Vp-p, the
information signal will appear at the output of the switch only at the instants for which the amplitude of
pulse is 1V. Thus, the signal will be in pulsed form and the amplitude of pulses will be equal to that of the
amplitude of information signal at that instant. As shown in figure 2.
PAM is an analog system because the amplitude of pulse can vary infinitely i.e. the levels is are not
discrete. When the switch is open, the voltage is zero; when switch is closed (a switch closes when IV
appear at controlling i/p) the output voltage is equal to the instantaneous signal voltage. The sample width
depends upon how long a switch remains closed.

Procedure:

 Connect ± 12V and ground to the indicated position on ST2151 trainer (Do not turn the supply on).

 Keep the Sampling Signal Selector Switch at Internal Signal position.

 Put the Duty Cycle Selector Switch at position 5 i e. adjust sampling signal’s duty cycle to 50%.

 Connect 1 KHz Sine wave output to Signal Input socket in Sampling Circuit. You can observe the
process of step-by-step generating sine wave signal from square wave of 1 KHz at TP3, TP4, TP5
and TP6 respectively.

 Time/Div. = 500u Volt/Div.

 Turn On the supply (Turning ‘On’ the supply will randomly select the sampling frequency).

 Select sampling frequency of 8 KIT2 by Sampling Frequency Selector Switch Pressed till 80 KHz
signal LED glows.

 Observe the sampled 1 KHz sine wave at and Sample Output (TP39) on oscilloscope. The display
shows 1 KHz sine wave being sampled at 8 KHz, so there are 8 samples for every cycle of the sine wave.

 Connect Sample Output to Fourth Order LPF Input. Observe the filtered output (TP48) on the
oscilloscope. The display shows the reconstructed 1 Khz sine wave.

 Similarly observe the sampled 1 KHz sine wave at and Sample and Hold Output (TP41) on
oscilloscope. The display shows 1 KHz sine wave being sampled and Hold signal at 8 KIIz.
  Connect Sample and Hold Output to Second Order LPF Input and observe the filtered output
(TP44) on oscilloscope. The display shows the reconstructed 1 Khz sine wave.

Time/Div. 50u
Volt/Div. = 1
Sampling Signal 8KHz (50%)

Conclusion:

From This Practical we study sampling theorm and Reconstruction in pulse amplitude
Modulation.

Practical 2

Aim: To Understand And The Concept Of Pulse Code Modulation And To Observe The Performance Of
PCM System.
Steps in Pulse Cole Modulation:

Sampling:

The signals which are required to be transmitted as information is known as information signal and in the
case of voice communication this will be a continuously changing signal communing speech information.
The aim of the kit is to transmit the signals in digital form and is to reproduce this information signal in
analog form at the receiving end of the communication system with the help of sampling and
reconstruction trainer.

In the exercises to follow. You will simulate audio signal by a 1 KIIz test signal provided On board. The
repetitive, non-changing waveform does not contain information. Provided the frequency of the test-signal
lies within the frequency range which an information signal will occupy, a test signal of this type can be
extremely helpful in system analysis and testing.

The voice signals are limited to the range 300 Hz to 3.4 KHz, a 1 KHz frequency fits conveniently in this
range and can be used to demonstrate and test many techniques used in communication system.

Theory of sampling:

The signals we use in the real world, such as our voice, are called “analog” signals. To process these signals
for digital communication, we need to convert analog signals to “digital” form While an analog signal is
continuous in both time and amplitude, a digital signal is discrete in both time and amplitude. To convert
continuous time signal to discrete time signal, a process is used called as sampling. The value of the signal
is measured at certain intervals in time. Each measurement is referred to as a sample.

Principle of sampling:

Consider an analogue signal x(t) that can be viewed as a continuous function of time, as shown in figure 3.
Figure 4 depicts the sampling of a signal at regular interval (period) t=nTs where n is an integer. The
sampling signal is a regular sequence of narrow pulses δ(1) of amplitude 1.Figure 5 shows the sampled
output of narrow pulses δ(1) at regular interval of time.
Figure 2.2
Procedure:

a) Initial set up for trainer ST2103:

Mode Switch Position

FAST position Function generator setting

DC1& DC 2 amplitude controls: Fully

Clockwise direction. I KHz & 2 KHz signal levels :10

V peak-peak.

Pseudo random sync code generator switch :OFF position

Error check code selector switches A & B: A=0 & B=0

Position (Off Mode)

All switched faults :OFF position

1. Connect on ST2103: as shown in figure 2.1

DC I output to CH 0 input

DC 2 output to CH1 input

2. Turn On the power. With the help of digital voltmeter/ oscilloscope, adjust the DC 1 amplitude
control until the DC 1 output measures OV The accuracy should be within +/-20mV. Turn the DC
2 amplitude control, fully counter clockwise.
3. Observe the output on the A/D converter block LEDs (D0 to D6).
4. Turn the DC I control fully anti-clockwise and repeat the above procedure by varying DC 2
control. Check that the digital code for the Set voltage value is identical to that of the DC I
setting.
Once again take the precaution of maintaining the set input within +/- 20mV range of the
specified voltage.
5. Switch ‘Off the trainer. Disconnect the DC 1 & DC 2 supply from CH 0 & CH1. Connect~1 KHz
signal to CH 0 & 2 KHz signal to CH1 input as shown in figure 2.2.
6. Trigger the dual trace oscilloscope externally by the CHI signal available at TP12. Observe the
signal at CH 0 & CH I sample output (TP5) with reference to the SC Signal (TP7) on the second
trace. Give a special attention to the phase relation between the two signals.
 7. Now connect the oscilloscope channel 1 to CH 1 sample (TP6) sketch the three waveforms with
utmost importance to the relationship between the three waveforms.
8. Connect oscilloscope channel 1 input to SC test points (TP7) & oscilloscope channel 2 input to
EC test point (TP8).
Observe the phase relation between the two SC & EC test point. Notice that EC goes high at the
end of conversion & remains latched until next SC Pulse.

conclusion: From this Practical we understood concept of pcm and observe the performance of pcm
system and its connection.
 Practical 3

Objective: Study of Time Division Multiplexing

Equipment required:

1. ST2103 timer with power supply cord

2. Oscilloscope with connecting probe
3. Connection cords

Procedure:

A. Initial set up for

trainer ST2103:

Mode Switch
Position

FAST position
Function generator
setting:

DC1 & DC 2
amplitude
controls : fully

Clock wise
direction. 1KHz &
2KHz signal levels :
10

V peak-peak

Pseudo random sync code generator switch : OFF position

Error check code selector switches A & B : A=0 & B=0

Position (‘Off Mode).

All switched faults : OFF position.

 1. Connect the 1KHz output to CHI D
2. Turn on the power supply and oscilloscope. Check that the PAM output of 1KHz sine wave is
available at TP15 of the ST2103.
3. Connect channel 1 of the oscilloscope to TP10 & channel 2 of the oscilloscope to TP15. Observe the
timing &phase relation between the sampling signal TP10 & the sampled wave form at TP15.
4. Turn off the power supply. Now connect also the 2KHz supply to CH1.
5. Connect channel 1 of the oscilloscope to TP12 & channel 2 of the oscilloscope to TP15.
6. Observe & explain the timing relation between the signals at TP10,5,6,12&15.

Conclusion: from this practical we study how to connect the TDM pulse modulation transmission.

Practical-4

Aim: to understand the concept of delta modulation and to chieve the achieve the delta modulation & de-
modulation.

Theory:
Delta modulation is a system of digital modulation developed after pulse code modulation. In this system
at each sampling time. Say the Kth sampling time, the difference between the sample value at sampling
time k and the sampling time K and the sample value at the previous sampling time (k-1) is encoded into
just a single but, i.e. at each sampling time we ask simple question.
Has the signal amplitude increased or decreased since the last sample was taken?
If signal amplitude has increased, then modulator’s output is at logic level 1. If the signal amplitude has
Decreased, the modulator output is at logic level 0.
Thus, the output from the modulator is a series of zeros and ones to indicate rise and fall of the waveform
Since the previous value. One way in which delta modulator and demodulator is assembled is as show In
figure 1 and figure 2.

The Delta Modulator Works as follows

The analog signal which is to be encoded into digital data is applied to the +ve input of the voltage
comparator which compares it with the signal applied to its -ve input from the integrator output (more
about this signal in forth coming paragraph).

The comparator’s output is logic ‘0’ or ‘l’ depending on whether the input signal at +ve terminal is lower or
greater then the-ve terminals input signal.
The comparator’s output is then latched into a D-flip-flop which is clocked by the transmitter clock. Thus,
the output of D-flip-Flop is a latched ‘1’ or ‘0’ synchronous with the transmitter clock edge.

This binary data stream is transmitted to receiver and is also fed to the unipolar to bipolar converter. This
block converts logic ‘0’ to voltage level of +4V and logic ‘1’ to voltage level-4V.

The Bipolar output is applied to the integrator whose output is as follows:

a) Rising linear ramp signal when -4V is applied to it, (corresponding to binary 1)
b) Falling linear ramp signal when +4V is applied to it (corresponding to binary 0)

The integrator output is then connected to the -ve terminal of voltage comparator, thus completing the
modulator circuit.

Procedure:
1. Connect the mains supply
2. Make connection on the board as shown in the figure 7
3. Ensure that the clock frequency selector block switches A & B are in A = 0 and B = 0 position
4. Ensure that integrator 1 block’s switches are in following position:
a) Gain control switch in left-hand position (towards switch A & B).
b) Switches A & B in A=0 and B-0 positions.
5. Ensure that the switches in integrator 2 blocks are in following position:
a) Gain control switch in left-hand position (towards switch A & B)
b) Switches A & B are in A=0 & B=0 positions.
6. Turn ON of the trainer.
7. In order to ensure for correct operation of the system. we first take the input to 0V So connect the
‘+’ input of the delta modulator’s voltage comparator to OV and monitor on an oscilloscope the
output of integrator (TP17) and the output of the transmitter’s level changer (TP15).
 If the transmitter’s level changer output has equal positive and negative output levels. Integrator’s
output will be a triangle wave centered around ‘0’ Volts, as shown in figure 6 (Case A). However, if
the level changer’s negative level is greater than the positive level, the integrator’s output will
appear as shown in figure 6 (Case B). Should the level changer’s positive output level be the greater
of the two levels, the integrator’s output will resemble that shown in figure 6 (Case C).

8. The relative amplitudes of the level changer’s positive and negative output levels can be varied by
adjusting the level adjust present in the bistable and level changer circuit 1 block when it is turned
anticlockwise, the negative level increases relative to the positive level, when turned clockwise, the
positive level increases relative to the negative.

Prove that you can obtain all the three waveforms shown in figure 6 by turning the potentiometer
from one extreme to another Try explaining the reason behind it.

9. Adjust the transmitter’s level change present until the output of integrator 1 (TP17) is a triangle
wave centerd around 0 Volts, as shown in figure 6 (Case A). The peak to peak amplitude of the
signal wave at the integration’s output should be 0.5V (approximately), thus amplitude is known as
the integrator Step size.

The output from the transmitter’s bistable circuit (TP14) will now be a stream of alternate ‘l’ and
‘0’, ‘s’ this is also the output of the delta modulator itself. The delta modulator is now said to be
‘balanced’ for correct operation.

10. Examine the signal at the output of integrator 2 (TP47) at the receiver. This should be a triangle
wave, with step size equal to that of integrator 1, and ideally centre around 0 Volts. If there is any
DC bias at the output of integrator 2, remove it by adjusting the receiver’s level adjust present (in
the bistable & level changer circuit 2 block). This present adjusts the relative amplitudes if the
positive and negative output levels from the receiver’s level changer circuit only when these levels
are balanced will there be no offset at the output of integrator2.
 The receiver’s low pass filter (whose cut off frequency is 3.4 KHz.) then filters output the higher-
frequency triangle wave, to leave a DC level at the filters output (TP51). If the receiver’s level adjust
present has been adjusted correctly, this DC level. Will be ‘0’ a volt, the delta demodulator is now
also balanced for correct operation.

11. Disconnect the voltage comparators input from OV and reconnect it to the 250Hz output from the
function generator block: the modulator’s anallog input signal is now a 250Hz sine wave.
Monitor this analog signal at the voltage comparator’s input TP9 trigger the scope on this signal
together with the output of, integrator 1 (TP17) Note how the output of the transmitter’ integrator
follows the analog input, as was illustrated in figure 1.
Note: It may be necessary to readjust slightly the transmitter’s level adjust present (in the bistable
& level changer circuit 1 block) in order to obtain a stable, repeatable trace of the integrator’s
output signal.

12. Display the data of the transmitter’s bistable (at TP14), together with the analog input at TP9 (again
trigger on this signal), and note that the 250Hz sine wave has effectively been encoded into a
stream of data bits at the bistable’s output, ready for transmission to the receiver.

13. For a full understanding of how the delta modulator is working, examine the output of the voltage
comparator (TP11), the bistable’s clock input (TP13), and the level changer’s bipolar output
(TP15).

14. Display the output of integrator 1 (TP17) and that of integrator 2 (TP47) on the scope. Note that the
two signals are very similar in appearance, showing that the demodulator is working as expected.

15. Display the output of integrator 2 (TP47) together with the output of the receiver’s low pass filter
block (TP51) Note that although the integrator’s output has been smoothed out somewhat by the
 low pass filter, some unwanted ripple still remains at filter’s output This ripple’ is due to
quantization noise at the integrator’s output. Which is caused by the relatively large integrator step
size. This step size can be reduced by increasing the rate at which the system is clocked (i.e. The
sampling frequency), since this reduces the sampling period, and hence the time available between
samples for the integrators to charges up and down.

16. The current system clock frequency is 32 KHz. This is set by the A, B switches in the clock frequency
selector block, which are currently in the A=0. B=0 positions. While monitoring the same signals,
increase the system clock frequency to 64KHz, by putting the switches in the A=0, B=1 positions.

Note: If the integrator’s output (TP47) no longer gives a stable trace after changing the clock
frequency, make a slight adjustment to the transmitter’s level adjust preset (in the bistable & level
changer circuit I block), until the trace is once again stable.
Notice that, at the integrator’s (TP47), the frequency of the triangular error signal doubles, and the
peak-to-peak amplitude of that error signal (i.e. the step size) is now halved.
Examine the ripple at the low-pass filter’s output (TP51). Note that this is now less than it was
before.

17. By changing the system clock frequency to first 128KHz (clock frequency selector switches in A=1,
B=0 positions), and then to 256KHz (switches in A=1, B=0 positions), note the improvement in the
low-pass filter’s output signal (TP51).
Once again, it may be necessary to adjust slightly the transmitter’s level adjust preset, in order to
obtain a stable oscilloscope trace.

18. Using a system clock, frequency of 256KHz (which gives a step size of approximately 60mV).
Compare the low pass filter’s output (TP51) with the origin analog input (119) There should now
be no noticeable difference between them, other than a slight delay.

19. While continue to monitor the transmitter’s malay input (P9) and the receive’s low-pass filter
output (PS1), discour the comparator’s Comput from the 25011/ sine wave output, and reconnect
at me the 500112.1 KHz and 2 KIZ utpots turn. Note that, as the frequency of the analog signal
increases, so the low pas filter’s output becomes more distorted and reduced in amplitude.

20. In order to understand what has caused this distortion, leave the comparator’s input connected to
the 2KHz sine wave output of the function generator, and examine the output of integrator 2
(TP47). Note that the integrator’s output is no longer an approximation to the analog input signal,
but is instead somewhat triangular in shape.

Compare this with the output of integrator 1 (TP17), and note that the two signals are exactly the
same, the problem obviously starts in the delta modulator circuit.

21. Compare the 2KHz analog input signal (TP9) with the output of integrator 1 (TP17) it should now
become clear what has happened.

The analog signal is now changing so quickly that the integrator’s output cannot ramp fast enough
to ‘catch up’ with it, and the result is known as ‘slope overloading.’
22. Although the system clock frequency i.e. the sampling frequency determines how often the
integrator’s output direction (up or down) can change, it does not affect how quickly the
integrator’s output can ramp up and down. Consequently, changing the system clock frequency will
not help the slope overload problem, prove this by changing the clock frequency selector switches,
and noting that the problem is still present. Return the switches to the A= 1, B=1 (256KHz clock
frequency) position before continuing.

23. If slope overloading is to be avoided in a practical delta modulation system, the transmitter
integrator must be able to ramp up or down at a rate which is at least as great as the maximum rate
of change at the transmitter’s analog input. If the incoming analog signal is a sine wave, its
maximum rate of change occurs at the zero crossing point, and is proportional to both the
frequency and the amplitude of the sine wave.

Hence, the likelihood of slope overloading can be reduced by either reducing the maximum input
frequency, or by reducing the maximum input amplitude to the delta modulator. We have already
seen how slope overloading can be avoided by reducing the frequency of the analog input signal
since there was no problem with the ~ 250 Hz analog inputs. Now check that the problem can also
be avoided if the amplitude of the input signal is reduced, do this by slowly turning the -2KHz
preset anticlockwise.
Note that there comes a time when the integrator’s output can once again follow analog input
signal.

24. Another possible way of overcoming slope overloading is to increase the gain of the integrators so
that they can ramp up and down faster, and so follow even those analog input waveforms that
change very quickly.

To illustrate this, first return the 2 KHz preset to its clock wise (maximum amplitude) position, so
that slope overloading can once again be seen on the scope.

In each of the two integrator blocks, there are two red switches labeled A and B. The 2bit binary
code produced by these switches selects one of four integrator gains, the lowest gain selected when
the switches are in the A=0 & B=O positions. For each increasing step in the switch code from
A=0,B=0 to A=1,B=1. The integrator gain is doubled.

Change the codes produced by the switches (in both integrator 1 and integrator 2 blocks) from A=0,
B=0 to A=1, B=1, to double the gain of the two integrators; note that slope overloading still occurs.

Then change both sets of switches to the A=1, B=0 position, and finally to the A=1, B=1, position, to
show that slope overloading can be eliminated if the integrator gain is large enough. Once again, it
may be necessary to make a slight adjustment to the transmitter’s level adjust pressed, in order to
obtain a stable trace on oscilloscope.

Note that, although it is the gain of integrator 1 alone which determines whether or not slope
overloading will occur, integrator 2 must have the same gain if the amplitude of the demodulator’s
analog output is to be equal in amplitude to the modulator’s analog input.
 25. We have observed slope over loading can be overcome by changing anyone of the three following
options:
a) Reducing the maximum input frequency to the delta modulator.
b) Reducing the maximum input amplitude, or
c) Increasing the integrator gain.

Conclusion: From this experiment we are study that we understood that the concept of Delta modulation
& De-modulation and also understood Wire Connection.

Praction-5

Aim: To study the performance of an

Theory:
As it has been seen, delta modulation system is unable to chase the rapidly Changing information of the
analog signal, which gives rise to distortion & hence poor quality reception. This is known as slope
overloading phenomenon. The problem can be overcome by increasing the integrator gain (i.e. step-size).
But using high step-size integrator would lead to a high quantization noise.

Quantization Noise:

It is defined as error introduced between the original signal, & the quantized signal due to the fixed step
size in which the signal (quantized) is incremented. As the error is random in nature & hence
unpredictable, it can be treated as noise High quantization noise may play havoc on small amplitude
signals. The solution to this problem is to increase the integrator gain for fast-changing input & to use
normal gain for small amplitude signals.

The basic idea is to increase the integrator the integrator gain (it is doubled on this trainer) when slope
overload occurs. If still it is unable to catch up with the signal, the integrator gain is doubled again. The
integrator on board has four available gains standard, standard X2, standard X4, and standard X8. The
integrator thus adopts it self to the gain where its lowest value can just overcome the slope overloading
effect. See figure 8.
Functionally, the adaptive delta modulator/demodulator is shown in figure 9 & figure 10. As it can be
observed, the adaptive delta modulator is similar to the delta modulator except for few blocks namely the
counter & the control circuit.

The input to the control circuit is the latched data from the D Flip-Flop. The counter is reset whenever
‘high’ appears at the output of the control circuit. Both the counter & the control circuit are clocked by the
same TX clock. The input to the integrator from the counter is a two-bit control word, which controls the
gain of the integrator. When the output of counter is ‘00’ the gain is lowest (standard) where as it is
highest (standard X8) for counters output ‘1 I’.
Procedure:

1. Connect the mains supply.

2. Connect the board as per figure 11.

3. Ensure that the clock frequency selector switches A & B are in A=0 & B=0 position.

4. Ensure that the switches in TX. Integrator gain control block are in following positions.
a) Gain control switch at the L.H.S. position. (towards switches A & B)
b) Switches A & B in position A=0 & B=0.

5. Ensure that the switches in receiver’s integrator gain control block are in following positions:

a) Gain control switches at the R.H.S. position. (towards switches A & B)

b) Switches A & B in Position A=0 & B=0.
6. Turn all the potentiometers of function, generator block namely 250Hz to 2KHz then fully clockwise
positions.
7. Turn ON the supply

8. As the gain control switch is towards A & B switches the gain setting is still manual, connect the
voltage comparator’s +ve input to 0V & check whether the modulator & demodulator are balanced
for correct operation as in delta modulation experimentation.

Change the clock frequency selector switches to the A=1, B=1, positions (256KHz Clock Frequency)
before continuing.

9. Disconnect the voltage comparators ‘+’ input from OV and reconnect it to the 2KHz output from the
function generator block.

10. Monitor the 2KHz analog input at TP9 and the output of integrator 1 at TP17. Note that slope
overloading is still occurring, as indicated by the fact that the integrator’s output is not an
approximation of the analog input signal.

11. At the transmitter, move the slider of the gain control switch in the integrator 1 block to the right-
hand position (towards the sockets labeled A, B). At the receiver, move the slider of the gain control
switch in the integrator 2 blocks to the left-hand position (again towards the sockets labeled A, B)
The gain of each integrator is now controlled by the outputs of the counter connected to it
Functionally, the transmitter and receiver are now configured as shown in the figure 9 & 10 e as
adaptive delta modulator and demodulator respectively.

12. Once again examine the 2KHz analog input at TP9 and the output of integrator at TP17, noting that
the slope overloading problem has been eliminated, and that the integrator’s output once again
follows the analog input signal. Again, it may be necessary to adjust slightly the transmitter’s level
adjust preset, in order to obtain a stable trace of the integrator’s output signal.

13. Compare the output of integrator 1 (TP17) with that of integrator 2 (TP47), noting that, as
expected, both are identical in appearance.

14. Examine the output of the low pass filter (TP51) and the output of integrator 2 (TP47). The filter
has removed the high-frequency components from the integrator’s output signal, to leave goods,
clean 2KHz sine wave.

15. Compare the original 2KHz analog input signal (at TP9) with the output signal from the receiver’s
low pass filter (at TP47).
Note that the demodulator’s output signal is equal in amplitude to the modulator’s input signal, but
is delayed somewhat.

16. Disconnect the voltage comparator’s ‘+’ input from the 2 KHz function generator Output, and
reconnected it in turn to the 1KHz, 500Hz and 250Hz outputs, noting in each case that the
demodulator’s output signal is identical to the modulator’s input signal, but delayed in time.

17. The adaptive delta modulator/demodulator system has therefore eliminated any slope overloading
problems. To examine in detail how it does this, reconnect the voltage comparator’s input to the
 function generator’s 2KHz output, then reduce the system clock (i.e. sampling) frequency to 32KHz,
by putting the clock frequency selector switches in the A=0, B=0positions.
Although a 32KHz sampling frequency is too low to ensure that an undistorted output is obtained
from the demodulator’s low pass filter, it does increase the step size to a level, which makes it
easier to understand how the system is operating.

18. Monitor the 2KHz analog input signal at TP9 and at the output of integrator (TP17) should now
become a little clearer as to how the adaptive delta modulator is operate It will be noted that the
slope of the integrator’s output signal is no longer constant, but increases in a series of discrete
steps, in order to ‘catch up with the fast-changing analog input signal.
If the integrator output does not ‘catch up’ with the analog input within two clock periods of its
direction changing, the slope of the integrator’s output signal. (i.e. The integrator gain) is doubled. If
it has still not caught up with the analog input signal by the end of the third clock period, the
integrator gain will once again be doubled. If the integrator output still lags behind at the end of the
fourth clock period, the integrator’s gain is doubled once again, to its maximum value. It then
remains at this value until the integrator output ‘catches up’ with the analog input signal. Once the
integrators output ‘overtakes’ the analog input signal, its direction changes, and its rate of change
reverts to the minimum value.

19. Examine also the test points in the adaptive control circuit 1 block (TP20-24), to ensure you have a
complete understanding of how the adaptive delta modulator is operating.

20. While monitoring the outputs of the modulator’s binary counter (TP21 and 22), slowly turn the
2KHz preset anticlockwise, in order to reduce the amplitude of the 2KHz analog input signal. Notice
that once the analog input signal becomes small enough, both the counter’s outputs becomes
permanently low, causing the integrator to have minimum gain. This happens because the input
 signal is now so small that the integrator can always follow it, even with minimum gain

Conclusion: from this practical we are study that how can work an adoptive delta modulation circuits
 Practical-6

Aim: To sandy and perform PAM

Pulse Amplitude Modulation:

Must digital modulation systems are based on pulse modulation. It involves variation of a pulse parameter
in accordance with the instantaneous value of the information signal. This parameter can be amplitude,
width, repetitive frequency etc.

Depending upon the nature of parameter varied, various modulation systems are used. Pulse amplitude
modulation, pulse width modulation. Pulse code modulation are few modulation systems cropping up
from the pulse modulation technique. In pulse amplitude modulation (PAM) the amplitude of the pulses
are vaned in accordance with the modulating signal.

In true sense, pulse amplitude modulation is analog in nature but it forms the basis of most digital
communication and modulation systems. The pulse modulation systems require analog information to be
sampled at predetermined intervals of time Sampling is a process of taking the instantaneous value of the
analog information at a predetermined time interval.

A sampled signal consists of a train of pulses, where each pulse corresponds to the amplitude of the signal
at the corresponding sampling time. The signal sent to line is modulated in amplitude and hence the name
Pulse Amplitude Modulation (PAM).

Pulse amplitude modulation, the simplest form of pulse modulation, is illustrated in Figure 11. It forms an
excellent introduction to pulse modulation in general. Pulse amplitude modulation is a pulse modulation
system in which the signal is sampled at regular intervals, and each sample is made proportional to the
amplitude of the signal at the instant of sampling. As shown in Figure 11. The two types are double
polarity pulse amplitude modulation, which is self-explanatory and single polarity pulse amplitude
modulation, in which a fixed DC level is added to the signal, to ensure that the pulses are always positive.
As will be seen shortly, the ability to use constant- amplitude pulses is a major advantage of pulse
modulation, and since Pulse Amplitude Modulation does not utilize.
1. Pulse Amplitude Modulation (PAM):
In pulse amplitude modulation system the amplitude of the pulse is varied in accordance with the
instantaneous level of the modulating signal. Now days, the PAM system is not generally used, but it
forms the first stage of the other types of pulse modulation.

2. Pulse Width Modulation (PWM):

In PWM system the width of the pulse is varied in accordance with the instantaneous level of the
modulating signal.

3. Pulse Position Modulation (PPM):

In PPM System, the position of the pulse relative to the zero reference level is varied in accordance
with the instantaneous level of the modulating signal.

4. Pulse Code Modulation (PCM):

In PCM System the amplitude of the sampled waveform at definite time intervals is represented as a
binary code. The first three techniques of the above described systems are not truly digital but in
fact are analog in nature. The very fact that the variation of a particular pulse parameter is
continuous rather than being in the diserete step makes the system analog in nature.
As a result of this, the PAM signals are vulnerable to noise & dispersion of the pulse. The channel
introduces noise on the signal from various sources. Also the receiver is not noise free.

Equipment Required:

1. ST2110 with power supply cord

2. CRO with connecting probe
3. Connecting cords

Procedure:
 1. Connect the circuit as shown in Figure 11.
a) Output of sine wave to modulation signal input in PAM block keeping the switch in 1KHz
position.
b) 8KHz pulse output to pulse nput.

2. Switch On’ the power supply & oscilloscope.

3. Observe the outputs at TP(3 & 5) these are natural & flat top outputs respectively.

4. Observe the difference between the two outputs.

5. Vary the amplitude potentiometer and frequency change over switch & observe the effect on the
two outputs.

6. Vary the frequency of pulse, by connecting the pulse input to the 4 frequencies available i.e. 8, 16,
32, 64 kHz in Pulse output block.

7. Switch ‘On’ fault No. 1, 2, 3, 4 one by one & observe their effect on Pulse Amplitude Modulation
output and try to locate them.

8. Switch ‘Off the power supply.

Conclusion: from this practical we are study that now can work pulse amplitude modulating.
 Practical – 7

Aim: To study and perform PPM.

Equipment Required:

1. ST2110 with power supply cord

2. CRO with connecting probe
3. Connecting cords

Connection Block Diagram

Procedure:

1. Connect the circuit as shown in Figure 4.1 and also described below for clarity.
a. Connect the DC output to input of PPM block.

2. Switch ‘On’ the power supply & oscilloscope.

3. Observe the output of PPM block at TP7.

4. Vary the DC output while observing the output of PPM block.

 5. Switch ‘On’ the switched faults No. 1, 2, & 6 one by one & observe their effects PPM input and try to
locate them.

6. Switch ‘Off the power supply.

Conclusion: from this practical we are study that how can work PPM and how can connecting that probe
with CRO.
 Practical-8

Aim: Study of PWM using different Sampling Frequency.

Equipment Required:

1. ST110 with power supply cord

2. CRO with connecting probe
3. Connecting cords

Procedure:

1. Connect the circuit as shown in Figure 7.1 and also described below for clarity.
a. 1KHz sine wave output of function generator block to modulation input of PWM block.
b. 64KHz square wave output to pulse input of PWM block.

2. Switch “On’ the power supply & oscilloscope.

3. Observe the output of PWM block.

4. Vary the amplitude of sine wave and see its effect on pulse output.

5. Vary the sine wave frequency by switching the frequency selector switch to 2KHz.
 6. Also, change the frequency of the pulse by connecting the pulse input to different pulse frequencies
viz. 8KHz, 16KHz, 32KHz and see the PWM output.

Conclusion: from this practical we study that how can work different sampling frequency using pulse
width modulation.
 Practical – 9

Aim: To generate and demodulate amplitude shift keyed (ASK) signal using MATLAB

Theory:

Generation of ASK:

Amplitude shift keying ASK is a modulation process, which imparts to a sinusoid two or more discrete
amplitude levels. These are related to the number of levels adopted by the digital message. For a binary
message sequence there are two levels, one of which is typically zero. The data rate is a sub-multiple of the
carrier frequency. This the modulated waveform consists of bursts of a sinusoid One of the disadvantages
of ASK. Compared with FSK and PSK, for example, is that it has not got a constant envelope. This makes its
processing (eg. power amplification) more difficult, smee linearity becomes an important factor. However,
it does make for ease of demodulation with an envelope detector.

Demodulation:

ASK signal has a well defined envelope. Thus it is amenable to demodulation by an envelope detector.
Some sort of decision-making circuitry is necessary for detecting the message. The signa recovered by
using a correlator and decision making circuitry is used to recover the binary sequence.

Algorithm Initialization commands ASK modulation:

1. Generate carrier signal

2. Start FOR loop
3. Generate binary data, message signal(on-off form)
4. Generate ASK modulated signal.
5. Plot message signal and ASK modulated signal.
6. End FOR loop.
7. Plot the binary data and carrier.

ASK demodulation:

1. Start FOR loop

2. Perform correlation of ASK signal with carrier to get decision variable.
3. Make decision to get demodulated binary data. If x>0, choose ‘1’ else choose “0”
4. Plot the demodulated binary data
Program:

%ASK Modulation

%ASK Modulation

clc; clear all; close all;

%GENERATE CARRIER SIGNAL Tb=1; fc=10;
t=0:Tb/100:1;
c=sqrt(2/Tb)*sin(2*pi*fc*t);
%generate message signal N=8;
m=rand(1,N); t1=0;t2=Tb for i=1:N
t=[t1:.01:t2]
if m(i)>0.5 m(i)=1;
m_s=ones(1,length(t)); else
m(i)=0;
m_s=zeros(1,length(t)); end
message(i,:)=m_s;
%product of carrier and message ask_sig(i,:)=c.*m_s; t1=t1+(Tb+.01); t2=t2+(Tb+.01);
%plot the message and ASK signal subplot(5,1,2);axis([0 N -2 2]);plot(t,message(i,:),'r');
title('message signal');xlabel('t--->');ylabel('m(t)');grid on hold on
subplot(5,1,4);plot(t,ask_sig(i,:));
title('ASK signal');xlabel('t--->');ylabel('s(t)');grid on hold on
end hold off
%Plot the carrier signal and input binary data subplot(5,1,3);plot(t,c);
title('carrier signal');xlabel('t--->');ylabel('c(t)');grid on subplot(5,1,1);stem(m);
title('binary data bits');xlabel('n--->');ylabel('b(n)');grid on

% ASK Demodulation
t1=0;t2=Tb for i=1:N
t=[t1:Tb/100:t2]
%correlator x=sum(c.*ask_sig(i,:));
%decision device if x>0
demod(i)=1; else
demod(i)=0; end t1=t1+(Tb+.01); t2=t2+(Tb+.01);
end
%plot demodulated binary data bits subplot(5,1,5);stem(demod);
title('ASK demodulated signal'); xlabel('n--->');ylabel('b(n)');grid on
SNPIT&RC, UMARAKH ELECTRONICS AND COMMUNICATION

Model Graphs:

conclusion: from this practical we study that how can work use signal using matlab

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Practical – 10

Aim: To generate and demodulate phase shift keyed (PSK) signal using MATLAB

Generation of PSK signal

PSK is a digital modulation scheme that conveys data by changing, or modulating, the
phase of a reference signal (the carrier wave). PSK uses a finite number of phases, each
assigned a unique pattern of binary digits. Usually, each phase encodes an equal number
of bits. Each pattern of bits forms the symbol that is represented by the particular
phase. The demodulator, which is designed specifically for the symbol-set used by the
modulator, determines the phase of the received signal and maps it back to the symbol
it represents, thus recovering the original data.

In a coherent binary PSK system, the pair of signal Si(t) and S. (t) used to represent
binary symbols 1 & 0 are defined by

S. (1) 2E/ T. Cos 2aft

S: (t)=√2E/T (2+)=√2E/Th Cos 2nft

Where 0 ≤t Th and Eb – Transmitted signed energy

For bit
The carrier frequency fc =n/Tb for some fixed integer n.

Antipodal Signal:

The pair of sinusoidal waves that differ only in a relative phase shift of 180° are called
antipodal signals.

BPSK Transmitter

The input binary symbols are represented in polar form with symbols I &0 represented
by constant amplitude levels VEb & -VEb. This binary wave is multiplied by a sinusoidal
carrier in a product modulator. The result in a BSPK signal.

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SNPIT&RC, UMARAKH ELECTRONICS AND COMMUNICATION

The received BPSK signal is applied to a correlator which is also supplied with a locally
generated reference signal e) (1). The correlated o’p is compared with a threshold of
zero volts. If x 0, the receiver decides in favour of symbol 1. Ifx< 0, it decides in favour of
symbol 0.

Algorithm Initialization commands PSK modulation

 Generate carrier signal.

 Start FOR loop

 Generate binary data, message signal in polar form

 Generate PSK modulated signal

 Plot message signal and PSK modulated signal.

 End FOR loop.

 Plot the binary data and carrier.

PSK demodulation:

 Start FOR loop Perform correlation of PSK signal with carrier to get decision
variable 2. Make decision to get demodulated binary data. If x>0, choose ‘I’ else
choose ‘0’ Plot the demodulated binary data

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SNPIT&RC, UMARAKH ELECTRONICS AND COMMUNICATION

Program:

% PSK modulation

clc; clear all; close all;

%GENERATE CARRIER SIGNAL Tb=1;
t=0:Tb/100:Tb;
fc=2; c=sqrt(2/Tb)*sin(2*pi*fc*t);
%generate message signal N=8;
m=rand(1,N); t1=0;t2=Tb for i=1:N
t=[t1:.01:t2]
if m(i)>0.5 m(i)=1;
m_s=ones(1,length(t)); else
m(i)=0;
m_s=-1*ones(1,length(t)); end
message(i,:)=m_s;
%product of carrier and message signal bpsk_sig(i,:)=c.*m_s;
%Plot the message and BPSK modulated signal subplot(5,1,2);axis([0 N -2
2]);plot(t,message(i,:),'r');
title('message signal(POLAR form)');xlabel('t--->');ylabel('m(t)'); grid on; hold on;
subplot(5,1,4);plot(t,bpsk_sig(i,:)); title('BPSK signal');xlabel('t--->');ylabel('s(t)'); grid
on; hold on;
t1=t1+1.01; t2=t2+1.01;
end hold off
%plot the input binary data and carrier signal subplot(5,1,1);stem(m);
title('binary data bits');xlabel('n--->');ylabel('b(n)'); grid on;
subplot(5,1,3);plot(t,c);
title('carrier signal');xlabel('t--->');ylabel('c(t)'); grid on;

% PSK Demodulation

t1=0;t2=Tb for i=1:N t=[t1:.01:t2]

%correlator x=sum(c.*bpsk_sig(i,:));
%decision device if x>0
demod(i)=1; else
demod(i)=0; end t1=t1+1.01; t2=t2+1.01;
end
%plot the demodulated data bits subplot(5,1,5);stem(demod);
title('demodulated data');xlabel('n--->');ylabel('b(n)'); grid on

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Conclusion:From this pratical we study that now can work psk signal using MATLAB.

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