Xilinx XC2C256-6FT256C - Consumer Electronics - Medical Equipment
Xilinx XC2C256-6FT256C - Consumer Electronics - Medical Equipment
Xilinx XC2C256-6FT256C - Consumer Electronics - Medical Equipment
-5G Technology
-Cloud Computing
-Wireless Technology
-Industrial Control
-Artificial Intelligence
-Medical Equipment
-Internet of Things
-Consumer Electronics
The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O
standards (see Table 1). This XC2C256-6FT256C device is also 1.5V I/O compatible
with the use of Schmitt-trigger inputs. The XC2C256-6FT256C device is designed for
both high performance and low power applications. This lends power savings to
high-end communication equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall system reliability is
improved
This XC2C256-6FT256C device consists of eight Function Blocks inter-connected by
a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and
complement inputs to each Function Block. The Function Blocks consist of a 40 by
56 P-term PLA and 16 macrocells which contain numerous configuration bits that
allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T
flip-flop or as a D latch. There are also multiple clock signals, both global and local
product term types, configured on a per macrocell basis. Output pin configurations
include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A
Schmitt-trigger input is available on a per input pin basis. In addition to storing
macrocell output states, the macrocell registers may be configured as direct input
registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis. Three global clocks are
available for all Function Blocks as a synchronous clock source. Macrocell registers
can be individually configured to power up to the zero or one state. A global set/reset
control line is also available to asynchronously set or reset selected registers during
operation. Additional local clock, synchronous clock-enable, asynchronous set/reset
and output enable signals can be formed using product terms on a per-macrocell or
per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature
allows high performance synchronous operation based on lower frequency clocking to
1. Xilinx XC2C256
2. XC2C256 development board
3. XC2C256 reference design
4. CoolRunner-II CPLD evaluation kit
5. XC2C256-6FT256C Datasheet PDF
6. XC2C256 evaluation board
7. CoolRunner-II CPLD XC2C256
8. CoolRunner-II CPLD starter kit
9. CoolRunner-II CPLD evaluation kit
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