Volume30, Issue2, February 2020 e12227

Received: 8 February 2019 Revised: 26 August 2019 Accepted: 27 September 2019

DOI: 10.1002/2050-7038.12227

RESEARCH ARTICLE

Processor in the loop test for algorithms designed to control

power electronics converters used in grid‐connected
photovoltaic system

Bouazza Fekkak1 | Mohamed Menaa1 | Bouziane Boussahoua1 | Djamila Rekioua2

1
Power Electronics and Industrial Systems
Summary
Laboratory, Department of Electrical
Engineering, University of Sciences and Enhancement of photovoltaic (PV) system efficiency based on simple testing
Technology Houari Boumediene, Bab techniques is one of the most promising solutions. This is due to its low cost
Ezzouar, Algeria
2
and easy implementation. This paper shows a way to develop applications
Industrial Technology and Information
Laboratory, Faculty of Technology, based on a new method of operating the STM32F407‐VG board. Thereafter,
University of Bejaia, Bejaia, Algeria the processor in the loop (PIL) test can easily be conducted. This method
requires an FT232RL USB‐UART converter board as an external serial
Correspondence
Bouazza Fekkak, Power Electronics and communication interface that can replace the frequently used internal STLink
Industrial Systems Laboratory, communication interface. The main advantage of this external device lies in the
Department of Electrical Engineering,
setting of its baud rate using the aliasing technique. This technique can provide
University of Sciences and Technology
Houari Boumediene, Bab Ezzouar, an efficient solution to transfer data from the embedded board to the computer
Algeria. and vice versa at high baud rate. The PIL testing becomes faster and therefore
Email: fekkak8@msn.com
more flexible. The studied case is a grid‐connected small scale PV system. The
produced power from the PV generator (PVG) is injected into the grid. The

LIST OF SYMBOLS AND ABBREVIATIONS Terminology: DGSs, Distributed generation sources; dq current control, Decoupling control of d and
q current components; DSP, Digital signal processor; FOCV, Fractional open circuit voltage; FT232RL, FTDI Chip FT232RL USB to Serial UART
3MBd, 28‐Pin, SSOP; HIL, Hardware in the loop; INC, Incremental conductance; MPP, Maximum power point; MPPT, Maximum power point
tracking; PEDs, Power electronics devices; Ph, Phase; PI, Proportional integral regulator; PIL, Processor in the loop; PLL, Phase‐locked loop; PV,
Photovoltaic; PVG, Photovoltaic generator; PVG, Photovoltaic generator; PWM, Pulse width modulation; SPR‐435NE, Sunpower SPR‐435NE‐WHT‐
D (435 W) solar panel; STC, Standard test conditions; STC, Standard test conditions; STLink, Internal communication interface for the STM32F
core; STM32407‐VG, ST microelectronics ARM Cortex‐M4 core with DSP and FPU, 1 Mbyte Flash, 168 MHz CPU; VCP, Virtual com port; VOC,
Voltage‐oriented control; VSI, Voltage source inverterSymbols: d, Duty
cycle;
 eabc, (V), 3‐ph Grid voltages; edq, (V), Direct and quadrature
W
components of space vector (e) expressed in park reference frame; G, , Irradiation; iabc, (A), 3‐ph grid currents; L, (H), Filter Inductance;
m2
Mod, Inverter 3‐ph PWM; Q, (VAR), Reactive Power; s, Laplace operator; Vin, (V), Boost converter input voltage; VLL, (V), Line to line voltage; Vo,
(V), Boost converter output voltage; C, (F), Output capacitor of the boost converter; Cin, (F), Input capacitor of the boost converter; Icap, (A), DC
bus current; Idc, (A), PVG output DC current; Ipv, (A), PVG current; Lin, (H), Input inductance of the boost converter; Pac = P, (W), Active power;
Pcap, (W), DC bus power; Pdc, (W), DC Power delivered by PVG; Pmax, (W), Maximum power; Tαβ, Clarke transform; Vdc, (V), DC bus voltage; Vdc*,
(V), DC bus voltage reference; Vmpp, (V), Voltage at MPP; Vpv, (V), PVG voltage; idq *, (A), Direct and quadrature reference components of space
vector (i*) expressed in Park reference frame; idq, (A), Direct and quadrature components of space vector (i) expressed in park reference frame;
uabc*, (V), 3‐ph voltage references for the 3‐ph VSI control; udq*, (V), Direct and quadrature reference components of voltage reference for the 3‐ph
VSI control in park reference frame; va, (V), Grid first phase voltage; vabc, (V), 3‐ph controlled output VSI voltages; vdq, (V), Direct and quadrature
components of space vector (v) expressed in Park reference frame; vm, (V), Grid voltage amplitude; vαβ, (V), Alpha and beta components of space
vector (v) expressed into orthogonal stationary reference frame; θ, (rd), Actual phase angle of grid first phase voltage; θ′, (rd), Estimated phase
angle detected by PLL; ω, (rad/s), Radian frequency of the grid voltage

Int Trans Electr Energ Syst. 2019;e12227. wileyonlinelibrary.com/journal/etep © 2019 John Wiley & Sons, Ltd. 1 of 19
https://doi.org/10.1002/2050-7038.12227
2 of 19 FEKKAK ET AL.

Peer Review
The peer review history for this article is incremental conductance (INC) algorithm‐based maximum power point track-
available at https://publons.com/publon/
ing (MPPT) technique is developed for extracting the maximum power from the
10.1002/2050‐7038.12227.
PVG. The dq current control method is presented for the three phase voltage
source inverter (3‐ph VSI). Further, a scenario of frequency changes in the grid
is chosen in order to verify the phase‐locked loop (PLL) ability to track the grid
phase angle. The simulation results under MATLAB/Simulink show the effi-
ciency of both controllers and dynamic behavior of the full PV chain. Next,
the proposed PIL test is performed by automatically generating the C code from
both control algorithms using the Simulink features. This C code is imple-
mented on the STM32F407‐VG board that acts as an external controller mean-
while the plant is still running on the host computer. The PIL test results show
that the controllers simulated under MATLAB/Simulink behave in the same
way once executed on the embedded board

K E YWO R D S
dq current control, grid, MPPT, PIL

1 | I N T RO D U C T I O N

Historically, control design for power electronics devices (PEDs) was tested in the field or with analog simulators.1 This
process was slow to analyze information1 and its ability to represent large AC systems was limited.2 Moreover, it pre-
sented much risks of damaging the expensive hardware, which increased testing time and cost.3,4 Also, if the designed
controllers are tested directly on PEDs, it is difficult to know precisely which components operating in the real plant are
causing the failure when a bug occurs. This testing method, which is purely hardware‐based, increased the consumed
time to debug runtime errors. Thus and for rapid and safe processing, many purely software‐based approaches are devel-
oped such as the model in the loop (MIL) or software in the loop (SIL) simulations.5 They certainly reduce danger and
high cost but provide limited information about aspects of design and problems that could arise later during the devel-
opment process.3,6 Researchers had to deal with such testing‐related disadvantages. They ended up overcoming these
drawbacks by developing new methods that are in the same time software and hardware based. Their main objectives
for reducing cost danger and testing time while still keeping testing efficiency. They have further improved with the
advent of DSP and high‐performance processors during these last few years.
Among these techniques, there is the processor in the loop (PIL) testing that can be applied in many applications
such as wind turbine, chemical reactor, robotic, drone, and many others. This testing technical is mainly used to check
the system ability to handle potential problems. It consists to predict that simulated controllers behave the same way as
on real plant.4 In addition, this test can be repeated many times to make possible corrections till the problems are solved
reducing risk, testing time and cost.5
PIL testing is one of the most powerful tools used to test and design embedded system with low‐cost option. If the
hardware in the loop (HIL)3,4,6,7 test is designed to be a real‐time simulation,2,3 PIL test is not to be “real‐time.” Thus,
no expensive real time systems are needed such as RTDS, Opal‐RT, NI PXI, HYPERSIM simulators.1,2
Many studies showing PIL testing applications using STM32F/ Dspic/FPGA/DSP cores. It concerns the testing of con-
trollers such as the PEDs controllers.5,8-12
Each of the cores cited above has its own advantageous and drawbacks. But the main advantageous of the STM32F
core compared with FPGA and Dspace cores besides its low cost is its easy implementation. Indeed, there is no need to
manually write a complex program as the VHDL for the FPGA boards.9 Over more, the Cortex M3 of the STM32F core
(168 MHz) is much faster than Dspic core, which is limited to 40 MHz.13 Further, the serial I/O module UART available
in the Dspic board to interface the control circuit with computer cannot support above 9600 bps.8
Regarding PIL testing that are performed by STM32F cores, many authors used the same method to reach their
goals.5,10,11 In most cases, internal STLink communication interface is used. This method is a bit complicated since there
are three different steps to perform the PIL testing. Starting from the MIL simulation, followed by the SIL simulation,
FEKKAK ET AL. 3 of 19

and ending by the PIL test.5 Each step has its specific objective. For the MIL, the objective is to check the model devel-
oped from the algorithm meets the desired requirements. Whereas for SIL, the objective is that the software generated
from the model in the host computer is in accordance with the MIL. Finally, the objective for PIL testing is to check that
the software generated from the model in the embedded target is in accordance with SIL. In addition, configuring many
parameters on Simulink makes the task more complex such as, enabling PIL in order to create a PIL block and choosing
an operating system (OS) (Baremetal or CMSIS‐RTOS RTX), which can limit performance efficiency. Further, among
the drawbacks of this method is that the internal communication interface cannot support more than 115 200 bps. This
influences the communication speed between the target and the host and then the speed of the PIL test.
Thus, new simpler PIL method using STM32F407‐VG board is proposed instead of those cited in the literature.5,10,11
The FT232RL USB‐UART converter board is used as external communication interface in order to create a virtual serial
port on computer (COM port). The main advantage of this external board is that it can be easily set. One of the most
basic operations with the all class of FT232R boards is the setting of their baud rates. This technique called “aliasing”,14
where one baud rate is substituted by the driver in place of another baud rate. In this case, we can easily exceed
115 200 bps significantly.
Regarding the optimization of the grid connected photovoltaic (PV) systems, it is still a big challenge for researchers.
Therefore, many solutions are proposed in order to improve their energy efficiency.15-23 Considerable efforts are effec-
tively made to control these systems. The most common control strategies applied to the grid‐tie inverter are based
on either voltage‐oriented control (VOC)23 or decoupled current control.24 This decoupling control is used to control
active power (P) and reactive power (Q) separately.19,24 For the control of the DC‐DC boost converter, many maximum
power point tracking (MPPT) techniques are discussed in the literature.5,10,16,25 Another MPPT technique based on frac-
tional open circuit voltage (FOCV) is modified and discussed in Fekkak et al.23 The phase‐locked loop (PLL) is used for
synchronization between the 3‐ph VSI and the grid..16,23-25
The example discussed in this paper deals with the case of a small PV system connected to a utility grid, without stor-
age batteries. All PVG production is injected into the grid. A scenario of frequency changes in the grid is chosen in order
to show ability of the PLL to track the grid phase angle..26
This proposed PIL method, which is described in detail in Section 5, is performed in order to test algorithms that are
designed for controlling the boost converter5,10 and the 3‐ph VSI operating in the PV chain.11 These control algorithms
tested by PIL integration method, are the following:

1. The dq Current control23,26: In this control method, the active power reference is set according to the DC bus power
while the reactive power reference is set to zero.
2‐. INC algorithm‐based MPPT27,28: This technique is used in order to extract maximum power (Pmax) from the PVG.

The DC bus voltage is maintained constant by means of bus voltage control integrated in 3‐ph VSI controller. The
proposed DC bus voltage control is developed in Section 3.2.
Once the controllers and the power plant are working correctly when simulated in the same software environment,
the PIL testing is then performed. This step is done after configuration of the Waijung Blockset on MATLAB/Simulink
as described in detail in Section 5.2. After that, C code is generated and run onto target hardware (STM32F407‐VG),
which acts as a controller. Whereas, the plant still running in MATLAB/Simulink environment (on host computer),
as shown in Figure 1.
If any glitches occur during the PIL testing, it will easily go back to controllers for making necessary changes, before
generating the C code and implementing it again on the embedded board. This operation can be repeated many times

FIGURE 1 Processor in the loop (PIL) closed loop

4 of 19 FEKKAK ET AL.

until simulation results are satisfying.10,11 Once above tests are completed and accepted, the controllers can be safely
implemented on real hardware.
This paper is organized as follow: System presentation is introduced in Section 2. The 3‐ph VSI, the Boost converter
and their controls are presented in Sections 3 and 4. Proposed PIL simulation steps are presented in Section 5. The sim-
ulation results followed by the PIL test results to show validity of the proposed model under various irradiations and
constant temperature are presented in Sections 6 and 7. Finally, conclusion is presented in Section 8.

2 | SYSTEM PRESENTATION

The proposed PV system is illustrated in Figure 2, and it is equipped with the following:

1. Four (×4) SPR‐435NE modules connected in series. The datasheet of this module is given in Table 121;
2. Boost converter;
3. 3‐ph VSI;
4. 02 controller blocks;
5. AC utility grid with parameters given in Table 2.23

FIGURE 2 Simulink of the grid‐connected photovoltaic (PV) system

TABLE 1 Module SPR‐435NE‐WHT‐D SOLAR PV PANEL/Electrical datasheet at STC

Parameters Index Values

Maximal power Pmax 435 W

Open circuit voltage Voc 85.6 V
Short circuit current Isc 6.43 A
Voltage at maximim power Vmpp 72.9 V
Current at maximim power Impp 5.97 A
Temperature coefficient for Voc β −0.28%/°C
Temperature coefficient for Isc α 0.060%/°C

TABLE 2 Filter and grid parameters

Parameters Index Values

Line to line voltage VLL 380 V

Frequency f 50 Hz
Filter Inductance L 0.002 H
FEKKAK ET AL. 5 of 19

3 | T H E 3‐ p h V S I C O N T R O L L E R

The controller is necessary to drive the 3‐ph VSI in order to transform a DC quantity to an AC quantity and for keeping
DC bus voltage constant.16,22,23
This controller is composed of eight blocks. Each Block has a specific role as described below:

○. Block 1: Ensure the DC bus measurement;

○. Block 2: Ensure the AC grid measurement;
○. Block 3: PLL. Ensure synchronization with grid;
○. Block 4: DC voltage controller;
○. Block 5: Park transform. Ensure transformation from abc to dq;
○. Block 6: Current controller;
○. Block 7: Inverse Park transform. Ensure transformation from dq to abc;
○. Block 8: PWM converter.

The blocks 3, 4, and 6 of the diagram shown in Figure 3 are detailed below:

3.1 | Current controller block—block 6

The 3‐ph grid tie inverter can be represented by Figure 4.

The voltage at the grid side of the converter can be formulated as follows23:.

d
vabc ¼ L iabc þ eabc (1)
dt

Where uabc are the 3‐ph output voltages of the 3‐ph VSI. While, iabc refer to grid currents and eabc refer to grid
voltages. L, being the filter, which is located between the 3‐ph VSI and grid. The resistive part will be ignored.16,23

FIGURE 3 Synoptic of the control

diagram

FIGURE 4 Topology of the 3‐ph grid tie inverter15

6 of 19 FEKKAK ET AL.

3‐ph currents and voltages are transformed in dq reference frame using Park transform.23,26 Thus, (1) becomes (2):
" # " #  " # " #
vd d id 0 −1 id ed
¼L þ ω:L þ (2)
vq dt iq 1 0 iq eq

The error between reference currents and measured currents is carried via PI controller. The decoupling terms from
(2) are compensated by feed‐forward. The components of the control voltage for the 3‐ph VSI in park reference frame are
obtained (3).23
(  
u* d ¼ PI i* d − id − ω:L:iq þ ed
  (3)
u* q ¼ PI i* q − iq þ ω:L:id þ eq

The dq current control is realized by putting (i*q=0)..16,23

The structure of the inner current controller is illustrated in Figure 5.
The reference voltage components presented in (3) are transformed back to (u*abc), using inverse Park trans-
form.18,23,29 These 3‐ph voltage references are used as inputs for PWM to control the 3‐ph VSI.

3.2 | Block of the proposed DC Bus voltage control—block 4

Tuning of the DC‐link voltage controller is determined by the transfer function between the defined current reference
value and the DC‐link voltage.
From power balance of the VSI‐DC terminal (Figure 4).

Pac þ Pdc þ Pcap ¼ 0 (4)

3
vd id þ vdc I dc þ vdc I cap ¼ 0 (5)
2

where Idc and Icap are the PVG output DC current and the DC bus current respectively, and 3/2 factor comes from the
Park's transformation.
From (5), the current through the DC bus capacitor (C) is


3 v d id
I cap ¼− þ I dc (6)
2vdc

And the same current in terms of voltage across the capacitor is given by

dvdc
I cap ¼ C (7)
dt

FIGURE 5 Structure of the inner current control23,26

FEKKAK ET AL. 7 of 19

From Equations (6) and (7), the differential equation for the dc voltage becomes


dvdc 3 vd id 2 vdc I dc 3 vd id id
¼− id þ ¼− id − I dc (8)
dt 2Cvdc 3vd 2Cvdc C

Applying Laplace Transform to (8), we obtain (9)


id 3 vd
s vdc ¼ − id þ I dc (9)
C 2vdc

((9) shows that DC voltage is regulated by controlling the active current id. From (9), DC voltage control block dia-
gram is proposed and presented in Figure 6.

3.3 | PLL—block 3

Injected inverter current must be synchronized with grid voltage in the case of distributed generation sources (DGSs).
So, it is required to work at unity power factor according to the IEEE standard 1547.26 The phase angle of grid first volt-
age must be extracted to synchronize the system with grid.23
There are many PLL structure cited in literature.15,16,19,20,29 In this article, an easily configurable PLL method is used.
This PLL based on the Clarke transformation is detailed below:

3.3.1 | αβ‐PLL using Clarke transform:

The instantaneous grid voltages are defined as follows23:

2 3 2 3
va vm sinðθÞ
6 7 6 7
vabc ¼ 4 vb 5 ¼ 4 vm sinðθ − 2π=3Þ 5 (10)
vc vm sinðθ þ 2π=3Þ

These balanced instantaneous grid voltages (vabc) are transformed to be alpha‐beta voltages (vαβ) expressed into
orthogonal stationary reference frame, by using Clarke transform (Tαβ) as given by (11).23,30
2 3
1 1
1 − −
26 2 2 7
T αβ ¼ 6 pffiffiffi pffiffiffi 7 (11)
34 3 35
0 −
2 2

This allows us to write:

vαβ ¼ T αβ :vabc (12)

FIGURE 6 Block of the proposed DC bus voltage controller

8 of 19 FEKKAK ET AL.

Replacing vabc and Tαβ by their values described by (10) and (11), then (12) becomes (13):
" #  
vα vm sinðθÞ
¼ (13)
vβ vm cosðθÞ

From (13), we obtain (14)

vα vm sinðθÞ
¼ (14)
vβ vm cosðθ ¼ tanðθÞ

Therefore


vα
θ ¼ arctan (15)
vβ

As it can be seen, both signals vα and vβ do not carry information about the grid amplitude (vm). So, only the phase
angle (θ) of grid first phase voltage (va) is detected.

4 | DC‐DC BOOST CONVERTER

The main role of DC‐DC boost converter presented in Figure 7 is to control the DC voltage via an adequate algorithm.
This to make the PVG always operates at MPP.6,10,21 The MPPT device is therefore very important for PVG efficiency.
The converter gain is given by (16),5,10,23,28:

Vo 1
¼ (16)
Vin 1 − d

The parameters of the used Boost converter are given in Table 316:

4.1 | Maximum power point tracking

The extraction of the maximum power is an essential step in the PV energy conversion field. To increase the efficiency of
the GPV, a maximum power point (MPPT) algorithm is applied to the DC/DC converter.16,26:

FIGURE 7 Boost converter topology5,10

TABLE 3 Parameters of the boost converter

Parameters Values

Lin 24.10−9 H
C 9.10−3 F
Cin 5.10−3 F
R 10−3 Ω
FEKKAK ET AL. 9 of 19

4.1.1 | MPPT tracking device

The power supplied by a PV field depends mainly on environmental conditions (irradiation, temperature, and shading).
Therefore, in order to produce maximum power, MPP must be continuously track down by the MPPT algo-
rithm.5,6,10,23,25 The algorithm called INC is used for its simplicity and ease of implantation in real time.,27,28 Figure 8.

INC algorithm
dP
The INC algorithm is based on the fact that the maximum power point (MPP) is reached only if dV
¼ 0).27,28 The PV
array characteristics shown in Figure 8, prove further that (dP dV ) is greater than zero to the left of the MPP and less
than zero to the right of the MPP. This leads to the following set of equations:

dP=dV ¼ 0 for V ¼ Vm
dP
dV
>0 for V > Vm (17)
dP=dV < 0 for V < Vm

Given P = I × V, the derivative of the produce power with respect to the voltage V, gives the following relation:

dP dðVxI Þ dV dI dI
¼ ¼I þV ¼IþV (18)
dV dV dV dV dV

dP
If P is maximal, then ¼ 0, then:
dV

dI I
¼− (19)
dV V

The required incremental changes dV and dI are obtained by comparing the most recent measured values for V and I
with those measured during the previous cycle:

dV ðkÞ ≈ V ðkÞ − V ðk − 1Þ (20)

dI ðk Þ ≈ I ðk Þ − I ðk − 1Þ (21)

The central function for finding the MPP uses the following conditions:

dI I
¼− (22)
dV V

dI I
>− (23)
dV V

FIGURE 8 Sign of the dP/dV at different positions on the photovoltaic (PV) characteristic curve of a PV array27,28
10 of 19 FEKKAK ET AL.

If the relation (22) is true, then the MPP is reached and no change in the voltage V(k) is necessary. If the relation (22)
is false, depending on whether V(k) is greater or less than Vmpp, the voltage V(k) is adjusted accordingly to the following
flowchart as presented in Figure 9.

5 | P RO P O S E D P I L T E S T

To achieve this purpose, the following steps must be followed:

a. Testing the Model in MATLAB/Simulink

○. In this first step, PV plant model and its control are created and simulated in the same MATLAB/Simulink envi-
ronment, as presented in Figure 2. The aim is to check if the model developed works properly with no errors.

b. Waijung Installation

To install Waijung, the following steps must be done:

○. Download and Install STM32 ST‐Link Utility

STM32 ST‐LINK Utility (STSW‐LINK004) is a full‐featured software interface for programming STM32F board.

○. Install Waijung Blockset

After executing “install_waijung.m” from within MATLAB, Waijung will automatically create a Sublibrary with all
its content (Blockset) and should appear in Simulink libraries to be ready for use. The Installation Status and Installed
Blockset must be checked in order to know if the installation is successful.

○. Install FT232RL USB UART Driver

This driver is necessary to make the FT232RL board work properly. It is also used in order to create Virtual COM Port
(VCP), and causes the USB device to appear as an additional COM Port available on computer.

c. Dividing the model into two parts

FIGURE 9 Incremental conductance (INC) algorithm flowchart27,28

FEKKAK ET AL. 11 of 19

The Model is divided into two main parts in two separated Simulink model: Power and Control parts Figure 10.

○. Power part (Figure 10A): PVG: Boost converter; 3‐ph VSI; PLL; Grid.

○. Control part (Figure 10B): INC and dq current control algorithms.

○. The following output‐ports of the Power part, which represent at the same time the input‐ports of the control part
are colored in red, as shown in Figure 10A,B.

PVG voltage (Vpv), PVG current (Ipv), Grid 3‐ph voltages and currents (Vabc, Iabc), DC bus voltage (Vdc), grid first
phase angle (ωt).

○. While, the following input‐ports of the power part, which represent at the same time the output‐ports of the control
part are colored in blue color, as shown in Figure 10A,B.

FIGURE 10 The Simulink Model divided in two parts: A, power part; B, control part
12 of 19 FEKKAK ET AL.

Duty cycle (D) and 3‐ph PWM (mod).

○. The red ports are connected to UART RX block ports and Blue ports are connected to UART TX blocks ports in the
Simulink Target part. Inversely, these red ports are connected to Host Serial TX block ports, and blue ports are con-
nected to Host Serial RX Block ports in the Simulink Host part.

d. UART configuration of the control part and generation of the C code.

✓. Figure 11 shows the configuration of system control part (Target). The generated C code is implemented on
STM32F407 board. The UART/Rx Block is configured to receive the values from the controls part (Target) and
UART/Tx Block is configured to send the instruction to it.

✓. To generate the C code of both controllers from the control part and implemented it on the STM32F407‐VG
board, it is simply required to click on the build process button available on Simulink window. The Waijung track
building process window is then displayed as shown in Figure 12.
✓. The Waijung Track Build process indicates the result of each operation. All green, indicate “success”. All red, indi-
cate “Failure,” Figure 12.
✓. This model need only compile (auto download will be disabled).

FIGURE 11 UART configuration of the control part in Simulink

FIGURE 12 Build process window

FEKKAK ET AL. 13 of 19

e. Host serial configuration of the power part and Connection Layout between STM32F407 with FT232RL cards
(Figure 13).

✓. The both boards (FT232RL and STM32F407‐VG) are connected from their USB (type Mini B) to the computer USB
(type A).
✓. Simulation is run from Simulink (Host PC). The STM32F407‐VG board, which is implemented with C code is acting
as controller.
✓. Pin D8/D9 (which are set at Tx/Rx) of the STM32F407 board are connected to Rx/Tx of the FT232RL board, respec-
tively. GND Pins of both boards are joined together.
✓. Host Serial Tx Block is configured to receive the values from PV plant (Host). Host Serial Rx Block is configured to
send the instruction to it.

STM32F407 with FT232RL boards

Figure 14 summarizes the PIL test. The STM32F407 board acting as external controller is connected to the computer
on which the power part is executed. The system behaves as if it is in a real environment with the following values (Vpv,
Ipv, Vdc, Vabc, Iabc, ωt). It means that instead of reading the physical sensors, the values of the above cited signals are

FIGURE 13 Host serial configuration of the power part in Simulink and connection layout between

FIGURE 14 The input and output signals in the implementation with the STM32F407 board
14 of 19 FEKKAK ET AL.

calculated by simulation tool and used as inputs for the embedded board. In return, the values of the outputs signals (D,
mod) computed by STM32F407 processor are fed back into the Simulation to drive the virtual environment. The simu-
lation results are also displayed on Simulink scopes.
f. Setting up communication in UART and Host Serial.
To get the most effective results of the simulation, we should set the Host Serial Block in the host model and UART
Rx/Tx Block in the target model.
Characteristics of Host PC and target are given in Table 4.
After putting the initial value (as closed loop HIL test) at “NOT Checked,” the host will send the information to
the target at the start of the simulation. This ensures that the data transfer between host and target can pick the correct
setting as shown in Table 4.
Further, format must be defined for data transmission between Host and Target for synchronization. Binary data
format is recommended for high‐speed data transfer. If the computer does not receive data from the target board, then
error message will be displayed.

6 | SIMULATION RESULTS (POWER AND CONTROL PARTS IN SAME

M A T L A B / S I M U L I N K EN V I R O N M E N T

The simulation model with the proposed control scheme is built on the platform of MATLAB/Simulink with simulation
time equal to 1.5 second. Irradiance scenario is shown in Figure 15. Temperature is set constant at 25°C.
In this case, maximum power (Pmax) and Voltage at MPP ( Vmpp) delivered by the PVG at different Irradiances (G)
and T = 25°C are shown in Table 5.

TABLE 4 Configuration of host serial and UART (Rx/Tx) blocks

Host PC Target STM32F407 Board

Host serial Rx Block Host serial Tx Block UART Rx Block UART Tx Block
Transfer Enable initial value Transfer Transfer
Case Mode (Closed Loop HIL test) Transfer Mode Mode Mode

Algorithm in Target Plant Blocking NOT Checked Blocking Blocking Blocking

in Host PC

FIGURE 15 Scenarios of irradiance and temperature

TABLE 5 Pmax and Vmpp values at different irradiation (G)

G, W/m2 Pmax, W Vmpp, V

1000 1740 291.6

800 1392 287.8
600 1044 284.6
FEKKAK ET AL. 15 of 19

vdc is adjusted at 800 V and maintained constant.

The frequency changes in the grid are shown in Table 6.

6.1 | Simulation results

The following figures show results of some simulations of case studies.

6.2 | Discussion of the simulation results

○. From 0 to 0.5 s, G = 600 w/m2, T = 25 °C, f = 49.8 Hz, Pmax = 1044 W:

Figure 16A presents the DC side voltage. It shows that PVG delivers Vmpp ≈ 284.6 V as mentionned in Table 5.
While, the DC bus voltage follows instantaneously its reference voltage (Vdc*). In steady state, the DC bus voltage
is stabilized at 800 V as desired. Figure 16B shows that the DC power delivered by PVG reaches its maximum
(≈1044 W) as mentioned in Table 5. The Figure 16C shows that the active power injected to the grid (≈1040 W)

TABLE 6 Frequency profile (f)

Time Simulation, s Values, Hz

0‐0.5 49.8
0.5‐1 50.2
1‐1.5 50

FIGURE 16 Simulation results with MATLAB/Simuliink. A, DC voltages; B, DC powers.; C, grid active and reactive power PQ_grid; D,
grid side line current (×68) and voltage; E, frequency variation
16 of 19 FEKKAK ET AL.

FIGURE 17 Simulation results with PIL test. A, DC Voltages; B, DC powers.; C, grid active and reactive power PQ_grid; D, Grid side line
current (×68) and voltage; E, Frequency variation

is slightly lower than the DC power, due to the internal power losses. The Figure 16E shows that the grid frequency
is detected as expected (49.8 Hz).

○. From 0.5 to 1 s, G = 1000 w/m2, T = 25 °C, f = 50.2 Hz, P_max = 1740 W:

Figure 16A shows that PVG delivers Vmpp ≈ 291.6 V as mentioned in Table 5. In steady state, the DC bus voltage is
stabilized at 800 V as desired. The simulation of the DC power at (STC) should reach its maximum as mentionned in
Table 5. This matches the simulation result in Figure 16B (≈1740 W). Figure 16C shows that the active power injected
to the grid reachs almost its maximum (≈1737 W) as expected. Figure 16E shows that PLL has succeeded to track the
new grid frequency as expected (50.2 Hz).

○. From 1 to 1.5 s, G = 800 w/m2, T = 25 °C, f = 50 Hz, Pmax= 1392 W:

Figure 16 A shows that PVG delivers Vmpp ≈ 287.8 V as mentionned in Table 5. The DC bus stabilizes in steady state
at the reference value (Vdc ≈ 800 V) as expected. In this simulation period, the PVG should be close to the MPP curve
and providing maximum DC power (≈1392 W) as mentionned in Table 5. This result is close to the simulation result in
Figure 16B. The Figure 16C shows that the active power injected to the grid (≈1387 W) is almost equal to the expected
value, and Figure 16E shows that the grid frequency is also acruatlely detected as expected (50 Hz).
Finally and for the all simulation period and regardless of irradiance changes, we can see in Figure 16C that the reac-
tive power remains null according to the desired reference (i*q = 0), and Figure 16D shows that there is no advance or
delay in the phase between grid side line voltage and current. They are in phase and sinusoidal. The THD of the current
is lower than 2%.
Considering all simulation results, we conclude that

○. The performance of the proposed DC bus voltage control is verified.

FEKKAK ET AL. 17 of 19

○. The pq control performance to maintain the power factor close to unity as desired is demonstrated.
○. The tracking accuracy of INC algorithm‐based MPPT is verified.
○. The PLL ability to track the grid phase angle is obtained.

7 | PIL TEST RESULTS USING STM32F407 BOARD

Once both control algorithms are validated in the Simulink environment, the PIL test is performed.
The same climatic conditions and the same frequency changes are chosen. The simulation time is always equal to
1.5 second.
The goal here is to check if both controllers behaves in the same way as in the simulation under MATLAB/Simulink.

7.1 | Discussion of the PIL test results

○. For the entire simulation period:

Figure 17A shows that DC bus voltage is maintained constant (≈800 V) as desired. The Figure 17B shows the DC
power produced by the PVG reaches its maximum (approximately 1740 W) at STC as expected. Figure 17C shows that
the injected active and reactive power follow their reference values (approximately 1740 W and 0 Var) as expected. It is
supposed that losses are not important in the studied system. Figure 17D shows that grid side line voltage and current
are in phase, and Figure 17E shows that the grid frequency is accurately detected as expected.
The obtained results presented in Figure 17 using PIL test are in totally accordance with the simulation results illus-
trated in Figure 16. The same discussion for the simulation can be then made for the PIL test. Both converters have the
same behavior as that obtained during simulation under Simulink. The automatically generated code from both control-
lers algorithm can be then safely implemented on real hardware.

8 | CONCLUSION

This manuscript proposes a new method of operating the STM32F407‐VG board in order to perform the PIL
integration method. The controllers elaborated under Simulink are directly implemented on embedded board without
any requirement for the designer to manually re‐write the program.
The FT232RL USB‐UART converter board is used as an external serial communication interface instead of internal
STLink interface. The major advantage of this external device is that it supports much more than 115 200 bps that
STLink cannot handle. This will increase the PIL test speed while the efficiency is kept unaltered.
The studied case is the implementation of PEDs control algorithms that are used in grid connected PV system. Once
both controllers behaved correctly when simulated together with their corresponding plant model in the same software
environment, the PIL test is the next step. The C code is automatically generated from both algorithms control and
implemented on the embedded board while the plant is still running on the host computer.
The control strategies and simulation results under MATLAB/Simulink as well as the results of PIL integration
method are presented. The simulation results obtained for various operating conditions show the robustness of the
d‐q current control to regulate the injected active power into the grid and to achieve a unity power factor. Through
the same simulation results, the performance of the proposed DC bus voltage control and the tracking accuracy of
the selected INC algorithm‐based MPPT are also verified. Further, they show PLL ability to accurately track the grid
phase angle even during fast frequency changes.
The results of the PIL integration method show that they are in total accordance with the simulation under
MATLAB/Simulink. Thus, this proposed PIL test method could provide an easy manner to test prototypes with low cost
option. Also, danger and testing time are significantly reduced. These control algorithms, which are verified using PIL
test can be integrated with embedded software that interfaces with real PV power converters.
On the other hand, this grid connected small PV system can be a typical solution for residential PV applications. It
can also be a solution to meet energy demand part and improve the electrical distribution grid. Finally, the controllers
18 of 19 FEKKAK ET AL.

developed through this inexpensive embedded board as well as the proposed PV system topology can contribute to
reduce the high costs of PV systems.

ORCID
Bouazza Fekkak https://orcid.org/0000-0002-8696-8578

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How to cite this article: Fekkak B, Menaa M, Boussahoua B, Rekioua D. Processor in the loop test for
algorithms designed to control power electronics converters used in grid‐connected photovoltaic system. Int Trans
Electr Energ Syst. 2019;e12227. https://doi.org/10.1002/2050‐7038.12227