An Improved SVPWM Strategy For Three-Level Neutral Point Clamped Converter Capacitor Voltage Balancing
An Improved SVPWM Strategy For Three-Level Neutral Point Clamped Converter Capacitor Voltage Balancing
An Improved SVPWM Strategy For Three-Level Neutral Point Clamped Converter Capacitor Voltage Balancing
Abstract— DC link capacitor voltage balancing is a classical inserted into the converter. These “hard” methods basically
issue of multilevel converters because it causes error in output increased the size and cost of the converter.
voltages or even damages the capacitors. Additional circuits or
proper uses of redundant states can be utilized to reduce the On the other hand, other researchers want to use soft
deviation of neutral point voltage. This paper proposed an methods. They did not increase the hardware complexity of
improved method using modulating times of redundant states the converter but required much more complicated
as optimal parameters in capacitor voltage deviation calculation executed in drive circuits. In [7] the authors
minimization problem of three-level neutral point clamped introduced an alternative space vector modulation technique
converters. The procedure of formulating and minimizing the for three-level NPC converter in an aircraft starter generator
capacitor voltage deviation is presented in detail. Test results system. In the region of high modulation index, the medium
show the significant improvement of this method over previous vectors were not used, but a small vector instead. This
solutions. doubles the step in the output phase voltages and takes away
the staircase waveform, hence, the advantage in harmonic
Keywords—three-level NPC converter, redundant state, space characteristics of the three-level converter. The authors of [2]
vector modulation, quadratic function and [3] aimed to select the best switching states to generate
I. INTRODUCTION the required output voltage and at the same time drive the
voltage of DC link capacitors to balance value. The
Three-level converters are more and more interested in disadvantage of this method is that only one redundant state
research and industrial applications where high power and was used for one vector throughout the whole sample time
medium voltage are required because they have many and this can very likely cause overshoot.
advantages over classical inverter. They generate staircase
waveform of output voltage, hence improve its harmonic In this paper, the authors proposed a way to improve the
characteristic; combine the working voltages of valves soft methods. Space vector is held unchanged to preserve the
connected in series, so reduce the required blocking voltage principle of “three nearest vectors” but manipulated times of
of valves as compared to classical two-level inverter of the redundant states are used as optimal parameters. Test results
same output voltage capability. show the validity of this method. The neutral point voltage is
stabilized and its deviation about balance point decreases
There are three main topologies of there-level converter, dramatically as compared to former methods. Although a lot
which are neutral point clamped (or diode-clamped), flying of calculation is required per sample time, intervening at
capacitor (or capacitor clamped), and cascaded H-bridge. In these optimal parameters has become increasingly simple
this paper, the neutral-clamped topology (Fig. 1) is due to the recent development of digital signal processors.
considered. It was the first type of multilevel converter.
Despite having many advantages, three-level NPC
converter has a classical drawback which is to keep the Cup
capacitor voltage balanced when using only one DC source.
Otherwise neutral point (O) voltage will not be equal to Edc
Edc 2 and the exact required voltage cannot be generated, 2
especially when the modulation index is low. Moreover, this
leads to unsafe working of the capacitors. ia
Edc ib
This critical problem is of great concern since three-level ic
NPC converter was first used. Many researches were 0
conducted and many solutions were proposed.
On the one hand, researchers proposed using additional Edc
hardware for balancing capacitor voltages. The authors of [1] 2
used a “back-to-back” rectifier/inverter configuration and Cdown
coordinated switching angles of rectifier and inverter to
achieve capacitor charge balance. In [4] auxiliary capacitor-
based circuits were used. In [5] and [6] inductors were
Fig. 1. Three-level NPC converter topology.
The research was performed with the support of the Russian Ministry
of Education and Science grant (Project № 8.8313.2017/BCh).
978-1-7281-4158-9/20/$31.00 ©2020 IEEE
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II. METHOD FOR CALCULATION AND MINIMIZING NEUTRAL
POINT VOLTAGE DEVIATION
To minimize neutral point voltage deviation using
manipulating times of redundant states as optimal
parameters, it is necessary to build its formula as a function
of manipulating times, then minimize this function and
design an appropriate sequence of states.
A. Calculation of neutral point voltage deviation
(type 1) (type 2)
The shift of neutral point voltage (or lower capacitor
voltage ΔVC ,low ) is caused by phase currents flowing to
neutral point. According to [3], if the sample time is
supposed to be short enough compared to output current
period, the phase currents change very little during one
sample time, then ΔVC ,low after one sample time is derived as
(1) for the case of three-level neutral point clamped
converter.
ta ia + tb ib + tc ic
ΔVC ,low = (1)
Cup + Clow
(type 3) (type 4)
where t a , t b , and t c are the connected times to neutral point
during one sample time of phases a, b, and c, respectively. Fig. 3. Four types of triangles in space vector.
The estimated deviation of neutral point voltage after this To have the specific formulae of (2), it is necessary to
sample time is: determine which phases will be connected to neutral point
and how long they will connect. Moreover, the calculation is
Edc
ΔE = − VC ,low − ΔVC ,low (2) analogous in any Sector, so in this paper only formulae
2 derived from Sector 1 are shown in detail.
When the voltage vector Vs rotates in the space vector, (2)
will have specific forms. To our knowledge, the modulation times t1, t 2 , and t 3 were
used for only the “best states” of the required vector V1, V2 ,
The space vector of three-level NPC converter consists of
and V3 . In this paper these times are allocated for every
27 states, making 24 triangles as shown in Fig. 2.
redundant state to utilize compensating ability to neutral
For the sake of simplicity in calculation of duty cycles, Vs point voltage of every phase as much as possible.
and its three nearest vectors are rotated to Sector 1. The
feasible rotated vector will fall into one of the four triangles 1) When voltage vector Vs rotates in triangle 2
as shown in Fig. 3. The three nearest vector used to Referring to Fig. 2 and Fig. 3, there are two possible
synthesize Vs will come to apices of triangles in Sector 1. The states for vector V1, which are V11 (100) and , and only one
modulation times required for vectors V1 , V2 , and V3 are state for each vector V2 or V3, which are V2 (200) and (210).
denoted as t1, t 2 , and t 3, respectively. Both V11 and V21 are used with total period per sample time,
say T1 and T2. Phase a is connected to neutral point when V11 is
manipulated. Phase b is connected to neutral point when
manipulating V12 or V3 . And for phase c, when V12 is
manipulated. So the total change of the neutral point voltage
after one sample time is:
T1ia + ( t1 − T1 )( ib + ic ) + t3ib
ΔVC ,low = (3)
Cup + Clow
Substitution (3) to (2) leads to the formula of neutral
point voltage deviation:
Edc t (i + i ) + t3ib ia − ib − ic
ΔE = − VC ,low + 1 b c + T1 (4)
2 Cup + Clow Cup + Clow
2) When Vs rotates in triangle 4
There are two possible states for vector V1 which are
V11 (110) and V12 (221) . Following the same process as for
triangle 2, now the formula of neutral point voltage deviation
is:
Edc (t i + t i ) i − i − i
ΔE = − VC ,low − 1 c 2 b + c a b T1 (5)
2 Cup + Clow Cup + Clow
Fig. 2. Space vector of three-level NPC converter
where T1 is total time to manipulate V11 in one sample time.
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3) When Vs rotates in triangle 3 To minimize the number of valves to be switched the
Now each of the vectors V1, V2 has two redundant states. sequence of states in one sample time and their
Let the two states V11 (110) , V12 (221) of V1 take total times T1 corresponding intervals are designed as follow:
and (t1 − T1 ) and the two states V21 (100) , V22 (211) of V2 take T t t t −T
total times T2 and (t2 − T2 ). In this triangle the formula of ΔE V11 1 → V2 2 → V3 3 → V12 1 1 →
after one sample time is as follow: 2 2 2 2
t t T
Edc t i + t (i + i ) + t3ib → V3 3 → V2 2 → V11 2
ΔE = − VC ,low + 1 c 2 b c + 2
2
2
2 Cup + Clow If some state’s interval is zero, then it is not manipulated.
(6)
i +i −i i −i −i
+ a b c T1 + a b c T2 2) When Vs rotates in triangle 4
Cup + Clow Cup + Clow T1 is found by solving the optimal problem:
4) When Vs rotates in triangle 1 2
and V22 (221) take total times T2 and (t2 − T2 ) ; and the three + c a b T1
Cup + Clow
state V31 (111) , V32 (222) , and V33 (000) take total times T3 ,
(t3 − T3 ) 2 , and (t3 − T3 ) 2 . Actually, when the load is Let
perfectly symmetrical there is no need to consider T3 because
Edc
the total effect of three phases to neutral point is cancelled. 2 − VC ,low ( Cup + Clow ) − t1 (ib + ic ) − t3ib
The formula of ΔE in this triangle now becomes: T14* = −
Edc t (i + i ) + t2 ic ia − ib − ic ic − ia − ib
ΔE = − VC ,low + 1 c b + T1 +
2 Cup + Clow Cup + Clow The solution of T1 is:
(7)
ia + ib − ic i +i +i T1 = t1 2 if ic − ia − ib = 0
+ T2 + a b c T3
Cup + Clow Cup + Clow T1 = 0 if T14* ≤ 0 and ic − ia − ib ≠ 0
B. Optimal times for redundant states and their sequence T1 = T14* if 0 < T14* ≤ t1 and ic − ia − ib ≠ 0
1) When Vs rotates in triangle 2 T1 = t1 if t1 < T14* and ic − ia − ib ≠ 0
T1 is found by solving the optimal problem:
Suitable sequence of states and their corresponding
( ΔE ) 2 ⎯⎯⎯→
0 ≤ T1 ≤ t1
min intervals:
Or
T t t t −T
2 V11 1 → V3 3 → V2 2 → V12 1 1 →
Edc t1 (ib + ic ) + t3ib 2 2 2 2
2 − VC ,low + C + C +
t t T
( ΔE ) = ⎯⎯⎯→ min
2 up low
→ V2 2 → V3 3 → V11 1
(ia − ib − ic ) 0 ≤ T1 ≤ t1
2 2 2
+ T1
Cup + Clow 3) When Vs rotates in triangle 3
If the coefficient of T1 happens to be zero (i.e. T1 and T2 are found by solving the optimal problem:
ia − ib − ic = 0), then ( ΔE ) 2 does not depend on T1, that means Edc t1ic + t2 (ib + ic ) + t3ib
2
any value of T1 in the interval [0; t1] can be a solution to 2 − VC ,low + Cup + Clow
+
minimize ( ΔE ) 2 , and T1 = t1 2 is chosen for a smooth 2
( ΔE ) = ⎯⎯⎯⎯ → min
switching pattern. ia + ib − ic ia − ib − ic 0 ≤T1 ≤ t1
0 ≤T2 ≤ t2
+ T1 + T2
Cup + Clow Cup + Clow
If T1’s coefficient is not zero, then ( ΔE ) 2 is a quadratic
function of T1 .
Let Let
Edc
2 − VC ,low ( Cup + Clow ) + t1ic + t2 (ib + ic ) + t3ib
Edc
2 − VC ,low ( Cup + Clow ) + t1 (ib + ic ) + t3ib
T12* = − T13* = −
ia − ib − ic ia + ib − ic
Edc
(The index “2” in T12* denote triangle 2) 2 − VC ,low ( Cup + Clow ) − t1 (ib + ic ) − t3ib
The optimal solution of T1 is: T23* = −
ia − ib − ic
T1 = 0 if T12* ≤ 0 The solution of T1 is:
T1 = T12* if 0 < T12* ≤ t1
T1 = t1 if t1 < T12*
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T1 = t1 2 if ia + ib − ic = 0 T3 = t3 3 if ia + ib + ic = 0
T1 = 0 if T13* ≤ 0 and ia + ib − ic ≠ 0 T3 = 0 if T31* ≤ 0 and ia + ib + ic ≠ 0
T1 = T13* if 0 < T13* ≤ t1 and ia + ib − ic ≠ 0 T3 = T31* if 0 < T31* ≤ t3 and ia + ib + ic ≠ 0
T1 = t1 if t1 < T13* and ia + ib − ic ≠ 0 T3 = t3 if t3 < T31* and ia + ib + ic ≠ 0
The solution of T2 is: Suitable sequence of states and their corresponding
intervals:
T2 = t2 2 if ia − ib − ic = 0
t −T T T T
T2 = 0 if T23* ≤ 0 and ia − ib − ic ≠ 0 V33 3 3 → V11 1 → V21 2 → V31 3 →
2 2 2 2
T2 = T2* if 0 < T23* ≤ t2 and ia − ib − ic ≠ 0
t −T t −T t −T
T2 = t2 if t2 < T23* and ia − ib − ic ≠ 0 → V12 1 1 → V22 2 2 → V32 3 3 →
2 2 2
Suitable sequence of states and their corresponding t −T t −T T
intervals: → V22 2 2 → V12 1 1 → V31 3 →
2 2 2
T T t T T t −T
V21 2 → V11 1 → V3 3 → → V21 2 → V11 1 → V33 3 3
2
2
2 2 2 2
t −T t −T t −T
→ V22 2 2 → V12 1 1 → V22 2 2 → III. SIMULATION RESULTS
2 2 2
To test the validity of this SVPWM strategy, the three-
t T T level NPC converter is used to feed a three-phase RL wye-
→ V3 2 → V11 1 → V21 2
2 2 2 connected load. The tests are conducted under the purposely
4) When Vs rotates in triangle 1 unbalanced condition of all DC link capacitors and three
T1, T2, and T3 are found by solving the optimal problem: phase loads. All system parameters are shown is table 1.
2
Edc t (i + i ) + t2 ic TABLE I. SYSTEM PARAMETERS
− VC ,low + 1 c b +
2 Cup + Clow Parameter Symbol Value
i −i −i i +i −i DC link voltage E dc 1200 V
(ΔE )2 = a b c T1 + a b c T2 + ⎯⎯⎯⎯ → min Output voltage and frequency Vs 600 V
Cup + Clow Cup + Clow 0 ≤T1 ≤ t1
0 ≤T2 ≤ t2
Output voltage frequency 50 Hz
0 ≤ T ≤
3 3t fs
i +i +i Sampling frequency f svm 16 kHz
+ a b c T3
Cup + Clow Upper capacitor Cup 90 μF
Let Lower capacitor C low 110 μF
Inductance of phase a and c loads La , L c 10 mH
Edc
2 − VC ,low ( Cup + Clow ) + t1 (ic + ib ) + t2ic Inductance of phase b load Lb 11 mH
T11* = − Resistance of phase a and c loads R a, R c 10 Ω
ia − ib − ic Resistance of phase b load Rb 11 Ω
dc
E
2 − VC ,low ( Cup + Clow ) + t1 (ic + ib ) + t2ic
Output voltage of phase a and three phase currents are
* completely in accordance with the theory of three-level NPC
T21 = − converter as shown in Fig. 4 and Fig. 5.
ia + ib − ic
Edc
2 − VC ,low ( Cup + Clow ) + t1 (ic + ib ) + t2ic
T31 = −
*
ia + ib + ic
The solution of T1 is:
Phase a voltage (V)
T1 = t1 2 if ia − ib − ic = 0
T1 = 0 if T11* ≤ 0 and ia − ib − ic ≠ 0
T1 = T11* if 0 < T11* ≤ t1 and ia − ib − ic ≠ 0
T1 = t1 if t1 < T11* and ia − ib − ic ≠ 0
The solution of T2 is:
T2 = t2 2 if ia + ib − ic = 0
T2 = 0 if T21* ≤ 0 and ia + ib − ic ≠ 0
T2 = T21* if 0 < T21* ≤ t2 and ia + ib − ic ≠ 0
T2 = t2 if t2 < T21* and ia + ib − ic ≠ 0
The solution of T3 is: Fig. 4. Phase a voltage of converter
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Neutral point voltage of method i
(a) method i
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