DEPARTMENT OF PHYSICS

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA

PH 705 : ELECTRONICS LABORATORY

Laboratory Manual
By
Dr. M.N. Satyanarayan

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 CONTENTS

S. No. Name of the experiment Page

No.
1. Introduction to the laboratory, course plan, evaluation scheme 2
and general instructions.

2. Experiment No. 1: Operational Amplifier based Integrator 4

and Differentiator

3. Experiment No. 2 : 555 Timer and its applications 9

4. Experiment No. 3 : Schmitt Trigger, Logarithmic and Anti- 14

Logarithmic Amplifiers

5. Experiment No. 4: RC Phase Shift, Colpitts and Hartley 18

Oscillators

6. Experiment No. 5: Frequency response of Active Low Pass 23

and High Pass Filters

7. Experiment No. 6: Frequency response of Active Band Pass 27

and Band Reject Filters

8. Experiment No. 7: Verification of truth tables of various 31

types of logic gates, flip-flops
9. Experiment No. 8: Shift registers, Decade and Up/Down 33
counters

10. Appendix I – LM741 Data Sheet 39

11. Appendix – II – 555 Timer Data Sheet 44

12. Appendix III – Logic Gates Data Sheet 54

13. Appendix IV – Flip Flops Data Sheet 64

14. Appendix V – Shift Register and Counters Data Sheet 68

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 Introduction to the laboratory, general instructions course plan and
evaluation scheme

1. The laboratory runs from Monday to Thursday 2.00 PM to 5.00 PM. The total number
of students is divided into four batches, each batch approximately containing 6 - 8
students. Thus the first batch of 6-8 students will report to the lab on Monday, the
next 6-8 on Tuesday and so on.

2. All students are advised to report to the class on time on their allotted day.
Attendance will be taken in every class and it is mandatory to maintain a 75%
attendance.

3. You will be allotted experiments approximately two weeks after the semester begins.
The details of the experiment will be posted on the notice board outside the lab.

4. You are expected to come with preparation to the laboratory and are expected to ready
your circuit with minimal assistance from the laboratory staff. No student will be
permitted to come to the laboratory and then study his/her experiment.

5. The course plan and the evaluation scheme is provided in the next page. You must
bring with you a dedicated notebook with the circuit diagram of your experiment of
the day already prepared. After completing your experiment for the day, you must get
your notebook signed by the instructor.

6. After completion of your experiment, please place back all the components,
connecting wires in their respective places. Turn off the power supplies, multimeters,
oscilloscopes and other equipment before you leave your table.

7. You must also maintain a lab record in which you will prepare a final version of the
experiment with detailed procedure and your experimental observations. This record
will be evaluated.

8. All graphs wherever required must be computer generated. All best fit lines, if
applicable, must be done using a software and not manually.

9. Permission will not be given to complete an experiment in advance. At the same

time, absentees will stand to lose 50% marks for that experiment. However, they
can complete the pending experiment after they finish all the other experiments.

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 Course and Evaluation Plan
1. Course Code: PH 705
2. Course Title : ELECTRONICS LABORATORY
3. L-T-P : (0 – 0 – 3)
4. Credits : 2
5. Prerequisites: Nil
6. Course Instructor: Dr. M.N. Satyanarayan
7. Teaching Department: Physics

Objective: To enable the student to:

8. Build and test simple op-amp based integrator, differentiator and filter circuits.
9. To build a 555 timer circuit and study its applications.
10. To build and study Schmitt trigger, log and antilog amplifiers.
11. To verify the functioning of digital electronic ICs.

Skill Development of the students expected from the course:

1. Build various op-amp based circuits such as integrator, differentiator, Schmitt trigger,
high and low pass filters, bandpass and band rejection filters.
2. Exposure to 555 timer IC and its applications.
3. Using digital ICs in various applications such as shift registers, counters.

List of experiments (please refer to the table of contents):

Evaluation scheme:

S.No. Evaluation component Weightage

1. Regular experiments 40%

2. Final examination 60%

Prof. M.N. Satyanarayan

Course Instructor

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 EXPERIMENT NO 01

OP-AMP BASED INTEGRATOR AND DIFFERENTIATOR

Aim: To study the frequency response of an operational amplifier based integrator and
differentiator circuits and hence to find their cut-off frequencies.

The experiment consists of three parts. The first part is to study the frequency response of an
operation amplifier circuit in either inverting mode or non-inverting mode. Before starting
your work, refer to the Appendix-1 for op-amp data sheet.

Components Required:

Op-amp 741 (1), 1k resistor (1), 10 k resistor (1), connecting wires, a bipolar power supply 
12V, breadboard.

Part-1: to study the frequency response of an operational amplifier.

1. On a bread board, place the op-amp in the central portion which is marked as a

Fig. 1.1 : Breadboard on which you will make your circuit

(Source: https://components101.com/misc/breadboard-connections-uses-guide)

rectangle in the figure above. Locate the notch at the top of the IC and locate pins 1-4
on one side and 5-8 on the other side. Refer to the data sheet at the end of the manual.

2. Connect pin 4 of the op-amp to VEE (12V) and pin 7 to +VCC (+12V) of the DC
regulated multi output fixed power supply which is on your table. Ensure that the pins
are connected to the correct polarity or else the op-amp will get damaged.

3. Wire up the circuit as an inverting amplifier with a gain of 10. In order to do this you
need to connect a 1K resistor to pin 2 of the op-amp and a 10K resistor between pin 2
and pin 6 of the op-amp. Do not use very long wires. Wires must be neatly secured on
the breadboard.

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4. The signal input from the function generator is connected to pin 2 while pin 3 of the
op-amp, ground terminal of the function generator and the ground terminal of the
multi-output fixed power supply must be connected together.

5. Ensure all connections are done as mentioned above and turn on the power supply.

6. To start, you have to set the amplitude of the input signal (this is kept constant
throughout the experiment) to say, 200 mV sine wave. You can do this by connecting
a BNC cable from the function generator directly to, say, Channel 1 of the dual
channel oscilloscope. The oscilloscope volts/div for channel 1 must be correctly set so
as to read a 200 mV peak-to-peak voltage.

7. Feed the input signal to the pin 2 of the op-amp. You can set the frequency of the
input signal to say 1 kHz for this. Now connect the pin 6 of the op-amp through a
BNC cable to the channel 2 of the oscilloscope.

8. Observe the amplified signal on the oscilloscope. Measure the amplitude of the output
signal on the oscilloscope. Is the amplification as expected?

9. Without changing the input signal amplitude, change the frequency from say 100 Hz
to about 10 MHz at first without taking any reading to quickly check the frequency
response of the op-amp. Note the frequency beyond which the output signal amplitude
begins to reduce. This is the bandwidth of the op-amp.

10. Now for each frequency, measure the output signal voltage. You may go in larger
steps upto the frequency at which the output signal begins to reduce. Beyond this
frequency, go in smaller steps, each time noting the output signal voltage.

11. Make a tabular column as shown below:

Input voltage (Vi): _____

S.No. Frequency (Hz) Output Voltage (Vo/Vi) Gain(dB)

=20log10(Vo/Vi)

12. On a semi-log graph paper, plot the gain (in dB) as a function of frequency.
Determine the cut-off frequency from this graph.

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Part – 2: Integrator circuit

Components required: 10 k and 1 k resistors ( 1 each), 0.01 F capacitor (1), connecting

wires, a bipolar power supply  12V.

For an integrator or differentiator circuit, you will require two resistances and a capacitance.
Connect the operational amplifier as an integrator as shown in the following diagram.

Fig. 1.2: Op-amp based integrator circuit

(Source: https://www.electronics-tutorial.net/analog-integrated-circuits/op-amp-integrator/practical-
integrator/)

The transfer function for the integrator is given by,

Rf Rf
V0 R R
 
Vi (1  jR f C )   f 
1  j  
  fa 
1
where f a  . For all f  f a the gain Vo/Vi is a constant. Then,
2R f C

Rf
V R
Gain = 0 
Vi  f 
2

1   
 fa 
At f = fa, the gain is 0.707 of its low frequency value. This is called the cut-off frequency of
the integrator.

1. Choose a 0.01 F capacitor and resistor Rf of 10k and let R be 1k.

2. Repeat steps 6-12 as mentioned above. Plot a graph of gain (in dB) versus frequency
as semi- log graph. Calculate the 3-dB frequency from this graph and compare with
the theoretical value.

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Part – 3: Differentiator Circuit

Components required: Capacitors (1F and 0.1 F, 1 each), resistors 10k,1k – 1 each.
connecting wires, a bipolar power supply  12V.

For the differentiator circuit, you require two resistance and two capacitances. The op-amp is
to be wired as follows.

Fig. 1.3 Op-am based differentiator circuit

(Source: https://www.electronics-tutorial.net/analog-integrated-circuits/opampdifferentiator/practical-
differentiator/)

The transfer function for the differentiator is given by,

V0 jR f C1

Vi (1  jR f C f )(1  jR1C1 )

If we choose RfCf =R1C1, then,

jR f C1 j  f 
V0
    fa 
Vi (1  jR f C f ) 2 1   f 
 fb 

The gain therefore is,

f
V0 fa

Vi   f 2 
1    
  f b  

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 1 1
Here, f a  and f b  .
2R f C 2R1C1

Choose C1 = 1F and Cf = 0.1 F, with Rf = 10k and R1 = 1k. Carry out steps 6-12 as in part
– 1.

Calculate the two important frequencies of the differentiator as shown in the above figure.

For the integrator and differentiator experiments, you need to show separate tabular columns.

Part – 4: Observation of integrated and differentiated waveforms on the oscilloscope.

Integrator: Input a square waveform of a frequency that falls within the integrator
bandwidth. Observe the output waveform on the scope. Adjust the time base on the scope to
get clear 3-4 period of the input and output waveforms. Store the waveforms on your pen
drive.

Differentiator: Input a triangular waveform of a frequency that falls within frequencies fa

and fb as measured by you. Observe the output waveform on the scope. Adjust the time base
on the scope to get clear 3-4 period of the input and output waveforms. Store the waveforms
on your pen drive.

Now input a square wave to the differentiator. What do you observe? Why? Store the
waveforms on the pen drive.

You need to print all the waveforms and stick them on your record book.

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 EXPERIMENT NO 02

555 TIMER AND ITS APPLICATIONS

Aim: To prepare a circuit to study the square waveform generation using a 555 timer IC and
to obtain astable, monostable and bistable multivibrators.

Astable operation:

In this mode, the timer has no stable states and hence toggles between ON state and OFF state
indefinitely. One can add a switch from the power supply to turn on the timer or turn it off.
The basic circuit that enables one to generate a rectangular waveform using a 555 timer IC is
shown below. The data sheet for a 555 timer circuit is provided in Appendix – 2.

Fig. 2.1 – 555 Timer in astable mode

(Source: https://www.electronics-tutorials.ws/waveforms/555_oscillator.html)

Components required: One 555 timer IC, resistors 1k and 10k – 1 each, capacitances 0.1F
and 0.033F – 1 each, connecting wires, either a fixed 12 V dc power supply or a variable (5-
15 V) dc power supply, a BNC cable with alligator clips, an oscilloscope (Tek 2002B).

Choose C2 to be a small capacitance. Say 100 nF. Make all the connections as shown above.
The timing diagram is controlled by R1, R2 and C1. If T is the period of a pulse, then

T = TON + TOFF.

TON = 0.7*(R1+R2)*C1

TOFF = 0.7*R2*C1

Therefore,

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 T = 0.7x(R1+2*R2)xC1

The frequency of the desired waveform then is equal to,

f = 1/T = 1.44/( R1+2*R2)*C1

Choose a value of C1 say, 10 F. For a desired frequency, the resistance values can then be
determined such that R2 >> R1. Then the duty cycle, which is given by

TON
D
TOFF  TON

will be approximately 50%. If one chooses R2 to be ten times R1, then one gets approximately
50% duty cycle.

Before starting your experiment with timer, it is important to study the datasheet of the timer
IC given in Appendix – II (page 43).

Experimental Procedure:

1. Connect up the circuit as shown above. Use R1 = 1 k, R2 = 10 k and C1 = 0.1F.

2. Ensure that all pins are correctly connected. If you are using an electrolytic capacitor,
then the polarity has to be correctly observed.
3. Once all connections are ok, turn on the power supply. The timer IC works on a broad
range of voltages from 5 – 15 V dc. Set the voltage to say, 12 V.
4. Connect the oscilloscope to pin 3 of the timer and observe the waveform on the
oscilloscope. Set the trigger level correctly to observe a clear square wave pattern.
5. Measure the TON and TOFF of the square waveform from the scope. Compare it with
your calculations. Mention the measured and calculated values in your laboratory
record.

Monostable Mode:

The following circuit diagram of the timer ensures a monostable operation, in which the timer
spends a finite amount of time in the ON state and comes back to the OFF state. Therefore, it
has one stable state which is the OFF state.

The amount of time the timer stays in ON state is determined by the following equation.

  1.1* R * C

If C is chosen as 10 F then the value of R can be fixed if the amount of time the timer is to
stay ON is fixed.

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 Fig. 2.2 – Monostable multivibrator based on 555 timer
(Source: https://www.electronicshub.org/monostable-multivibrator-using-555-timer/)

Components required: One 555 timer IC, one each of 10 F and 0.01 F capacitors, a 100 k
resistor, connecting wires, a 5 V fixed dc power supply, a 5-15 V dc variable power supply, a
switch, connecting wires, a BNC cable with alligator clips, an oscilloscope (Tek 2002B)

Experimental Procedure:

1. Connect up the circuit as shown above. Notice that there is only one resistor required
here.
2. Choose a 10 F capacitor and carefully observing its polarity, place it in the circuit in
the appropriate position.
3. If a 1.1 sec ON time is required, then the value of the resistor can be calculated. Use
this resistance in the circuit.
4. To the pin 2, you have to connect a switch such that it can supply a “negative trigger”.
That is, the switch should be configured in such a way that in the closed position, it
passes 5V and in open position, it grounds. By doing so, you will provide a trigger
pulse to the pin 2.
5. After ensuring all the pins are correctly connected, turn on the power supply and set it
to 10 V if it is an INDOSAW variable power supply. If it is a fixed power supply, use
+12 V (+Vcc) and ground. CAREFUL: Do not connect anything to the -12 V
terminal.
6. Set the scope in appropriate time base. Provide the trigger from pin 2 and observe the
pulse on the scope.
7. Measure the TON of the pulse. Compare it with the predicted value. Store the
oscilloscope trace on your pen-drive.

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Bistable Mode:

In the bistable mode, the timer has two stable states, the ON state and the OFF state and can
remain in one of the states indefinitely until it is forced to change the state.

Fig. 2.3 – Bistable multivibrator circuit

(Source: https://circuitdigest.com/electronic-circuits/555-timer-bistable-multivibrator-circuit-diagram)

Components required: One 555 timer IC, one 0.01 F capacitor, 10 k resistors - two,
connecting wires, a 5-15 V dc variable power supply, two switches, BNC cable with alligator
clips, an oscilloscope (Tektronics 2002B) or an LED and a 220 ohm resistor.

Experimental procedure:

1. Connect up the circuits with the resistors and the capacitor as shown in the figure
above.
2. In place of the 9 V battery, you may use a variable 5-15 V dc power supply.
3. The experiment uses two switches S1 and S2 as shown in the figure.
4. The output from pin 3 may either be connected to a scope or to an LED through a 220
 resistor.
5. Trigger PIN 2 and Reset PIN 4 input are kept HIGH using two Pull-up resistors R1
and R2.
6. Now when Push button Switch S1 is pressed, Trigger PIN 2 gets grounded ( < Vcc/3)
and the lower comparator output becomes HIGH for a moment, which SETs the flip
flop and 555 output is HIGH.
7. 555 remains in this state until the Reset input, because now both the comparators are
at LOW.
8. Now when button S2 is pressed, it makes the Reset PIN LOW and Reset the internal
Flip flop and OUTPUT goes LOW.
9. So external trigger (PIN2) Sets the flip-flop and output Goes HIGH and Reset signal
(PIN4) Resets the flip-flop and output Goes LOW.

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10. You may either use the scope to take snapshot of your experiment and put it in your
record or connect an LED to the pin 3 via a 220  resistor. The other pin of LED goes
to ground.

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 EXPERIMENT NO. 03

SCHMITT TRIGGER, LOGARITHMIC AND ANTI-LOGARITHMIC

AMPLIFIERS

Aim:
1. To realize a Schmitt Trigger circuit based on operational amplifier circuit and to
determine the upper trigger point (UTP) and the lower trigger point (LTP)
experimentally.
2. To construct and study the output response of a logarithmic amplifier
3. To modify the above circuit and study to output response of an antilogarithmic
amplifier.

1. Schmitt Trigger:

A Schmitt trigger is a regenerative comparator based on operational amplifier. They can be

made in both inverting as well as non-inverting modes. The input voltage is compared with
that determined by the circuit components. Whenever the input voltage increases beyond the
the level set by the circuit components, the output switches from its maximum positive level
to its maximum negative level. An inverting Schmitt trigger circuit is shown below.

Fig. 3.1 Inverting Schmitt trigger circuit.

(Source: https://www.electronics-tutorial.net/analog-integrated-circuits/schmitt-trigger/inverting-schmitt-
trigger/)

If the output voltage of the circuit is high, the voltage of the non-inverting terminal is

 Vo R 2
V R2 
R1  R2
If the input at the inverting terminal is below VR2 at the non-inverting input, the output
voltage is kept at its high positive level. For the output to switch to its low level the input

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voltage must exceed VR2 by a very small amount. The voltage at which this switch over from
positive high level to low happens is called at the Upper Trigger Point (UTP). Therefore,
 Vo R 2
UTP 
R1  R2

When the output is negative, the corresponding triggering voltage to cause a low to high
transition is called the Lower Trigger Point (LTP) and is given by

 Vo R 2
LTP 
R1  R2
Components Required: Normal breadboard, Op-amp 741(1), resistors 180 k (1) and 100
k (1), connecting wires, Tek 2002B scope.

Experimental procedure:

1. Choose the resistors R1= 180 k and R2 = 100k.

2. Connect the op-amp circuit will correct bias voltages at appropriate pins.
3. Select a sin waveform on the function generator and input it to the inverting pin of the
op-amp. Observe the input waveform simultaneously on the Channel 1 of the scope.
4. The output pin of the op-am is connected to the channel 2 of the Tek scope.
5. Observe the output waveform of the Schmitt trigger.
6. Determine the UTP and LTP from the waveforms on the screen.
7. Put the scope in XY mode.
8. Observe the hysteresis pattern on the screen.
9. Measure the UTP and LTP from the hysteresis and compare with your earlier
measurement.
10. Store the scope traces on your pen-drive.

2. Logarithmic Amplifier

A logarithmic amplifier results when one replaces the feedback resistor of an operation
amplifier circuit with a nonlinear component such as a diode or a transistor such as the one
shown below:

(a) (b)
Fig. 3.2 (a) A diode based log amplifier, (b) a transistor (such as BC107) based log amplifier
Source – (a) https://en.wikipedia.org/wiki/Log_amplifier#/media/File:Op-Amp_Logarithmic_Amplifier.svg
(b) https://en.wikipedia.org/wiki/Log_amplifier#/media/File:Logamp.JPG

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Consider the circuit shown in fig. 3.2 (a). The following equation is obtained by applying
KCL to the inverting node of the op-amp.

vi   qV  
 I s exp a   1
R   k BT  

which is

vi  qV 
 I s exp a 
R  k BT 

Taking log on both sides,

 V 
Va  Vo  VT ln  i 
 RI s 

where VT is the volt-equivalent of temperature and is about 0.0259 V at 25oC. Is is the reverse
saturation current in the diode which is typically on the order of nA. Therefore, the output
voltage is the negative natural logarithm of the input voltage. Hence, for various input
voltages, one can measure the output voltage across the diode.

3. Anti-logarithmic Amplifier

Fig. 3.3 below shows the antilogarithmic amplifier which is obtained by interchanging the
resistance and the diode of fig. 3.2(a).

Fig. 3.3 Circuit diagram for an anti-logarithmic amplifier

(Source:https://www.tutorialspoint.com/linear_integrated_circuits_applications/linear_integrated_circuits_app
lications_log_and_anti_log_amplifiers)

Again, applying the KCL to the above circuit, we get,

  qV   V
I s exp a   1   o
  k BT   Rf

which again is,

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 V 
 R f I s exp i   Vo
 VT 

Thus, the output voltage is proportional to the negative exponential of the input voltage.

Components Required: Op-amp IC (1), 1 k resistor (1), 1N4007 diode (1), bread-board
(1), connecting wires, Tek 2002B oscilloscope, 12 V or 15 V dc power supply, signal
generator.

Procedure for logarithmic amplifier:

1. On a breadboard, make the circuit connections as shown in fig. 3.2 (a). The
experiment can also be done with a transistor, but here, we choose a diode.
2. While connecting the op-amp to the 12 V or 15 V power supply, ensure that you
are connecting the correct pins of the op-amp to the power supply.
3. Turn on the power supply.
4. Set the input voltage to 1V. Note the output voltage across the diode.
5. Change the input voltage in steps of 0.5 V upto 20 V and record the corresponding
output voltage as shown in the sample tabular column below:

S.No. Input Voltage (Vi) Output Voltage (Vo)

6. Plot a graph of output versus input voltage.

Procedure for anti-logarithmic amplifier:

1. Interchange the diode and the resistor in the log-amplifier as shown in fig. 3.3 and
construct an antilog amplifier.
2. Following other instructions as given above, set the input voltage to 50 mV and
record the output voltage across the resistor.
3. Increase the input voltage in steps of 10 mV upto 500 mV and record the
corresponding output voltage.
4. Tabulate your observations in a similar table as shown above.
5. Plot the graph between the input and the output voltages.

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 EXPERIMENT NO. 04

RC PHASE SHIFT, COLPITTS AND HARTLEY OSCILLATORS

Aim: To design and demonstrate oscillators of various types – RC phase shift, Colpitt‟s and
Hartley‟s oscillators.

Components required:
Breadboard, resistors (3.3 k - 3, 100 k - 1, 10 k - 1), Inductance box, Capacitance box,
op-amp 741 – 1,  15 V fixed dc regulated power supply, connecting wires, Tek 2002B
oscilloscope.

4.1 RC Phase-Shift Oscillator

The circuit diagram of an RC phase-shift oscillator is shown in fig. 4.1 below.

Fig. 4.1 – Circuit diagram of an op-amp based RC phase shift oscillator

(Source: https://en.wikipedia.org/wiki/Phase-shift_oscillator)

An oscillator is a circuit with a positive feedback. The amplifier in an oscillator receives the
output from a network, amplifies it, phase shifts it by 180o and applies it to the network input.
The network phase shifts the output by another 180o and attenuates before feeding it back to
the amplifier input. The active component here can either be a transistor or an operational
amplifier. In this experiment, an operational amplifier is used to build the oscillator. The
resistances Rfb and R1 are the input and feedback resistances of the inverting amplifier, while
R1-R3 and C1-C3 form the phase shift feedback network.

The resistances R2 and R3 can be of equal or different value. Also, the capacitances C1 – C3
can all be either equal or different.

If R2 = R3 = R, and C1 = C2 = C3 = C, the oscillation frequency of the oscillator can be shown

to be given by,

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 1
f 
2RC 6

Therefore, in order to generate a particular frequency, the usual practice is to fix the value of
the capacitors first and then calculate the required resistances. The output of the oscillator can
be observed on a oscilloscope.

The feedback factor B, defined for the feedback network, is given by

vf
B
v0

where vf is the output voltage of the feedback section and vo is the input voltage to the
feedback section. One can also define a closed-loop gain ACL, which is given by,

v0
ACL 
vf
It can be shown that for a phase shift of 180o the feedback factor must be always 1/29. This
also implies that the close-loop gain must be at least 29. If this closed-loop gain is made less
than this, the oscillator will not oscillate and will not produce a sinusoidal output. For a
closed loop gain slightly larger than 29, the oscillator can give a reasonably pure sinusoid.

4.2 – Colpitts Oscillator

A Colpitts oscillator uses a feedback circuit that consists of two capacitors and one inductor.
The circuit diagram of an op-amp based Colpitt‟s oscillator is shown below.

Fig. 4.2 Op-amp based Colpitt’s oscillator

(Source: https://www.electronicshub.org/colpitts-oscillator/)

In this circuit, the capacitance-inductor network is the feedback circuit and is called as
Colpitt‟s tank circuit. If L is the inductance and C1 and C2 are the two capacitances, then the
frequency of oscillation of the circuit can be shown to be

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 1
f 
2 LCT
where CT is the series combination of C1 and C2 given by

C1C 2
CT 
C1  C 2

The feedback factor here is given by

C2
B
C1
The minimum closed-loop gain must then be equal to the reciprocal of the above. That is,

C1
ACL 
C2
Again, as in the RC phase-shift oscillator, the operational amplifier along with the feedback
resistor R2 and the input resistor R1 forms the inverting amplifier. Selecting the capacitor
values based on above discussion enables one to choose the inductance for a given oscillation
frequency. You will use the capacitance and inductance decade boxes provided to you for this
experiment.

4.3 – Hartley’s Oscillator

Hartley‟s oscillator uses two inductances and a capacitance as shown in the figure below.

Fig. 4.3 – Op-amp based hartley’s oscillator

(Source: https://www.electronicshub.org/hartley-oscillator/)

Again, the network to two inductances and one capacitance forms the tank circuit, whose
frequency of oscillation is given by

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 1
f 
2 CLT

where C is the capacitance and LT is the series inductance given by,

LT = L1 + L2 +M

Here, L1 and L2 are the two inductors while M is the mutual inductance term. This term
comes into picture if the inductances are wound on the same core. However, if the
inductances are separate elements then one can assume M to be zero. In this experiment, we
have two separate inductances and the mutual inductance between them is zero.

The feedback factor and the closed loop gain are then given respectively by

L1
B
L2
and
L2
ACL 
L1

4.4 - Experimental Procedure:

4.4.1 RC phase-shift oscillator:

1. Connect the circuit on a normal breadboard as shown in fig. 4.1. Use a 100 k
resistor (Rfb) for op-amp feedback and a 10 k for R1 to the inverting input of the op-
amp.
2. Connect the +Vcc and –VEE pins of the op-amp to the respective terminals of the bias
power supply and ground the non-inverting terminal of the op-amp.
3. Ensure first that the op-amp is functioning as an inverting amplifier by feeding in a
sine-wave of say 1 kHz frequency and 1V amplitude.
4. Connect the output pin of the op-amp to the oscilloscope and configure it to a proper
display.
5. You must be able to observe the appropriate output waveform on the scope. If so, then
the op-amp is working properly.
6. Switch off the bias supply. Now assemble the RC phase shift network. Connect the
phase-shift network to the op-amp circuit. Choose C = 0.01 F and R = 3.3 k.
7. Theoretically calculate the oscillation frequency. Note down the theoretical value.
8. Turn on the bias power supply to the op-amp.
9. You must be able to observe the sine-wave output. Configure the display to clearly
show the output sine waveform. On the display, at the right side bottom the scope will
display the frequency of the generated sine-wave. Note down the value.
10. Store the trace in your pen-drive.
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 11. Now choose C = 0.1F. Repeat steps 6-11 as mentioned above.
12. Record your observations in the following form

S. No. Capacitance Resistance f (Hz) f (Hz),

(F) (k) (Theoretical) (Measured)

4.4.2 Colpitt’s Oscillator

1. Carry out the step 1 – 5 as mentioned in subsection 4.4.1.

2. This time, use the capacitance and inductance decade boxes provided to you. Choose
L = 110 mH, C1 = 100 nF and C2 = 1 nF.
3. Calculate the theoretical oscillation frequency.
4. Power up the circuit and observe the waveform on the oscilloscope. Configure it for
appropriate display.
5. Note down the measured oscillation frequency.
6. Change the capacitor or the inductance value to generate a new waveform.
7. Make a similar table of observations as above.

4.4.3 Hartley’s Oscillator

1. Carry out the step 1 – 5 as mentioned in subsection 4.4.1.

2. For this experiment also use the capacitance and inductance decade boxes provided to
you. Choose L1 = 10 mH, L2 = 1 mH and C = 1 nF.
3. Calculate the theoretical oscillation frequency.
4. Power up the circuit and observe the waveform on the oscilloscope. Configure it for
appropriate display.
5. Note down the measured oscillation frequency.
6. Change the capacitor or the inductance value to generate a new waveform.
7. Make a similar table of observations as above.

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 EXPERIMENT NO. 05

FREQUENCY RESPONSE OF ACTIVE LOW AND HIGH PASS FILTERS

Aim: To obtain the frequency response of an active low-pass and high pass filters and
determine the respective cut-off frequencies.

Components required:

Normal Breadboard – 1, op-amp 741 – 3, resistances (10k - 1, 1k - 1), capacitors (0.1F –
1, 0.001F – 1, 12 V dc regulated power supply.

5.1 Second Order Active Low-Pass Filter (LPF):

Fig. 5.1 below shows the circuit of an active LPF circuit. The circuit consists of a passive low
pass filter at the inverting input of an op-amp circuit. This circuit is called Sallen-Key low-
pass filter circuit. While the gain of the circuit is set by choice of R1 and R2, the cut-off
frequency of such a circuit is set by R1 and C1. Again, using simple circuit theory, it is
possible to show that the cut-off frequency of such a filter is given by,
1
f 
2 R3 R4 C1C 2

Fig. 5.1 A second-order active low-pass filter

(Source: https://www.electronicshub.org/active-low-pass-filter/)

If R3 = R4 = R and C1 = C2 = C, then the cut-off frequency is,

1
f 
2RC

For a desired cut-off frequency and for a given value of capacitance, the above equation is
used to determine the required resistance.

5.2 Second-Order Active High Pass Filter (HPF)

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Fig. 5.2 shows a second-order active high pass filter, which is again a Sallen–Key circuit. As
can be seen, when compared to fig. 5.1, the positions of the capacitors and resistors forming
the LPF are interchanged to make it an HPF.

Fig. 5.2 Active second order high-pass filter

(Source: https://www.electronicshub.org/active-high-pass-filter/)

Again, the circuit gain is set by the resistors R1 and R2 while the high pass action is decided
by the resistors R3, R4 and capacitors C1 and C2. The cut-off frequency of such a filter is again
given by the same expression as for the LPF. Thus, R3 = R4 = R and C1 = C2 = C, then the
cut-off frequency is again given by,

1
f 
2RC

5.3 Experimental Procedure:

5.3.1 Second order LPF

1. Make the circuit connections as shown in fig. 5.1. Use R2 = 10 k and R1 = 1 k.
2. Select C = 0.01F, and for a design frequency of 1 kHz, determine the value of R from the
above equation.
3. Choose the nearest available value from the component board in the laboratory.
4. Connect the bias supply to the appropriate pins of the op-amp circuit.
5. Turn on the function generator and measure the output of the generator directly on the
oscilloscope. Set the amplitude to 1 V peak-to-peak. This is the input signal amplitude
which will be kept constant throughout the measurement.
6. Now connect the function generator as the input to the filter circuit.
7. Ensure that all the grounds are connected together to a common ground (bias power
supply ground).
8. Connect the pin 6 of the op-amp to the Tek 2002B scope.

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9. Set the display appropriately and measure the output peak-to-peak voltage. It is a good
idea to ensure that the circuit is working correctly. In order to ensure this quickly, change
the frequency over all the ranges without taking any readings and see the output voltage
amplitude.
10. The output voltage will remain unchanged upto a certain frequency and then begin
decreasing as the frequency further increases. Once this is ensured, you can start taking
readings. Note the frequency when there is a perceptible change in the output voltage.
11. Now vary the frequency in steps of 10 Hz upto 1 kHz. In the region where the output
voltage remains constant, you may take reading in larger steps. Around the frequency
when the output voltage is expected to reduce, you need to take readings in finer steps in
order to have more data points.
12. Plot a graph between frequency f and 20*log(Vo/Vi). From this graph, readout the value
on y-axis for which the frequency response is flat.
13. From this value on the y-axis, come down by 3-dB. Mark out the corresponding
frequency on the graph. This is the measured cut-off frequency.

Observations:

Input Signal Amplitude (Vi): ________

S.No. Frequency (Hz) Vo (V) 20log(Vo/Vi)

3 dB cut-off frequency from the graph:_______

3 dB cut-off frequency from the formula:_______

5.3.2 Second-Order HPF

1. You will use the circuit as in fig. 5.2.

2. Choose C1=C2=0.1F, R3=R4=2k. Also, R1 = 10 k and R2 = 1 k.
3. Wire up all the components as shown in the circuit diagram. Connect all the ground points
to a single ground.
4. Select an input signal amplitude of 1 V peak-to-peak as done in the previous part (see item
5 for LPF) and connect the pin 6 of the op-amp to the Tek 2002B scope.
5. Start from a low frequency of 10 Hz or so and in steps of 10 Hz take readings upto a point
where the amplitude on the oscilloscope shows no further change.
6. Beyond this frequency, you can go in larger steps.
7. Plot a graph between frequency f and 20*log(Vo/Vi). From this graph, readout the value on
y-axis for which the frequency response is flat.
8. From this value on the y-axis, come down by 3-dB. Mark out the corresponding frequency
on the graph. This is the measured cut-off frequency.

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Observations:

Input Signal Amplitude (Vi): ________

S.No. Frequency (Hz) Vo (V) 20log(Vo/Vi)

3 dB cut-off frequency from the graph:_______

3 dB cut-off frequency from the formula:_______

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 EXPERIMENT NO. 06

FREQUENCY RESPONSE OF ACTIVE BANDPASS AND BAND-REJECT FILTERS

Aim: To obtain the frequency response of an active band-pass filter and determine the cut-off
frequencies, bandwidth and quality factor.

Components Required: 1k and 10k resistor modules, 0.1F and 0.001F capacitors,
connecting cables, Indosaw function generator and Tek 2002B oscilloscope.

6.1 Active Bandpass Filter:

An active bandpass filter is a bandpass filter which is implemented using op-amps. A

bandpass filter passes a range of frequencies with minimal attenuation that fall within its
passband. Fig. 6.1 below shows the layout of an op-amp based bandpass filter.

Fig. 6.1 Bandpass filter with an op-amp

(Source: https://www.electronics-tutorials.ws/filter/filter_7.html)

It is easily seen that the input stage to the non-inverting terminal of the op-amp is a high-pass
filter while the output of the op-amp drives a low pass filter. Again, using simple circuit
analysis techniques, it can be easily shown that there are two cut-off frequencies for such a
filter. The lower (fL) and upper (fH) cut-off frequencies of the filter are respectively given by,

1 1
fL  , fH 
2R1C1 2R2 C 2

The passband of the filter is then, given by, fH fL.

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6.2 Active Band Reject Filter:

In contrary to a band pass filter, a band-stop or a band-reject filter drops a range of

frequencies from passing through it while offering minimal attenuation to other frequencies.
Fig. 6.2 below shows the circuit for an active band reject filter. Note here that the LPF and
HPF sections are given to a summing amplifier, at whose input are the low-pass and high-
pass responses. The summing amplifier then simply adds the two responses thereby
providing overall, a band-reject filter.

Fig. 6.2 An op-amp based band-reject filter

(Source: https://www.electronics-tutorials.ws/filter/band-stop-filter.html)

The values of the resistances and capacitances can be chosen using the formulae for the
respective cut-off frequencies as already mentioned in the previous section. For a band-reject
filter, the cut-off frequency for the LPF section has to be lower than that of the HPF section.

6.3 Experimental Procedure:

6.3.1 Bandpass Filter

1. Choose R1 = 1 k, C1 = 0.1 F, R2 = 10 k , C2 = 0.001F such that the pass-band

gain (R2/R1) is 10.
2. Wire up the circuit as shown the fig. 6.1. Connect the op-amp bias power supply.
3. Connect a function generator, select sine-wave output and set the amplitude of the
sine-wave as 1 V.
4. Connect the Tek 2002B oscilloscope to the output of the low pass filter (see fig. 6.1).
5. Without noting any readings, quickly change the frequencies through all the ranges
and note the circuit response. Then amplitude of the output sine-wave should increase
as the frequency increases and then decrease on further increase in the frequency.

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 6. Note the frequency where the change in the output sine-wave amplitude reduces
considerably. This approximately is the lower cut-off frequency. Likewise, note the
upper cut-off frequency.
7. Now start taking the readings strtig from 0.1kHz to 1.0 kHz in steps of 0.1 kHz, from
1.0 kHz to 5 kHz in steps of 1 .0 kHz and then onwards in steps of 10 KHz upto 100
kHz.

Observations:

Input Signal Amplitude (Vi): ________

S.No. Frequency (Hz) Vo (V) 20log(Vo/Vi)

3 dB cut-off frequency from the graph:_______

3 dB cut-off frequency from the formula:_______

6.3.2 Band-Reject Filter

1. Choose RLP = 8 k, CLP = 0.1 F, RHP = 2k , CHP = 0.1F. Also choose the
resistances R at the inverting terminal input of the summing amplifier as 1 k and the
feedback resistor of the summing amplifier as 10k.
2. Wire up the circuit as shown the fig. 6.2. Connect the  15V op-amp bias power
supply.
3. Connect a function generator, select sine-wave output and set the amplitude of the
sine-wave as 1 V.
4. Connect the Tek 2002B oscilloscope to the output of the summing amplifier (see fig.
6.2).
5. Without noting any readings, quickly change the frequencies through all the ranges
and note the circuit response. The amplitude of the output sine-wave should decrease
as the frequency increases and then increase on further increase in the frequency.
6. Note the frequency where the output sine-wave amplitude reduces considerably. This
approximately is the lower cut-off frequency. Likewise, note the approximate upper
cut-off frequency.
7. Now start taking the readings starting from 30 Hz to 2.0 kHz in steps of 50 Hz. Note
the output voltage each time. Tabulate your observations as given in the next page.

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Observations:

Input Signal Amplitude (Vi): ________

S.No. Frequency (Hz) Vo (V) 20log(Vo/Vi)

3 dB cut-off frequency from the graph:_______

3 dB cut-off frequency from the formula:_______

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 EXPERIMENT NO. 07
LOGIC GATES AND FLIP-FLOPS

Aim: To understand the operation of various types of logic gates and flip-flops and verify
their truth tables.

Components required: Indosaw breadboard, logic gate modules (OR, AND, NOR, NAND,
XOR), S-R, J-K, and D- flip flop modules, clock pulse module, +5V fixed dc power supply,
connecting cables.

Digital electronics experiments largely require one to go through the data sheets of respective
digital ICs. The data sheets of all the ICs required for this experiment are attached overleaf.
The students are advised to study the data sheets and pay attention to the truth tables given
therein. In all the digital electronics experiment, you will have to call the laboratory staff to
certify your outputs on the breadboard.

8.1 Experimental Procedure for logic gates:

1. Place a logic gate module on the Indosaw breadboard. The module already has LEDs
at the inputs and the output ports.
2. Now for a given logic gate, verify the truth table by connecting the inputs
appropriately.
3. Complete the verification of the truth tables of all the logic gates given to you.
4. Tabulate your observations as shown below.

Observations for logic gates:

OR Gate: AND Gate: NOR Gate:

Input Input Output Input Input Output Input Input Output
A B A B A B

NAND Gate: XOR Gate:

Input Input Output Input Input Output
A B A B

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8.2 Experimental Procedure for Flip-Flops

8.2.1 R-S flip flop

1. The flip-flop family of ICs are essentially clocked devices. Therefore, in order to
verify the operation of the flip-flops, you will also need a clock pulser module and,
along with it, the flip-flop module, Indosaw breadboard, bias supply and connecting
cables.
2. For R-S flip-flop, make the connections as indicated on various ports of the module.
Refer to the truth table for R-S flip flop given in page no. . Ensure all ground are
connected to one common ground.
3. Verify the truth table by connecting the R and S inputs as per the truth table. Unless
the clock is pulsed, there will be no change in the state of the flip flop when either R
or S is HIGH.

8.2.2 J-K Flip Flop:

1. Place the J-K flip-flop module on the breadboard and carry out all the connections as
indicated in the module. Ensure all grounds are connected to one common ground.
2. Verify the truth table and note that each time the J and K inputs change, the clock has
to be pressed for the flip-flop to change its state.

8.2.3 D Flip-Flop:

1. Connect the D flip-flop module to the clock module and the 5 V power supply.
Connect the ground points to a common ground as mentioned earlier.
2. Verify the truth table of the D-flip-flop by giving single clock pulses each time the
input state changes.

Observations:

R-S Flip Flop: D Flip-Flop: J-K Flip Flop:

Clock S R Q Q‟ Clock D Q Q‟ Clock J K Q Q‟

0 0 0

  

  

  

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 EXPERIMENT NO. 08

SHIFT REGISTERS, DECADE AND UP-DOWN COUNTERS

Aim: To understand the operation and verify the truth tables of Shift Register 74LS164,
Decade Counter 74LS90, 4-bit Up/Down Counter 74LS163.

Components Required: Fixed 5V dc supply, one 74HC164 chip, one 7490 chip, one
74LS193 chip, eight 470  resistors, eight LEDs, breadboard, connecting wires, clock pulser.

8.1 Shift Register:

The IC 74LS164 is an 8-bit serial-to-parallel shift register. Fig. 8.1 below shows the pin
diagram of a 74HC164 8-bit shift register and the data sheet of the IC is given on page no. 50.

Fig. 8.1 Pin Diagram of 74HC164

(Source: https://www.instructables.com/id/The-74HC164-Shift-Register-and-your-Arduino/)

Pins A and B are connected through an AND gate internally and are the serial data input pins.
Of the two, one has to be held HIGH while the serial data has to be applied to the other pin.
Pins 3-6 and 10-12 (Q0-Q7) are the output pins. Pin 9 is the CLEAR pin that is active LOW.

Experimental Procedure:

1. You can use a normal breadboard to set the experiment up. You can use an Indosaw
breadboard to set up the clock pulse module next to it.
2. To start with, it is important to set pin 9 to LOW so that contents of all the output data
pins are set to LOW. Thereafter this pin should be made HIGH.
3. Data can then be entered serially through either A or B, while holding the other
HIGH. The output data on the LEDs should be recorded for different sets of input
bits.

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 4. Each time the entered bit will be sent to the output only upon receipt of a clock pulse.
For this purpose, you have been provided with a pulser circuit to generate a single
clock pulse of 1 sec duration.
5. Make a tabular column of input 8-bit pattern and the Q0-Q7 outputs. You must call
one of the laboratory staff and demonstrate the input bit pattern and corresponding
lighting of the LEDs at the output ports. Insert a 470  resistances between each data
output pin and the LED.
6. If the output of a given pin is HIGH, mark it as „H‟ in your table else mark it as „L‟.
This must correspond to the input 8-bit pattern.

8.2 Decade Counter:

74LS90 is a 4-bit decade counter which counts from 0000 (decimal 0) to 1001 (decimal 9)
and resets and is a negative edge triggered device. You will do this experiment on the
Indosaw breadboard.

Components Required: Fixed 5V dc supply, 74LS90 chip module, Indosaw breadboard,

connecting cables, clock pulser module.

The following figure shows the pin diagram of a 74LS90 chip.

Fig. 8.2 7490 4-bit decade counter

(Source: http://www.learnerswings.com/2014/10/control-common-cathode-seven-segment.html)

Consider the datasheet of 74LS90 given in page no. 52. The truth table of the device
mentions that to enable the counter to start the counting process, the pins 2,3,6,7 and 10 have
to be held LOW. This is already done in the module given to you.

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 Fig. 8.3: Pin connections to 7490
(Source: https://www.electronics-tutorials.ws/counter/bcd-counter-circuit.html).

Experimental Procedure:

1. Use a normal breadboard and place the 7490 chip as shown in fig. 1.1 on page 5 of
this manual such that the pins are on either side of the center divider.
2. Connect pins 2,3,6,7 and 10 together and connect them to the power supply ground.
3. Also connect pin 1 and 12 together.
4. Connect the positive terminal of the power supply to pin 5.
5. The clock pulser is connected to pin 14.
6. The pins 12, 11, 9 and 8 are the output pins. Connect one LED to each of these pins
through a 470  resistor.
7. Once the chip is power up, at each clock pulse, it will count. Refer to the truth table
provided in the data sheet of 7490 on page .
8. Your experimental output has to be validated by the laboratory instructor. Notify the
instructor to inspect the performance of your counter.

Observations:

Prepare your observations in the following format.

Clock QD (11) QC (8) QB (9) QA (12)

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8.3 Up/Down Counter

74LS193 is a 4-bit synchronous binary counter with dual clock. The data sheet for this IC is
given in page of Appendix IV. The counter when loaded with bits can count either up or
down depending on the way it is configured. If for example one loads 1111 as the four bits
and provides the clock to pin 4 while holding pin 5 HIGH, then the counter will decrement
from 1111 (decimal 15) to 0000 (decimal 0) successively at every clock pulse. Similarly, if
0000 is loaded into the counter and pin 5 is clocked while holding pin4 HIGH, the counter
will count upwards from 0000 to 1111 successively at every clock pulse.

Fig. 8.3: Pin diagram of 74LS193

(Source: http://www.datasheet-pdf.info/entry/74LS193-datasheet)

A detailed datasheet of the IC is available in Appendix-V page no. 72. Data can be loaded
into pins 1, 15, 10 and 9. Before loading the data, pin 11 (preset) has to be made LOW and
then the data loaded. Once the data is loaded, pin 11 is then made HIGH.

Experimental Procedure:

1. Wire up 74LS193 consulting the datasheet. No connections are to be made to pins 12

and 13.
2. Connect LEDs to pins 2, 3, 6 and 7 through 470  resistances.
3. Make the pin 11 LOW in order to load data into the counter.
4. Let the data be, say, 1111, that is, pin 1, 15, 10 and 9 are all HIGH.
5. Now the data is loaded into the counter. Next make pin 11 HIGH.
6. Connect the clock to pin 4 while holding the pin 5 HIGH.
7. Notice with each clock pulse, the LEDs light in a sequence that shows a count down.
QA is the least significant bit (LSB) while QD is the most significant bit (MSB).
8. Next, following step 3, load the counter with 0000 and connect the clock to pin 5
instead, while holding pin 4 HIGH.
9. With each clock pulse, observe the LEDs lighting up in sequence which shows count
up.

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Observations:

Prepare your observations in the following format. Again, you output must be validated by
the laboratory staff as you fill in the data in the following table.

Clock QD (7) QC (6) QB (2) QA (3)

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IC DATASHEETS

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Appendix - I

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Appendix – II

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Appendix – III

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 Appendix - IV

Note: The following datasheet shows S-R latch which is active LOW. But in the experiment you are
using active HIGH. Your inputs then are complementary to what is given in the datasheet.

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Appendix - V

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