CAT5132

16 Volt Digital
Potentiometer (POT)
with 128 Taps
and I2C Interface
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Description
The CAT5132 is a high voltage digital POT with non-volatile wiper
setting memory, operating like a mechanical potentiometer. The tap
points between the 127 equal resistive elements are connected to the
wiper output via CMOS switches. The switches are controlled by a
7-bit Wiper Control Register (WCR). The wiper setting can be stored MSOP−10
Z SUFFIX
in a 7-bit non-volatile Data Register (DR). The WCR is accessed via
CASE 846AE
the I2C serial bus.
Upon power-up, the WCR is set to mid-scale (1000000). After the MARKING DIAGRAM
power supply is stable, the contents of the DR are transferred to the
WCR and the wiper is returned to the memorized setting.
The CAT5132 has two voltage supplies: VCC, the digital supply and ANBx
V+, the analog supply. V+ can be much higher than VCC, allowing for YMR
16 V analog operations.
The CAT5132 can be used as a potentiometer or as a two-terminal
variable resistor.
ANBU = CAT5132ZI-10-GT3
Features ANBK = CAT5132ZI-50-GT3
ANBP = CAT5132ZI-00-GT3
 Single Linear Digital Potentiometer with 128 Taps Y = Production Year (Last Digit)
 End-to-end Resistance of 10 kW, 50 kW or 100 kW M = Production Month (1-9, A, B, C)
R = Production Revision
 I2C Interface
 Fast Up/Down Wiper Control Mode PIN CONFIGURATION
 Non-volatile Wiper Setting Storage SDA 1 SCL
 Automatic Wiper Setting Recall at Power−up GND V+
 Digital Supply Range (VCC): 2.7 V to 5.5 V VCC RL
A1 RW
 Analog Supply Range (V+): +8 V to +16 V
A0 RH
 Low Standby Current: 15 mA
 100 Year Wiper Setting Memory (Top View)

 Industrial Temperature Range: −40C to +85C ORDERING INFORMATION

 10-pin MSOP Package Device Package Shipping†
 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS CAT5132ZI−10−GT3
Compliant MSOP 3,000 /
CAT5132ZI−50−GT3
(Pb−Free) Tape & Reel
Applications CAT5132ZI−00−GT3
 LCD Screen Adjustment †For information on tape and reel specifications, in-
 Volume Control cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications Bro-
 Mechanical Potentiometer Replacement chure, BRD8011/D.
1. For detailed information and a breakdown of
 Gain Adjustment device nomenclature and numbering systems,
 Line Impedance Matching please see the ON Semiconductor Device No-
menclature document, TND310/D, available at
 VCOM Setting Adjustments www.onsemi.com.
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options,
please contact your nearest ON Semiconductor
Sales office.

 Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

July, 2013 − Rev. 7 CAT5132/D
 CAT5132

VCC V+

SDA 127
RH
SCL CONTROL LOGIC AND
A0 ADDRESS DECODE
A1

127 RESISTIVE

ELEMENTS
128 TAP POSITION
DECODE CONTROL
7−BIT
7−BIT WIPER
NONVOLATILE
CONTROL
MEMORY
REGISTER
REGISTER
(WCR)
(DR)
0
RL

Figure 1. Block Diagram RW

Table 1. PIN FUNCTION DESCRIPTION

Pin No. Pin Name Description
1 SDA Serial Data Input/Output − Bidirectional Serial Data pin used to transfer data into and out of the CAT5132.
This is an Open-Drain I/O and can be wire OR’d with other Open-Drain (or Open Collector) I/Os.

2 GND Ground
3 VCC Digital Supply Voltage (2.7 V to 5.5 V)
4 A1 Address Select Input to select slave address for I2C bus.
5 A0 Address Select Input to select slave address for I2C bus.
6 RH High Reference Terminal for the potentiometer
7 RW Wiper Terminal for the potentiometer
8 RL Low Reference Terminal for the potentiometer
9 V+ Analog Supply Voltage for the potentiometer (+8.0 V to 16.0 V)
10 SCL Serial Bus Clock input for the I2C Serial Bus. This clock is used to clock all data transfers into and out of
the CAT5132

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Value Unit
Temperature Under Bias −55 to +125 C
Storage Temperature −65 to +150 C
Voltage on any SDA, SCL, A0 & A1 pins with respect to Ground (Note 4) −0.3 to VCC + 0.3 V
Voltage on RH, RL & RW pins with respect to Ground V+
VCC with respect to Ground −0.3 to +6 V
V+ with respect to Ground −0.3 to +16.5 V
Wiper Current (10 sec) 6 mA
Lead Soldering temperature (10 sec) +300 C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −0.3 V to VCC +0.3 V.

Table 3. RECOMMENDED OPERATING CONDITIONS

Rating Value Unit
VCC +2.7 to +5.5 V
V+ +8.0 to +16 V
Operating Temperature Range −40 to +85 C

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 CAT5132

Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits

Symbol Parameter Test Conditions Min Typ Max Units

RPOT Potentiometer Resistance (100 kW) 100 kW
RPOT Potentiometer Resistance (50 kW) 50 kW
RPOT Potentiometer Resistance (10 kW) 10 kW
RTOL Potentiometer Resistance Tolerance 20 %
Power Rating 25C 50 mW
IW Wiper Current 3 mA
RW Wiper Resistance IW = 1 mA @ V+ = 12 V 70 150 W
IW = 1 mA @ V+ = 8 V 110 200 W
VTERM Voltage on RW, RH or RL GND = 0 V; V+ = 8 V to 16 V GND V+ V
RES Resolution 0.78 %
ALIN Absolute Linearity (Note 6) VW(n)(actual) − VW(n)(expected) (Notes 9, 10) 1 LSB
(Note 8)

RLIN Relative Linearity (Note 7) VW(n+1) − [VW(n) + LSB] (Notes 9, 10) 0.5 LSB
(Note 8)

TCRPOT Temperature Coefficient of RPOT (Note 5) 300 ppm/C

TCRatio Ratiometric Temperature Coefficient (Note 5) 30 ppm/C
CH/CL/CW Potentiometer Capacitances (Note 5) 10/10/25 pF
fc Frequency Response RPOT = 50 kW 0.4 MHz
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
7. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
8. LSB = (RHM − RLM)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal.
9. n = 1, 2, ..., 127
10. V+ @ RH; 0 V @ RL; VW measured @ RW with no load.

Table 5. D.C. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current FSCL = 400 kHz, SDA Open, 1 mA
(Volatile Write/Read) VCC = 5.5 V, Input = GND

ICC2 Power Supply Current FSCL = 400 kHz, SDA Open, 3.0 mA
(Nonvolatile WRITE) VCC = 5.5 V, Input = GND

ISB(VCC) Standby Current (VCC = 5 V) VIN = GND or VCC, SDA = VCC 5 mA

ISB(V+) V+ Standby Current VCC = 5 V, V+ = 16 V 10 mA
ILI Input Leakage Current VIN = GND to VCC 10 mA
ILO Output Leakage Current VOUT = GND to VCC 10 mA
VIL Input Low Voltage −1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 1.0 V
VOL1 Output Low Voltage (VCC = 3.0) IOL = 3 mA 0.4 V

Table 6. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5.0 V)

Symbol Parameter Test Conditions Min Max Units
CI/O Input/Output Capacitance (SDA) VI/O = 0 V (Note 11) 8 pF
CIN Input Capacitance (A0, A1, SCL) VIN = 0 V (Note 11) 6 pF

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 CAT5132

Table 7. A.C. CHARACTERISTICS

VCC = 2.7 − 5.5 V

Symbol Parameter (see Figure 6) Min Max Units

FSCL Clock Frequency 400 kHz
TI (Note 11) Noise Suppression Time Constant at SCL & SDA Inputs 50 ns
tAA SLC Low to SDA Data Out and ACK Out 1 ms
tBUF (Note 11) Time the bus must be free before a new transmission can start 1.2 ms
tHD:STA Start Condition Hold Time 0.6 ms
tLOW Clock Low Period 1.2 ms
tHIGH Clock High Period 0.6 ms
tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 ms
tHD:DAT Data in Hold Time 0 ns
tR (Note 11) SDA and SCL Rise Time 0.3 ms
tF (Note 11) SDA and SCL Fall Time 300 ns
tSU:STO Stop Conditions Setup Time 0.6 ms
tDH Data Out Hold Time 100 ns
11. This parameter is tested initially and after a design or process change that affects the parameter.

Table 8. POWER UP TIMING (Notes 12, 13)

Symbol Parameter Min Max Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms

Table 9. WIPER TIMING

Symbol Parameter Min Max Units
tWRPO Wiper Response Time After Power Supply Stable 5 10 ms
tWRL Wiper Response Time After Instruction Issued 5 10 ms

Table 10. WRITE CYCLE LIMITS

Symbol Parameter Min Max Units
tWR Write Cycle Time (see Figure 7) 5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

Table 11. RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units
NEND (Note 12) Endurance MIL−STD−883, Test Method 1033 100,000 Cycles
TDR (Note 12) Data Retention MIL−STD−883, Test Method 1008 100 Years
12. This parameter is tested initially and after a design or process change that affects the parameter.
13. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

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 CAT5132

TYPICAL PERFORMANCE CHARACTERISTICS

12 400
VCC = 2.7 V; V+ = 8 V
350
10 VCC = 5.5 V; V+ = 16 V VCC = 5.5 V
300
8
250
RWL (KW)

ICC2 (mA)
6 200 VCC = 2.7 V
150
4
100
2
50
0 0
0 16 32 48 64 80 96 112 128 −50 −30 −10 10 30 50 70 90 110 130
TAP POSITION TEMPERATURE (C)
Figure 2. Resistance between RW and RL Figure 3. ICC2 (NV Write) vs. Temperature

1.0 0.5
0.8 Tamb = 25C 0.4 Tamb = 25C
Rtotal = 10 K Rtotal = 10 K
0.6 0.3
ALIN ERROR (LSB)

ALIN ERROR (LSB)

0.4 0.2
0.2 0.1
0 0
−0.2 −0.1
−0.4 −0.2
−0.6 VCC = 2.7 V; V+ = 8 V −0.3 VCC = 2.7 V; V+ = 8 V
−0.8 VCC = 5.5 V; V+ = 16 V −0.4 VCC = 5.5 V; V+ = 16 V
−1.0 −0.5
0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128
TAP POSITION TAP POSITION
Figure 4. Absolute Linearity Error per Tap Figure 5. Relative Linearity Error
Position

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 CAT5132

tF tHIGH tR
tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO

SDA IN

tBUF
tAA tDH

SDA OUT

Figure 6. Bus Timing

SCL

SDA 8TH BIT ACK

BYTE n
tWR
STOP START ADDRESS
CONDITION CONDITION

Figure 7. Write Cycle Timing

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 CAT5132

SERIAL BUS PROTOCOL

The following defines the features of the I2C bus protocol: Acknowledge
1. Data transfer may be initiated only when the bus is After a successful data transfer, each receiving device is
not busy. required to generate an acknowledge. The acknowledging
2. During a data transfer, the data line must remain device pulls down the SDA line during the ninth clock cycle,
stable whenever the clock line is high. Any signaling that it received the 8 bits of data (see Figure 9).
changes in the data line while the clock is high The CAT5132 responds with an acknowledge after
will be interpreted as a START or STOP condition. receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
The device controlling the transfer is a master, typically a responds with an acknowledge after receiving each 8-bit
processor or controller, and the device being controlled is the byte.
slave. The master will always initiate data transfers and When the CAT5132 is in a READ mode it transmits 8 bits
provide the clock for both transmit and receive operations. of data, releases the SDA line, and monitors the line for an
Therefore, the CAT5132 will be considered a slave device acknowledge. Once it receives this acknowledge, the
in all applications. CAT5132 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
START Condition
The START Condition precedes all commands to the and waits for a STOP condition.
device, and is defined as a HIGH to LOW transition of SDA Acknowledge Polling
when SCL is HIGH. The CAT5132 monitors the SDA and The disabling of the inputs can be used to take advantage
SCL lines and will not respond until this condition is met of the typical write cycle time. Once the STOP condition is
(see Figure 8). issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling can
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH be initiated immediately. This involves issuing the START
determines the STOP condition. All operations must end condition followed by the slave address. If the CAT5132 is
with a STOP condition (see Figure 8). still busy with the write operation, no ACK will be returned.
If the CAT5132 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.

SCL

SDA

START STOP
CONDITION CONDITION
Figure 8. Start/Stop Condition

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

SCL FROM
MASTER 1 8 9

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER
START ACK SETUP ( tSU:DAT)
ACK DELAY ( tAA)

Figure 9. Acknowledge Condition

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 CAT5132

DEVICE DESCRIPTION

Access Control Register The next two bits, A1 and A0, are the internal slave
The volatile register WCR and the non-volatile register address and must match the physical device address which
DR are accessed only by addressing the volatile Access is defined by the state of the A1 and A0 input pins. Only the
Register AR first, using the 3 byte I2C protocol for all read device with slave address matching the input byte will be
and write operations (see Table 12). The first byte is the slave accessed by the master. This allows up to 4 devices to reside
address/instruction byte (see details below). The second on the same bus. The A1 and A0 inputs can be actively
byte contains the address (02h) of the AR register. The data driven by CMOS input signals or tied to VCC or Ground.
in the third byte controls which register WCR (80h) or DR The last bit is the READ/WRITE bit and determines the
(00h) is being addressed (see Figure 10). function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
Slave Address Instruction Byte Description
register only write is allowed.
The first byte sent to the CAT5132 from the master After the Master sends a START condition and the slave
processor is called the Slave Address Byte. The most address byte, the CAT5132 monitors the bus and responds
significant five bits of the slave address are a device type with an acknowledge when its address matches the
identifier. For the CAT5132 these bits are fixed at 01010 transmitted slave address.
(refer to Table 13).

Table 12. ACCESS CONTROL REGISTER

1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb

AR address − 02h WCR(80h) / DR(00h) selection

A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP

Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE

Device Type Identifier Slave Address Read/Write

ID4 ID3 ID2 ID1 ID0 A1 A0 R/W

0 1 0 1 0 X X X

(MSB) (LSB)

SLAVE
S ADDRESS AR REGISTER WCR/DR
T & INSTRUCTION ADDRESS SELECTION S
BUS ACTIVITY: A T
MASTER R FIXED O
T P
SDA LINE S P
A A A
VARIABLE C C C
K K K

Figure 10. Access Register Addressing Using 3 Bytes

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 CAT5132

Wiper Control Register (WCR) Description

The CAT5132 contains a 7-bit Wiper Control Register make use of the 7 LSB bits (The first data bit, or MSB, is
which is decoded to select one of the 128 switches along its ignored) on write instructions and will always come back as
resistor array. The WCR is a volatile register and is written a “0” on read commands.
with the contents of the nonvolatile Data Register (DR) on A write operation (see Table 14) requires a Start condition,
power-up. The Wiper Control Register loses its contents followed by a valid slave address byte, a valid address byte
when the CAT5132 is powered-down. The contents of the 00h, a data byte and a STOP condition. After each of the
WCR may be read or changed directly by the host using a three bytes the CAT5132 responds with an acknowledge. At
READ/WRITE command after addressing the WCR (see this time the data is written only to volatile registers, then the
Table 12 to access WCR). Since the CAT5132 will only device enters its standby state.
Table 14. WCR WRITE OPERATION
1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb
AR address − 02h WCR(80h) selection
A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
START

STOP
slave address byte WCR address − 00h data byte
ACK

ACK

ACK
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A x x x x x x x x A SP

An increment operation (see Table 15) requires a Start data is low the wiper is decremented at each clock. Once the
condition, followed by a valid increment address byte stop is issued then the device enters its standby state with the
(01011), a valid address byte 00h. After each of the two WCR data as being the last inc/dec position. Also, the wiper
bytes, the CAT5132 responds with an acknowledge. At this position does not roll over but is limited to min and max
time if the data is high then the wiper is incremented or if the positions.
Table 15. WCR INCREMENT/DECREMENT OPERATION
1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb

AR address − 02h WCR(80h) selection

A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
START

STOP
slave address byte WCR address − 00h increment (1) / decrement (0) bits
ACK

ACK

ST 0 1 0 1 1 0 0 0 A 0 0 0 0 0 0 0 0 A 1 1 1 1 0 0 0 0 SP

A read operation (see Table 16) requires a Start condition, CAT5132 responds with an acknowledge and then the
followed by a valid slave address byte for write, a valid device transmits the data byte. The master terminates the
address byte 00h, a second START and a second slave read operation by issuing a STOP condition following the
address byte for read. After each of the three bytes, the last bit of Data byte.

Table 16. WCR READ OPERATION

1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb

AR address − 02h WCR(80h) selection

A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
START

slave address byte WCR address − 00h

ACK

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0
START

STOP

slave address byte data byte

ST 0 1 0 1 0 0 0 1 A 0 X X X X X X X SP

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 CAT5132

Data Register (DR)

The Data Register (DR) is a nonvolatile register and its written during a write to DR. After a DR WRITE is complete
contents are automatically written to the Wiper Control the DR and WCR will contain the same wiper position.
Register (WCR) on power-up. It can be read at any time To write or read to the DR, first the access to DR is
without effecting the value of the WCR. The DR, like the selected, see table 1 then the data is written or read using the
WCR, only stores the 7 LSB bits and will report the MSB bit following sequences.
as a “0”. Writing to the DR is performed in the same fashion A write operation (see Table 17) requires a Start condition,
as the WCR except that a time delay of up to 5 ms is followed by a valid slave address byte, a valid address byte
experienced while the nonvolatile store operation is being 00h, a data byte and a STOP condition. After each of the
performed. During the internal non-volatile write cycle, the three bytes the CAT5132 responds with an acknowledge. At
device ignores transitions at the SDA and SCL pins, and the this time the data is written both to volatile and non-volatile
SDA output is at a high impedance state. The WCR is also registers, then the device enters its standby state.
Table 17. DR WRITE OPERATION
1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb

AR address − 02h DR(00h) selection

A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP
START

STOP
slave address byte DR address − 00h data byte
ACK

ACK

ACK
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A X X X X X X X X A SP

A read operation (see Table 18) requires a Start condition, acknowledge and then the device transmits the data byte.
followed by a valid slave address byte, a valid address byte The master terminates the read operation by issuing a STOP
00h, a second Start and a second slave address byte for read. condition following the last bit of Data byte.
After each of the three bytes the CAT5132 responds with an

Table 18. DR READ OPERATION

1st byte 2nd byte 3rd byte
START

STOP
ACK

ACK

ACK
ID4

ID3

ID2

ID1

ID0

Wb

AR address − 02h DR(00h) selection

A1

A0

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP
START

slave address byte DR address − 00h

ACK

ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0
START

STOP

slave address byte data byte

ST 0 1 0 1 0 0 0 1 A 0 X X X X X X X SP

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 CAT5132

POTENTIOMETER OPERATION

Power-On
The CAT5132 is a 128-position, digital controlled ~79 W is the resistance between each wiper position.
potentiometer. When applying power to the CAT5132, VCC However in addition to the ~79 W for each resistive segment
must be supplied prior to or simultaneously with V+. At the of the potentiometer, a wiper resistance offset must be
same time, the signals on RH, RW and RL terminals should considered. Table 19 shows the effect of this value and how
not exceed V+. If V+ is applied before VCC, the electronic it would appear on the wiper terminal.
switches are powered in the absence of the switch control This offset will appear in each of the CAT5132 end-to-end
signals, that could result in multiple switches being turned resistance values in the same way as the 10 kW example.
on. This causes unexpected wiper settings and possible However resistance between each wiper position for the
current overload of the potentiometer. When VCC is applied 50 kW version will be ~395 W and for the 100 kW version
the device turns on at the mid-point wiper location (64) until will be ~790 W.
the wiper register can be loaded with the nonvolatile
memory location previously stored in the device. After the Table 19. POTENTIOMETER RESISTANCE AND
nonvolatile memory data is loaded into the wiper register the WIPER RESISTANCE OFFSET EFFECTS
wiper location will change to the previously stored wiper Position Typical RW to RL Resistance for 10 kW
position. Digital POT
At power-down, it is recommended to turn-off first the 00 70 W or 0 W + 70 W
signals on RH, RW and RL, followed by V+ and, after that,
01 149 W or 79 W + 70 W
VCC, in order to avoid unexpected transmissions of the
wiper and uncontrolled current overload of the 63 5,047 W or 4,977 W + 70 W
potentiometer. 127 10,070 W or 10,000 W + 70 W
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the total
Position Typical RW to RH Resistance for 10 kW
resistor. Each of these contact points is addressed by the 7 bit Digital POT
wiper register which is decoded to select one of these 128
contact points. 00 10,070 W or 10,000 W + 70 W
Each contact point generates a linear resistive value 64 5,047 W or 4,977 W + 70 W
between the 0 position and the 127 position. These values 126 149 W or 79 W + 70 W
can be determined by dividing the end-to-end value of the
127 70 W or 0 W + 70 W
potentiometer by 127. In the case of the 10 kW potentiometer

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 CAT5132

PACKAGE DIMENSIONS

MSOP 10, 3x3

CASE 846AE
ISSUE O

SYMBOL MIN NOM MAX

A 1.10
A1 0.00 0.05 0.15
A2 0.75 0.85 0.95
b 0.17 0.27
c 0.13 0.23

E E1 D 2.90 3.00 3.10

E 4.75 4.90 5.05
E1 2.90 3.00 3.10
e 0.50 BSC
L 0.40 0.60 0.80
L1 0.95 REF
L2 0.25 BSC
θ 0º 8º

DETAIL A
TOP VIEW

A A2

c END VIEW
A1 e b

SIDE VIEW
q

L2

L
Notes:
L1
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187. DETAIL A

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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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