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 www.fairchildsemi.com

AN-5076
Design a High Power Factor Flyback Converter Using
FL7733A for an LED Driver with Ultra-Wide Output Voltage

Introduction
Due to continuous improvement of high-brightness LED’s inside small-form factor retrofit lamps and meet
efficacy, as increasing number of lighting lamps are international regulations without excessive cost increase for
designed using LED as the replacement for incandescent, SSL application. Fairchild Semiconductor’s Pulse Width
fluorescent, plate, down light, etc. LED drivers need highly Modulation (PWM) PSR controller, FL7733A, simplifies
precise output current regulation because LED brightness meeting SSL requirements while eliminating external
and color is dependent on LED current level. At the same components. FL7733A provides highly precise output
time, high Power Factor (PF) and low Total Harmonics current regulation versus change in the transformer’s
Distortion (THD) have become key design requirements for magnetizing inductance, input and output voltage
LED driver. In applications where precise output current information, and powerful protection functions for system
regulation is required, the conventional control method uses reliability.
current sensing in the secondary side, which results in
This application note presents practical design
additional sensing loss.
considerations for a single-stage flyback LED driver with
Primary-Side Regulation (PSR) for LED drivers can be a ultra-wide output voltage ranges using the FL7733A. It
solution for achieving international regulations (such as includes the procedure for designing the transformer and
Energy Star) for Solid-State Lighting (SSL) products. PSR selecting key components. The design procedure is verified
controls the output current precisely with the information in through an experimental prototype converter. Figure 1
the primary side of the power supply only, removing output shows the typical application circuit of primary-side
current sensing loss and eliminating secondary feedback controlled flyback LED driver using the FL7733A.
circuitry. This makes it feasible to fit the driver circuit

DC Output

AC Input

8 HV GATE 1
CS
FL7733A
6 COMI VDD 4

3 GND VS 5
NC
7

Figure 1. Typical Application Circuit

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.2 • 10/23/14
AN-5076 APPLICATION NOTE

Operation Principle of Primary-Side Regulation

Generally, Discontinuous Conduction Mode (DCM) Mode III
operation is preferred for single-stage primary-side flyback
converters because it allows better output regulation, higher When the diode current reaches zero, the transformer
PF, and lower THD. The operation principles of DCM auxiliary winding voltage begins to oscillate by the
flyback converter are as follows: resonance between the primary-side inductance (Lm) and the
effective capacitor loaded across MOSFET (Q).
Mode I
VGate MODE I MODE II MODE III
During the MOSFET turn-on time (tON), input voltage (VIN)
is applied across the transformer’s primary-side inductance
(Lm). Then, drain current (IDS) of the MOSFET increases
linearly from zero to the peak value (IDS.PK), as shown in VDS
NP
(VOUT VF )
Figure 3. During this time, the energy is drawn from the NS

input and stored in the inductor.

VIN
Mode II
When the MOSFET (Q) is turned off, the energy stored in IDS.PK
IDS
the transformer forces the rectifier diode (D) to turn on.
NP : NS ID D
NP
+ + VF
ID  IDS.PK
VIN NS
LM
IO
AC Input
Q IDS

VA NA
 VOUT
Gate NS
RS
PWM VCS
VCS Detector
Control

VDD NA tDIS
VCOMI
TRUECURRENT®
Calculation + tS
VA
Figure 3. Key Waveforms of PSR Flyback Converter
Ref EAI
VS
tDIS Detector
The output current can be estimated using the peak drain
current and inductor current discharge time because output
Primary Side Regulation
Controller current is the same as the average of the diode current in
steady state. The peak value of the drain current is
Figure 2. Primary-Side Regulated Flyback Converter determined by the CS peak voltage detector and the inductor
While the diode is conducting, output voltage (VOUT) and the current discharge time (tDIS) is sensed by the tDIS detector.
diode forward-voltage drop (VF), is applied across the With peak drain current, inductor current discharging time,
transformer’s secondary-side inductance and diode current (ID) and operating switching period information; the innovative
decreases linearly from the peak value (IDS.PK NP/NS) to zero. TRUECURRENT® calculation block estimates output
At the end of inductor current discharge time (tDIS), all energy current as follows:
stored in the transformer has been delivered to the output. 1 t DIS N 1
Io    VCS  P  (1)
2 tS NS RS
t DIS
 VCS  0.25 (2)
tS
NP 1
I o  0.125   (3)
NS RS

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 2
AN-5076 APPLICATION NOTE

Design Procedure
A design procedure for a single-stage flyback LED driver, where the IIN.rms and VIN.rms are rms line input current and
based on FL7733A, is presented in this section using the voltage, respectively.
schematic of Figure 1 as the reference. An offline LED
tON is required to calculate the required Lm value. With
driver with 50 W (50 V / 1 A) output has been selected as a
Equation (5) ~ (7), the turn-on time, tON, is obtained as:
design example. The design specifications are:
2Lm  IIN .rms
 Input voltage range: 90 ~ 264 VAC and 50 ~ 60 Hz tON 
2
(8)
 Nominal output voltage and current: 50 V / 1.0 A VIN .rms  fs
 Operating output voltage: 7 V ~ 55 V The input power is given as:
 Minimum efficiency: 88% PO
PIN  IIN .rms  VIN .rms  (9)
 Operating switching frequency: 65 kHz 
 Maximum duty: 40% With Equation (8)and (9), the Lm value is obtained as:
  (VIN .rms )2  fS  tON
2
Step 1. Transformer Primary-Side Inductance Lm  (10)
Selection (Lm) 2PO

FL7733A operates with constant turn-on and turn-off time, (Design Example) When the minimum input voltage is
as shown Figure 4. When MOSFET turn-on time (tON) and 90 VAC, the maximum tON occurs at full-load condition. The
switching period (tS) are constant, IIN is proportional to VIN maximum tON at 65 kHz of the operating frequency can be
and it can achieve high power factor. decided by maximum duty, then the magnetizing inductance
Max. Peak Drain Current (IDS.PK) Secondary Current Peak Envelop is obtained as:
Peak Input Current (IIN.PK)
0.88  90 2  65  10 3  (6.2  10 6 )2
Average Output Current Lm   175 µH
Primary Current Peak Envelop
2  50
Average Input Current (IIN) The drain peak current of MOSFET at nominal output power
is calculated as:
6.2  10 6  2  90
I DS.PK   4.51 A
175  10 6

Step 2. Sensing Resistor and nPS Selection

Constant On -Time (tON) Constant OFF -Time (tOFF)
tS
FL7733A adopts the TRUECURRENT® calculation method
Figure 4. Theoretical Waveform for constant output current (IO) regulation, as defined in
The single-stage flyback using FL7733A is assumed to Equation (1). The output current is proportional to turn ratio
operate in DCM due to constant tON and tS. Input voltage is nps between the primary and secondary windings of the
applied across the magnetizing inductance (Lm) during tON, transformer and inversely proportional to sensing resistor
charging the magnetic energy in Lm. Therefore, the value (RS). The FL7733A implements cycle-by-cycle current
maximum peak switch current (IDS.PK) of the MOSFET limit by detecting VCS to protect the system from an LED
occurs at peak point of line voltage, as shown Figure 4. The short or overload. Therefore, the VCS level needs to handle
peak input current (IIN.PK) is also shown at the peak input the rated system power without triggering current-limit
voltage of one line cycle. Once the maximum tON is decided, protection. It is typical to set the cycle-by-cycle limit level
IDS.PK of MOSFET is obtained at the minimum line input (typical: 0.85 V) at 15 ~ 20% higher than CS peak voltage
voltage and full-load condition as: (VCS.PK) at full-load condition. MOSFET peak current (ISW.PK)
is converted into VCS,PK as:
tON  VIN .PK
I DS.PK  (4)
Lm VCS.PK  ISW .PK  RS (11)
where VIN.PK and tON are the peak input voltage and the According to Equation (3), the primary-to-secondary turn ratio
maximum turn-on time at the minimum line input is determined by the sensing resistor and output current as:
voltage, respectively.
IO  RS
Using Equation (4), the peak input current is obtained by: nPS  (12)
0.125
1 V
IIN .PK   (tON )( IN .PK  tON )  fS (5)
2 Lm (Design Example) Once VCS,pk is set as 0.85 V, the sensing
resistor value and nPS are obtained as:
then, IIN.PK and VIN.PK can be expressed as:
VCS. pk 0.85
RS    0.188 
IIN .PK  2  IIN .rms (6) ISW .PK 4.51

1 0.19
VIN .PK  2  VIN .rms (7) n ps   1.52
0.125

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 3
AN-5076 APPLICATION NOTE

Step 3. nAS and nAP Selection Because FL7733A’s VDD operation range is 8.75 ~ 23 V,
MOSFET switching will be shut down by triggering UVLO
When VDD voltage is 23 V, the FL7733A stops its switching
if output voltage is lower than VOUT-UVLO (8.75×NS /NA).
operation due to Over-Voltage Protection (OVP). So, nAS
Therefore, VDD should be supplied properly without
and nAP can be determined as follows:
triggering UVLO across the wide output voltage range of 7
VDD.OVP 23 ~ 55 V. VDD can be supplied by adding external winding NE
n AS   (13)
VO.OVP VO.OVP and VDD circuits composed of a voltage regulator, as shown
n AS in Figure 5. The NE should be designed so VDD can be
n AP  (14) supplied without triggering UVLO at minimum output
nPS
voltage (Vmin.OUT). The external winding, NE, can be
where, nAS is the auxiliary-to-secondary turns ratio and
determined as:
nAP is the auxiliary to primary turns ratio of transformer.
(8.75  VCE.Q1  VF.D 3 )
(Design Example) Once output over-voltage level is set as NE   NS  N A (16)
(VF .Do  Vmin .OUT )
56 V, nAS is obtained as:
where VCE.Q1 is Q1’s collector-emitter saturation voltage,
23 and VF.D3 is D3’s forward voltage, and VF.Do is Do’s
n AS   0.41
56 forward voltage at the minimum output voltage.
0.41 (Design Example) An PQ3220 core is selected for the
n AP   0.27
1.52 transformer and the minimum turn number of the
transformer primary winding to avoid core saturation is
given by:
Step 4. Transformer Design
2  90  6.2  10 6
The number of primary turns is determined by Faraday’s law. N p,min   25.3
0.22  141 10 6
Np,min is fixed by the peak value of the minimum line input
voltage across the primary winding and the maximum on Once NP is selected with a margin about 5% ~ 10% to
time. The minimum number of turns for the transformer avoid core saturation:
primary side to avoid core saturation is given by:
N p  25.3  1.1  27.8
VIN .min . pk  tON
N p,min  (15) Once the turn number of the primary side (NP) is
Bsat  Ae
where Ae is the cross-sectional area of the core in mm2 determined as 28, the turn number of the secondary side
and Bsat is the saturation flux density in Tesla. (NS) is obtained by:
Since the saturation flux density decreases as temperature NS  28  1.52  18.4
rises, the high-temperature characteristics must be
considered if the transformer is used inside an enclosed case. Once the turn number of the secondary winding (NS) is
determined as 19, the turn number of the auxiliary winding
Do (NA) is obtained by:
VIN VOUT
N A  19  0.41  7.79
VIN.bnk NP NS Co

Then NA is determined to be 8.
VS Circuit
If VCE.Q1 and VF.D3 are set as 0.5 V and 0.7 V, respectively,
VDD D2 for Wide Output D3
4 Q1 VDD and assuming VF.Do is 1 V at minimum output voltage 7 V;
R1
the external winding NE can be obtained as:
C2 C3 C4 R16
NE
D1 (8.75  0.5  0.7)
NE   19  8  15.6
VAUX ZD2 (1  7)
+
R2 +
VS VS ZD1 Then NE is determined to be 16.
5 + VSC
NA External VDD Circuit
C1 R3

Figure 5. VS Circuit for Wide Output Voltage Range

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 4
AN-5076 APPLICATION NOTE

Step 5. VS Circuits for Wide Output Range

(Design Example) The voltage divider network is
The first consideration for R1, R2, and R3 selection is that determined as:
VS should be 2.45 V at the end of diode current conduction
time to operate at 65 kHz switching frequency at the rated VZD1  (23  0.5)  0.7  10.8
power. The second consideration is VS blanking, as Then VZD1 is determined to be 10 V and, assuming VF.D1 is
explained below. The output voltage is detected by the 0.7 V, R1 can be obtained by:
auxiliary winding and a resistive divider connected to the
23  10  0.7
VS pin, as shown in Figure 5. However, in a single-stage R1   1.23 k
10  10 3
flyback converter without a DC link capacitor, auxiliary
winding voltage cannot be clamped to reflected output R1 can be selected as 1.2 kΩ. Once VIN.bnk and IVS.bnk are
voltage over the whole input line cycle due to the small Lm 50 V and 90 µA, respectively, R2 is obtained by:
current, which induces VS voltage sensing error, as shown in 8  50
R2   1.2 k  157.53 k
Figure 6. Frequency decreases rapidly at the zero-crossing 28  90  10 6
point of line voltage, which can cause LED light flicker. To
maintain constant frequency over the whole sinusoidal line Once R2 is determined to be 160 kΩ, R3 is obtained by:
voltage, VS blanking disables VS sampling when line voltage 160  2.45
R3   47.51 k
10  0.7  2.45
is below a particular level by sensing the auxiliary winding.
VIN Then R3 can be selected as 51 kΩ.

VS.BNK After selecting R3, the VS level should be checked to see if

VIN.BNK
VS voltage across R3 is over 0.6 V at the minimum output
voltage 7 V as given by:
(N A  N E ) R3
VS   (7 V  VF .Do )  ( )  0.6 V
NS R1  R 2  R3

VS
If VS is less than 0.6 V, reduce the Zener diode voltage VZD1
Sensing Error and increase R3 values through Equations (17) to (20).

A bypass capacitor, C1, of 5 ~ 10 pF closely between the VS

VS at VIN > VIN.BNK VS at low VIN and GND pins is recommended to bypass the switching
Figure 6. VS Waveform noise. The value of the capacitor may affect constant-current
regulation. If excessively high VS capacitance is selected,
In wide output application, the VS level in normal condition
discharge time, tDIS, becomes longer and the output current
should be maintained between 0.6 and 3 V to avoid
is lower, compared to a small VS capacitor.
triggering SLP and VS OVP. This is feasible using additional
VS circuits, as shown in Figure 5.
Considering the high switching frequency, up to 50% of
rated output voltage and VS blanking level for VIN.bnk, the
Zener diode voltage (VZD1), R1, R2, and R3 can be obtained
as: IDS IDo
VZD1  (VDD.OVP  0.5)  VF .D1
(17)
tON tDIS
where VF.D1 is forward voltage of D1 connected in series
with Zener diode ZD1. tDIS
VAUX Delay
Considering Zener diode regulation range and its power
rating, R1 can be selected to limit the Zener diode current
IZD1 to 10 mA: VSC
(V  VSC )
R1  DDOVP (18)
10mA VS
where VSC is voltage clamped by D1 and ZD1.
VIN .bnk
R 2  n AP   R1 (19)
IVS .bnk
where VIN.bnk is the line voltage level for VS blanking and
IVS.bnk is the current level for VS blanking. Figure 7. VS Waveform for tDIS Detection
R 2  2.45
R3  (20)
VSC  2.45

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 5
AN-5076 APPLICATION NOTE

An additional consideration in VS circuits for wide output (Design Example) Diode voltage and current are obtained as:
voltage range is tDIS delay caused by the voltage difference
19
between VAUX and VSC when VAUX across auxiliary winding VD  56   265  2  310 V
28
is clamped to VSC as shown in Figure 7. This delay lasts
until VAUX is the same as VSC and may affect constant output 127 60
I D.rms  0.357    0.991 A
current regulation. It can be removed by putting a capacitor, 2  74.1 20
C9, between the auxiliary winding and the cathode of Zener
diode, ZD1. The VAUX is divided with capacitor voltage VC3
and VZD1 when the gate is turned off. Then VC3 is maintained
Step 7. Design RCD Snubber in Primary Side
to its voltage without discharging at the moment, but VZD2 is
decreased to VAUX – VC3 when the diode current ID reaches When the power MOSFET is turned off, there is a high-
zero. Therefore, VS can follow VAUX as the dotted line voltage spike on the drain due to the transformer leakage
shown in Figure 7. C3 should be selected to the proper value inductance. This excessive voltage on the MOSFET may
depending on resonant frequency determined by the lead to an avalanche breakdown and eventually failure of the
resonance between magnetizing inductance Lm and device. Therefore, it is necessary to use an additional
MOSFET COSS. The 330 pF used in this application was network to clamp the voltage. The RCD snubber circuit and
selected by trial and error. Its value can be obtained as: its waveform are shown in Figure 8. The RCD snubber
network absorbs the current in the leakage inductance by
300 kHz
C3   330 pF (21) turning on the snubber diode (DSN) once the MOSFET drain
fr voltage exceeds the cathode voltage of the snubber diode. In
where fr is the resonance frequency determined by the the analysis of snubber network, it is assumed that the
resonance between COSS and Lm. snubber capacitor is large enough that its voltage does not
change significantly during one switching cycle. The
Step 6. Calculate the Voltage and Current of snubber capacitor should be ceramic or a material that offers
the Switching Devices low ESR. Electrolytic or tantalum capacitors are
unacceptable for these reasons.
Primary-Side MOSFET: The voltage stress of the
MOSFET is discussed in determining the transformer turns VIN NP : NS ID
ratio. Assuming the drain voltage overshoot is considered as
certain voltage VOS, the maximum drain voltage is given as: VSN RSN CSN +
Lm
+
NP CO VOUT
VDS(max)  VIN .max . pk  (VO.OVP  VF .Do )  VOS (22)
NS
DSN Llk
where VIN.max.pk is the maximum line peak voltage and VOS
is the drain voltage overshoot. The rms current (ISW.rms)
IDS
though the MOSFET is given as:
+
t f VDS
I DS.rms  I pk  ON S (23)
6

(Design Example) Assuming that drain voltage overshoot is ID

about 100 V, the maximum drain voltage across the MOSFET
is calculated as: IDS.PK
28
VDS(max)  265  2   (56  1)  100  559 V
19
The rms current though the MOSFET is:
6.2  10 6  65  10 3
I DS.rms  4.51  1.17 A
6 VOS

Secondary-Side Diode: The maximum reverse voltage and NP VSN

(VOUT  VF )
rms current of the rectifier diode are obtained as: NS
VDS
NS
VD  VO  Vin. max .pk (24)
NP VIN
Vin.min.pk NP
ID.rms  ISW .rms   (25)
2  VRO NS Figure 8. Snubber Circuit and Waveforms

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 6
AN-5076 APPLICATION NOTE

Snubber capacitor voltage at full-load condition is given as:

VSN  VRO  VOS (26)
(Design Example) Since the voltage overshoot of the drain
voltage has been determined to be the same as the reflected
The power dissipated in the snubber network is obtained as: output voltage, the snubber voltage is:
2 VSN  VRO  VOS  200 V
VSN 1 VSN
PSN   Llk  I DS.. PK   fS
2
(27)
RSN 2 VSN  VRO The leakage inductance is measured as 3 µH. Then the loss
where Llk is leakage inductance, VSN is snubber capacitor in snubber networking is given as:
voltage at full load, and RSN is the snubber resistor.
1 200
PSN   5  10 6  4.56 2   65  10 3
The leakage inductance is measured at the switching 2 200  84
frequency on the primary winding with all other windings  3.48 W
shorted. The snubber resistor with proper rated wattage
should be chosen based on the power loss. The maximum 200 2
RSN   11.45 k
ripple of the snubber capacitor voltage is obtained as: 3.48

VSN
VSN  (28) To allow 15% ripple on the snubber voltage (200 V):
CSN  RSN  fS
In general, 5 ~ 20% ripple of the selected capacitor voltage 200
CSN   8.9 nF
is reasonable. In this snubber design, neither the lossy 0.15  200  12  103  65  103
discharge of the inductor nor stray capacitance is considered.

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 7
AN-5076 APPLICATION NOTE

PCB Layout Guidance

PCB layout for a power converter is as important as circuit 3. Control pin components; such as CCOMI, CVS, and RVS2;
design because PCB layout with high parasitic inductance or should be close to the assigned pin and signal ground.
resistance can lead to severe switching noise and cause
system instability. PCB should be designed to minimize 4. High-voltage traces related to the drain of the MOSFET
coupling of switching noise into control signals. and RCD snubber should be kept far way from control
circuits to avoid unnecessary interference.
1. The signal ground and power ground should be separated
and connected only at one position (GND pin) to avoid 5. If a heat sink is used for the MOSFET, connect this heat
ground loop noise. The power ground path from the bridge sink to the power ground.
diode to the sensing resistors should be short and wide. 6. The auxiliary winding ground should be connected closer
2. Gate-driving current path (GATE – RGATE – MOSFET – to the GND pin than the control pin components’ ground.
RCS – GND) must be as short as possible.

DC Output
Power
AC Input ground 5
RCS 2

FL7733A 4
RGATE

CS HV

GATE NC
CCOMI
1 GND COMI
CVS
VDD VS
3
CVDD RVS2

Signal
6 ground
RVS1

Figure 9. Layout Example

Lab Note
Before modifying or soldering / de-soldering the power device is sensitive to electrostatic discharge (ESD). To
supply, discharge the primary capacitors through the improve yield, the production line should be ESD protected
external bleeding resistor. Otherwise, the PWM IC may be as required by ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD
destroyed by external high voltage during the process. This STM 12.1, and EOS/ESD S6.1 standards.

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 8
AN-5076 APPLICATION NOTE

Schematic of Design example

Figure 10 shows the schematic of the 50 W LED driver design example. A PQ3220 core is used for the transformer. Figure
11 shows the transformer information.

GND
50V

Aux
Ro1

D3
Co3
Co2

C7
R16
C10

Co1

Q103
Do1

C8
R18

R19

ZD1
11
9

PQ3220 12V
T2

VDD
1

5
Aux

ZD2
C9

D5
R17

R8

R9
R6

R10
Q1
D1

C5
C2

R11
D2

R7

R12
C4
R4

R14
R5

C3

R13

C11
R20

VDD

5
GATE

CS

VS
VDD
U1

COMI

GND
NC
HV
8

3
R1

R2

R3

C6
C1

L
LF1
1

CF1

MOV1
CF2
BD1

F1

Figure 10. Schematic of the FL7733A 50 W Design Example

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 9
AN-5076 APPLICATION NOTE

NA(4 à5)

NE(6 à4)

NP2(2 à1)

Start
NS (9 à11)
2mm Barrier

NP1(3 à2)

Figure 11. Transformer Winding Structure

Table 1. Winding Specifications

No Winding Pin(S à F) Wire Turns Winding Method
1 NP1 3à2 0.45 φ 17 Ts Solenoid Winding
2 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
3 NS 9 à 11 0.7φ (TIW) 19 Ts Solenoid Winding
4 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
5 NP2 2à1 0.45 φ 11 Ts Solenoid Winding
6 Insulation : Polyester Tape t = 0.025 mm, 3-Layer
7 NE 6à4 0.25 φ 16 Ts Solenoid Winding
8 Insulation: Polyester Tape t = 0.025 mm, 3-Layer
9 NA 4à5 0.25 φ 8 Ts Solenoid Winding
10 Insulation: Polyester Tape t = 0.025 mm, 3-Layers

Table 2. Electrical Characteristics

Pin Specifications Remark
Inductance 1–3 170 µH ±10% 60 kHz, 1 V
Leakage 1–3 5 µH 60 kHz, 1 V, Short All Output Pins

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 10
AN-5076 APPLICATION NOTE

Bill of Materials
Item Part
Part Number Qty. Description Manufacturer
No. Reference
1 BD1 G3SBA60 1 4 A / 600 V, Bridge Diode Vishay
2 CF1 MPX AC275V 474K 1 470 nF / 275 VAC, X-Capacitor Carli
3 CF2 MPX AC275V 224K 1 220 nF / 275 VAC, X-Capacitor Carli
4 Co1, Co2, Co3 KMG 470 μF / 63 V 3 470 µF / 63 V, Electrolytic Capacitor Samyoung
5 C1 MPE 630 V 334K 1 330 nF / 630 V, MPE Film Capacitor Sungho
6 C2 C1206C103KDRACTU 1 10 nF / 630 V, SMD Capacitor 1206 Kemet
7 C3 KMG 10 μF / 35 V 1 10 µF / 35 V, Electrolytic Capacitor Samyoung
8 C4 C0805C104K5RACTU 1 100 nF / 50 V, SMD Capacitor 2012 Kemet
9 C5 C0805C519C3GACTU 1 5.1 pF / 25 V, SMD Capacitor 2012 Kemet
10 C6 C0805C205J3RACTU 1 2.2 µF / 25 V, SMD Capacitor 2012 Kemet
11 C7 KMG 1 μF / 50 V 1 1 µF / 50 V, Electrolytic Capacitor Samyoung
12 C8 SCFz2E472M10BW 1 4.7 nF / 250 V, Y-Capacitor Samwha
13 C9 C1206C331K5RACTU 1 330 pF / 630 V, SMD Capacitor 1206 Kemet
14 C10 C1206C471KDRACTU 1 470 pF / 630 V, SMD Capacitor 1206 Kemet
15 C11 C0805C101C3GACTU 1 100 pF / 25 V, SMD Capacitor 0805 Kemet
16 Do1 FFPF08H60S 1 600 V / 8 A, Hyper-Fast Rectifier Fairchild Semiconductor
17 D1, D3 RS1M 2 1000 V / 1 A, Ultra-Fast Recovery Diode Fairchild Semiconductor
18 D2 1N4003 1 200 V / 1 A, General-Purpose Rectifier Fairchild Semiconductor
19 D5 LL4148 1 100 V / 0.2 A, Small Signal Diode Fairchild Semiconductor
20 F1 250 V / 2 A 1 250 V / 2 A, Fuse Bussmann
21 LF1 B82733F 1 40 mH Common Inductor EPCOS
22 MOV1 SVC681D-10A 1 Metal Oxide Varistor Samwha
23 Q1 FCPF400N80Z 1 800 V / 400 mΩ, N-Channel MOSFET Fairchild Semiconductor
24 Q103 KSP42 1 High-Voltage NPN Transistor Fairchild Semiconductor
25 Ro1 RC1206JR-0727KL 1 27 kΩ, SMD Resistor 1206 Yageo
26 R1, R7 RC1206JR-0710KL 2 10 kΩ, SMD Resistor 1206 Yageo
27 R2, R3 RC1206JR-0715KL 2 15 kΩ, SMD Resistor 1206 Yageo
28 R4, R5, R20 RC1206JR-07100KL 3 100 kΩ, SMD Resistor 1206 Yageo
29 R6, R15 RC1206JR-0710RL 2 10 Ω, SMD Resistor 1206 Yageo
30 R8 RC0805JR-07160KL 1 160 kΩ, SMD Resistor 0805 Yageo
31 R9 RC0805JR-0727KL 1 56 kΩ, SMD Resistor 0805 Yageo
32 R10 RC1206JR-070R2L 1 0.2 Ω, SMD Resistor 1206 Yageo
33 R11, R12 RC1206JR-073RL 2 3.0 Ω, SMD Resistor 1206 Yageo
34 R13 RC0805JR-0710RL 1 10 Ω, SMD Resistor 0805 Yageo
35 R14 RC0805JR-07510RL 1 510 Ω, SMD Resistor 0805 Yageo
36 R16 RC1206JR-0730kL 1 30 kΩ, SMD Resistor 1206 Yageo
37 R17 RC1206JR-071KL 1 1.0 kΩ, SMD Resistor 1206 Yageo
38 R18, R19 RC1206JR-07300RL 2 300 Ω, SMD Resistor 1206 Yageo
39 T2 PQ3220 1 PQ Core, 12Pin Transformer TDK
40 U1 FL7733A 1 Main PSR Controller Fairchild Semiconductor
41 ZD1 15 V 1 15 V Zener Diode Fairchild Semiconductor
42 ZD2 10 V 1 10 V Zener Diode Fairchild Semiconductor

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 11
AN-5076 APPLICATION NOTE

Experimental Result of Design Example

To show the validity of the design procedure presented in
VDS (200 V / div) IDS (2.0 A / div)
this application note, the converter described by the
4.5 A 6.2 µs
design example was built and tested.
Figure 12 shows the normal operation waveforms at
minimum and maximum line voltage condition. Input
current waveform is sinusoidal and high PF and low THD
performance can be achieved by DCM control.
VAK (200 V / div) ID (5.0 A / div)
Figure 13 shows key waveforms at minimum input
condition. The conduction time and drain peak current for
the transformer inductance designed in STEP-1 are 6.2 s
and 4.5 A, respectively.
Figure 13. Operation Waveforms at Minimum Line
Figure 14 shows the CC tolerance measured over the Voltage Condition
entire line and output voltage ranges. CC over universal
line at rated output voltage is less than ±0.3% and total
CC regulation for whole line and ultra-wide output ±0.26%
voltage range (7 V ~ 55 V) is ±1.76%.

Figure 15 shows the PF and THD measured at rated load

condition. PF can reach beyond 0.9 and THD can achieve
less than 7% for universal line.

±1.76%

Figure 14. CC Tolerance

VIN (100 V / div) IIN (1.0 A / div)

PF
VOUT (20 V / div) IOUT (0.5 A / div)

THD

VIN (100 V / div) IIN (1.0 A / div)

VOUT (20 V / div) IOUT (0.5 A / div) Figure 15. PF and THD

Figure 12. Input and Output Waveforms

© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.2 • 10/23/14 12
AN-5076 APPLICATION NOTE

Related Product Resources

FL7733A — Primary-Side-Regulated LED Driver with Power Factor Correction

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Rev. 1.0.2 • 10/23/14 13
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