Iec Lab - Exp 09 - Fall 23-24

Revised: Fall 2021-22 Experiment 9 Student’s
Manual
American International University- Bangladesh

Department of Electrical and Electronic Engineering
EEE:…: Introduction to Electrical Circuits Laboratory
Experiment#9:
Title: Analysis of RLC parallel circuit and verification of KCL in AC circuits.
Theory and Methodology
In DC circuits, conductance (G) was defined as being equal to 1/ R . The total conductance of a
parallel circuit was then found by adding the conductance of each branch. The total resistance RT
is simply 1/GT . In ac circuits, we define admittance (Y ) as being equal to 1/ Z . The unit of
measure for admittance as defined by the SI system is Siemens, which has the symbol S.
Admittance is a measure of how well an ac circuit will admit, or allow, current to flow in the
circuit. The larger its value, therefore, the heavier the current flow for the same applied potential.
The total admittance of a circuit can also be found by finding the sum of the parallel admittances.
The total impedance ZT of the circuit is then 1/Y T that is, for the network of Fig.1
Y T =Y 1+Y 2 +Y 3+…………+Y N
Fig.1: Parallel Branch Equivalent Admittance.
Or, Since Z=1/Y ,

1 1 1 1 1
= + + +¿… … … … +
Z T Z1 Z 2 Z3 ZN
For two impedances in parallel,
© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

Manual
For three parallel impedances,
As pointed out in the introduction to this section, conductance is the reciprocal of resistance, and
The reciprocal of reactance (1/X) is called susceptance and is a measure of how susceptible an
element is to the passage of current through it. Susceptance is also measured in Siemens and is
represented by the capital letter B.
For the inductor,
Defining
For inductance, an increase in frequency or inductance will result in a decrease in susceptance or,
correspondingly, in admittance.
For the capacitor,

Manual
Defining
For the capacitor, therefore, an increase in frequency or capacitance will result in an increase in
its susceptibility.
For any configuration (series, parallel, series-parallel, etc.), the angle associated with the total
admittance is the angle by which the source current leads the applied voltage. For inductive
networks,θT is negative, whereas for capacitive networks,θT is positive.
Fig. 2: Parallel Circuit KCL verification

The circuit of fig.2 represents a RLC parallel circuit where the Total Current I will divide into I L
and I C in the parallel branches. If we apply KCL, I = I L + I C .
Pre-Lab Homework:
Study the phase relation of the reactive elements and how to solve the complex impedance
equations. Try to write the related equations and practice some mathematical problems to get
clear idea. Observe the graphs related to parallel RLC circuit. Use PSIM to generate the output of
the circuit provided in this lab sheet.
Apparatus:
a) Oscilloscope
b) Function generator

Manual
c) Resistor: 100  (3)

d) Inductor: 6.3 mH
e) Capacitor: 1F
f) Connecting wire.
g) Bread board
Precautions:
1. We have proceeded according to figure understanding the connections and check initially.
2. Operated the signal/function generator smoothly and connected the probes perfectly.
3. Calibrate the oscilloscope before connecting the channels across any components and ensure
that there was no problem in the probes of the oscilloscope.
4. Connected the components to the breadboard smartly to ensure the connections.
Procedure:
1. Constructed the circuit as shown in fig.1. Connected channel 1 of the oscilloscope across
function generator and channel 2 of the oscilloscope across RL
2. we have Set the amplitude of the input signal 5V peak and the frequency at 1 kHz and selected
sinusoidal wave shape.
3. Measured the value of VRL and IL
4. Determined phase relationship between E and VRL (i.e., θL) *
5. Connected channel 2 of oscilloscope across RC.
6. Determined phase relationship between the waves.
7. Measured value of VRC and IC.
8. Determined phase relationship between E and VRC (i.e., θC) *
9. Added IL and IC.
10. Measured VR and I connecting channel 2 across R.
11. Compared IL+IC with the practically obtained value of I.
12. Did the same work for setting input frequency 2 kHz and 4 kHz.
Data Table:

Manual
Freq.(f) I θ IR θR IL θL IC θC
(kHz) (A) (o) (A) (o) (A) (o) (A) (o)
1
2
3
4
5
Discussions:
i. In this experiment, RC, RL, RLC series circuits were constructed.
ii. Input shape, frequency, wave shape was modified as required. I, VR, VL& VC were
measured where necessary.
iii. The frequency input signal’s value was adjusted several times. The obtained data was
inserted into the table.
iv. Relevant calculation was done using the experimental data. The analysis and verification
were completed effectively.
If we apply KCL, I = I + I L C
Reference(s):
1. Robert L. Boylestad,” Introductory Circuit Analysis”, Prentice Hall, 12th Edition, New York,
2010, ISBN 9780137146666.
2. R.M. Kerchner and G.F. Corcoran, “Alternating Current Circuits”, John Wiley &
Sons, Third Ed., New York, 1956.
3. Lamar University website, [Cited: 12.01.2014]
Available: http://ee.lamar.edu/eelabs/elen2107/lab5.pdf
4. Lamar University website, [Cited: 12.01.2014]
Available: http://ee.lamar.edu/eelabs/elen2107/lab6.pdf

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Revised: Fall 2021-22 Experiment 9 Student’s

American International University- Bangladesh

Fig.1: Parallel Branch Equivalent Admittance.

Or, Since Z=1/Y ,

For two impedances in parallel,

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

For three parallel impedances,

For the capacitor,

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

Fig. 2: Parallel Circuit KCL verification

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

c) Resistor: 100  (3)

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)

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