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Co Unit2 Part2

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data. Data-Cache is inserted between these processing-units & main-memory.

The integer and


floating unit gets data from data cache. Instruction-Unit fetches instructions from an
instruction-cache or from main-memory when desired instructions are not already in cache.
Processor is connected to system-bus & hence to the rest of the computer by means of
a Bus Interface. Using separate caches for instructions & data is common practice in many
processors today. A processor may include several units of each type to increase the potential
for concurrent operations. The 80486 processor has 8-kbytes single cache for both instruction
and data. Whereas the Pentium processor has two separate 8 kbytes caches for instruction and
data.
Note: To execute instructions, the processor must have some means of generating the control-
signals. There are two approaches for this purpose:
1) Hardwired control and
2) Microprogrammed control.

HARDWIRED CONTROL
Hardwired control is a method of control unit design (Figure). The control-signals are
generated by using logic circuits such as gates, flip-flops, decoders etc. Decoder / Encoder
Block is a combinational-circuit that generates required control-outputs depending on state of
all its inputs. Instruction decoder decodes the instruction loaded in the IR. If IR is an 8 bit
register, then instruction decoder generates 28(256 lines); one for each instruction. It consists
of a separate output-lines INS1 through INSm for each machine instruction. According to code
in the IR, one of the output-lines INS1 through INSm is set to 1, and all other lines are set to 0.
Step-Decoder provides a separate signal line for each step in the control sequence. Encoder
gets the input from instruction decoder, step decoder, external inputs and condition codes. It
uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so on.
For example (Figure 7.12), Zin=T1+T6.ADD+T4.BR; This signal is asserted during time-slot T1
for all instructions during T6 for an Add instruction. During T4 for unconditional branch
instruction, when RUN=1, counter is incremented by 1 at the end of every clock cycle. When
RUN=0, counter stops counting. After execution of each instruction, end signal is generated.
End signal resets step counter. Sequence of operations carried out by this machine is
determined by wiring of logic circuits, hence
the name “hardwired”.
Advantage: Can operate at high speed.
Disadvantages: 1) Since no. of instructions/control-lines is often in hundreds, the complexity
of control unit is very high.
2) It is costly and difficult to design.
3) The control unit is inflexible because it is difficult to change the design.
HARDWIRED CONTROL VS MICROPROGRAMMED CONTROL
Attribute Hardwired Control Microprogrammed Control
Micro programmed control is a
Hardwired control is a control
control mechanism to generate
mechanism to generate control-
control-signals by using a memory
Definition signals by using gates, flip- flops,
called control store (CS), which
decoders, and other
contains the control-
digital circuits.
signals.
Speed Fast Slow
Control functions Implemented in hardware. Implemented in software.
Not flexible to accommodate new More flexible, to accommodate new
Flexibility system specifications or new system specification or new
instructions. instructions redesign is required.
Ability to handle Easier.
large or complex Difficult.
instruction sets
Ability to support Easy.
Operating systems& Very difficult.
diagnostic features
Design process Complicated. Orderly and systematic.
Applications Mostly RISC microprocessors. Mainframes, some microprocessors.
Instruction set size Usually under 100 instructions. Usually over 100 instructions.
2K to 10K by 20-400
ROM size -
bit microinstructions.
Chip area efficiency Uses least area. Uses more area.
Diagram
MICROPROGRAMMED CONTROL
Microprogramming is a method of control unit design (Figure). Control-signals are
generated by a program similar to machine language programs. Control Word(CW) is a word
whose individual bits represent various control-signals (like Add, PCin). Each of the control-
steps in control sequence of an instruction defines a unique combination of 1s & 0s in CW.
Individual control-words in microroutine are referred to as microinstructions (Figure).
A sequence of CWs corresponding to control-sequence of a machine instruction
constitutes the microroutine. The microroutines for all instructions in the instruction-set of a
computer are stored in a special memory called the Control Store (CS). Control-unit generates
control-signals for any instruction by sequentially reading CWs of corresponding microroutine
from CS. µPC is used to read CWs sequentially from CS. (µPC Microprogram Counter).
Every time new instruction is loaded into IR, o/p of Starting Address Generator is loaded into
µPC. Then, µPC is automatically incremented by clock; causing successive microinstructions
to be read from CS. Hence, control-signals are delivered to various parts of processor in correct
sequence.
Advantages
• It simplifies the design of control unit. Thus it is both, cheaper and less error prone implement.
• Control functions are implemented in software rather than hardware.
• The design process is orderly and systematic.
• More flexible, can be changed to accommodate new system specifications or to correct the
design errors quickly and cheaply.
• Complex function such as floating point arithmetic can be realized efficiently.
Disadvantages
• A microprogrammed control unit is somewhat slower than the hardwired control unit, because
time is required to access the microinstructions from CM.
• The flexibility is achieved at some extra hardware cost due to the control memory and its
access circuitry.

Organization Of Microprogrammed Control Unit To Support Conditional Branching


Drawback of previous Microprogram control
□ It cannot handle the situation when the control unit is required to check the status of the
condition codes or external inputs to choose between alternative courses of action.
Solution:
□ Use conditional branch microinstruction.
In case of conditional branching, microinstructions specify which of the external inputs,
condition- codes should be checked as a condition for branching to take place. Starting and
Branch Address Generator Block loads a new address into µPC when a microinstruction
instructs it to do so (Figure). To allow implementation of a conditional branch, inputs to this
block consist of external inputs and condition-codes & contents of IR.
µPC is incremented every time a new microinstruction is fetched from microprogram
memory except in following situations:
1) When a new instruction is loaded into IR, µPC is loaded with starting-address of
microroutine for that instruction.
2) When a Branch microinstruction is encountered and branch condition is satisfied, µPC is
loaded with branch-address.
3) When an End microinstruction is encountered, µPC is loaded with address of first CW in
microroutine for instruction fetch cycle.

Microinstructions
A simple way to structure microinstructions is to assign one bit position to each
control-signal required in the CPU. There are 42 signals and hence each microinstruction will
have 42 bits.
Drawbacks of microprogrammed control:
1) Assigning individual bits to each control-signal results in long microinstructions because the
number of required signals is usually large.
2) Available bit-space is poorly used because only a few bits are set to 1 in any given
microinstruction.
Solution: Signals can be grouped because
1) Most signals are not needed simultaneously.
2) Many signals are mutually exclusive. E.g. only 1 function of ALU can be activated at a time.
For ex: Gating signals: IN and OUT signals (Figure); Control-signals: Read, Write; ALU
signals: Add, Sub, Mul, Div, Mod.
Grouping control-signals into fields requires a little more hardware because decoding-
circuits must be used to decode bit patterns of each field into individual control-signals.
Advantage: This method results in a smaller control-store (only 20 bits are needed to store the
patterns for the 42 signals)

Techniques of Grouping of Control-Signals


The grouping of control-signal can be done either by using
1) Vertical organization &
2) Horizontal organisation.
Vertical Organization Horizontal Organization
Highly encoded schemes that use compact
The minimally encoded scheme in which
codes to specify only a small number of
many resources can be controlled with a
control functions in each microinstruction are
single microinstuction is called a horizontal
referred
organization.
to as a vertical organization.
Useful when higher operating-speed is
Slower operating-speeds.
desired.
Short formats. Long formats.
Limited ability to Ability to express a high degree of
express parallel
microoperations. parallelism.
Considerable encoding
of the control Little encoding of the control information.
information.

Microprogram Sequencing
The task of microprogram sequencing is done by microprogram sequencer. Two important
factors must be considered while designing the microprogram sequencer,
1) The size of the microinstruction &
2) The address generation time.
The size of the microinstruction should be minimum so that the size of control memory
required to store microinstructions is also less. This reduces the cost of control memory. With
less address generation time, microinstruction can be executed in less time resulting better
throughout. During execution of a microprogram the address of the next microinstruction to be
executed has 3 sources:
1) Determined by instruction register.
2) Next sequential address &
3) Branch.
Microinstructions can be shared using microinstruction branching.
Disadvantage of microprogrammed branching:
1) Having a separate microroutine for each machine instruction results in a large total number
of microinstructions and a large control-store.
2) Execution time is longer because it takes more time to carry out the required branches.
Consider the instruction Add src,Rdst ;which adds the source-operand to the contents
of Rdst and places the sum in Rdst. Let source-operand can be specified in following addressing
modes
a) Indexed b) Autoincrement c) Autodecrement d) Register indirect & e) Register direct
Each box in the chart corresponds to a microinstruction that controls the transfers and
operations indicated within the box. The microinstruction is located at the address indicated by
the octal number (001,002).
Branch Address Modification Using Bit-Oring
The branch address is determined by ORing particular bit or bits with the current
address of microinstruction. Eg: If the current address is 170 and branch address is 171 then
the branch address can be generated by ORing 01(bit 1), with the current address. Consider the
point labelled in the figure. At this point, it is necessary to choose between direct and indirect
addressing modes. If indirect-mode is specified in the instruction, then the microinstruction in
location 170 is performed to fetch the operand from the memory. If direct-mode is specified,
this fetch must be bypassed by branching immediately to location 171. The most efficient way
to bypass microinstruction 170 is to have bit-ORing of current address 170 & branch address
171.

Wide Branch Addressing


The instruction-decoder (InstDec) generates the starting-address of the microroutine
that implements the instruction that has just been loaded into the IR. Here, register IR contains
the Add instruction, for which the instruction decoder generates the microinstruction address
101. (However, this address cannot be loaded as is into the μPC). The source-operand can be
specified in any of several addressing-modes. The bit-ORing technique can be used to modify
the starting-address generated by the instruction-decoder to reach the appropriate path.
Use of WMFC
WMFC signal is issued at location 112 which causes a branch to the microinstruction
in location 171. WMFC signal means that the microinstruction may take several clock cycles
to complete. If the branch is allowed to happen in the first clock cycle, the microinstruction at
location 171 would be fetched and executed prematurely. To avoid this problem, WMFC signal
must inhibit any change in the contents of the μPC during the waiting-period.

Detailed Examination of Add (Rsrc)+,Rdst


Consider Add (Rsrc)+,Rdst; which adds Rsrc content to Rdst content, then stores the
sum in Rdst and finally increments Rsrc by 4 (i.e. auto-increment mode). In bit 10 and 9, bit-
patterns 11, 10, 01 and 00 denote indexed, auto-decrement, auto-increment and register modes
respectively. For each of these modes, bit 8 is used to specify the indirect version. The
processor has 16 registers that can be used for addressing purposes; each specified using a 4-
bit-code (Figure 7.21). There are 2 stages of decoding:
1) The microinstruction field must be decoded to determine that an Rsrc or Rdst register is
involved.

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