Slvubb 4 B

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com Table of Contents
User’s Guide
Power Stage Designer
ABSTRACT
Power Stage Designer™ software tool is a Java® based tool that helps engineers speed up their power supply
designs by calculating voltages and currents for 21 topologies according to the user's inputs. Additionally, Power
Stage Designer contains a Bode plotting tool and a helpful toolbox with various functions for power supply
design. This document describes how the different features of Power Stage Designer can be used and also
explains the calculations behind these functions.
Table of Contents
1 Topologies Window................................................................................................................................................................ 2
2 FET Losses Calculator........................................................................................................................................................... 5
3 Load Step Calculator..............................................................................................................................................................7
4 Capacitor Current Sharing Calculator.................................................................................................................................. 8
5 AC/DC Bulk Capacitor Calculator........................................................................................................................................10
6 RCD-Snubber Calculator for Flyback Converters..............................................................................................................11
7 RC-Snubber Calculator........................................................................................................................................................ 13
8 Output Voltage Resistor Divider..........................................................................................................................................15
9 Dynamic Analog Output Voltage Scaling........................................................................................................................... 17
10 Dynamic Digital Output Voltage Scaling...........................................................................................................................18
11 Unit Converter..................................................................................................................................................................... 19
12 Loop Calculator...................................................................................................................................................................20
12.1 Inputs............................................................................................................................................................................. 21
12.2 Transfer Functions......................................................................................................................................................... 23
13 Filter Designer.....................................................................................................................................................................35
13.1 Impedances....................................................................................................................................................................35
13.2 Transfer Functions......................................................................................................................................................... 35
13.3 Filter Output Impedance.................................................................................................................................................36
13.4 Damping Factor..............................................................................................................................................................36
14 Additional Information........................................................................................................................................................37
15 Revision History................................................................................................................................................................. 37
List of Figures
Figure 1-1. Main Window of Power Stage Designer Displaying Supported Topologies.............................................................. 2
Figure 1-2. Topology Window for SEPIC..................................................................................................................................... 3
Figure 1-3. Graph Window for FET Q1 of a SEPIC Operating in CCM....................................................................................... 4
Figure 2-1. FET Losses Calculator Window................................................................................................................................ 5
Figure 3-1. Load Step Calculator Window................................................................................................................................... 7
Figure 4-1. Capacitor Current Sharing Calculator....................................................................................................................... 8
Figure 5-1. Bulk Capacitor Calculator for AC/DC Power Supplies Window...............................................................................10
Figure 6-1. RCD-Snubber Calculator for Flyback Converters Window......................................................................................12
Figure 7-1. RC-Snubber Calculator Window............................................................................................................................. 13
Figure 8-1. Output Voltage Resistor Divider Calculator Window............................................................................................... 15
Figure 9-1. Dynamic Output Voltage Scaling Calculator Window..............................................................................................17
Figure 10-1. Dynamic Output Voltage Scaling Calculator Window............................................................................................18
Figure 11-1. Unit Converter Window..........................................................................................................................................19
Figure 12-1. Loop Calculator Window....................................................................................................................................... 20
Figure 12-2. Schematic of a Type II Compensation Network.................................................................................................... 28
Figure 12-3. Schematic of a Type II Transconductance Compensation Network...................................................................... 30
Figure 12-4. Schematic of a Type III Compensation Network................................................................................................... 31
Figure 12-5. Schematic of an Isolated Type II Compensation Network With a Zener Clamp....................................................32
SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 1

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Figure 12-6. Schematic of an Isolated Type II Compensation Network Without a Zener Clamp...............................................33
Figure 13-1. Filter Designer Window......................................................................................................................................... 35
Trademarks
Power Stage Designer™ is a trademark of Texas Instruments.
Java® is a registered trademark of Oracle.
All trademarks are the property of their respective owners.
1 Topologies Window
To start a power supply design with Power Stage Designer, first select a topology from the Topology menu. The
window changes and displays the schematic of the selected topology with a set of input fields and various output
values. After entering the parameters of the power supply specification, Power Stage Designer suggests a value
for the output inductance to stay below the entered current ripple requirement. For isolated topologies, the tool
also displays a recommendation for the transformer turns ratio (TTR) based on the selected maximum duty cycle
and suggests a value for the magnetizing inductance. Users can enter values of their choice and evaluate their
impact on voltage and current waveforms and other parameters like on-time, off-time, and duty cycle.
Figure 1-1 shows the main window of Power Stage Designer displaying supported topologies.
Figure 1-1. Main Window of Power Stage Designer Displaying Supported Topologies
2 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

www.ti.com Topologies Window
Figure 1-2. Topology Window for SEPIC
After clicking on one of the yellow highlighted components in the schematic (see Figure 1-2), a new window
displays the voltage and current waveforms for this specific component (see Figure 1-3). Additional information
like the minimum and maximum voltage, minimum and maximum current, as well as root mean square (RMS),
average, and AC values for the current is also provided in this window. The input voltage can be changed across
the entire input voltage range with a slider. For most topologies the load current can be altered in the range
of 1% to 100% of the entered output current with a second slider. Some topology models do not support such
a wide load current range, thus the load current slider can be changed only in the range of 50% and 100%.
The Quasi-resonant Flyback model uses a fixed output power as base for all calculations. That is why the load
current slider is not available for this specific topology.

Topologies Window www.ti.com
Figure 1-3. Graph Window for FET Q1 of a SEPIC Operating in CCM
Note
All equations used for calculations are ideal, with the only exception that the forward voltage of
rectifier and freewheeling diodes is considered. For a collection of the equations behind certain
topologies, see the Power Topologies Handbook.

www.ti.com FET Losses Calculator
2 FET Losses Calculator

The FET Losses Calculator lets the user either compare two different FETs or calculate losses for the main
FET and a synchronous rectifier in a hard-switching power stage. Figure 2-1 shows the FET Losses Calculator
window.
Note
The Quasi-resonant Flyback, LLC-Half-Bridge, LLC-Full-Bridge, and Phase-Shifted Full-Bridge are
resonant topologies. Manual inputs can provide more accurate results.
Figure 2-1. FET Losses Calculator Window
To attain the most accurate results, it is important to determine the gate drive voltage (VGS) of the power
management controller since the values for Qg (which is relevant for driver losses) and RDS(on) are dependent on
this voltage and must be obtained from graphs in the data sheet of the FET.
The different losses which can be seen in the FET of a power supply are conducted losses, switching losses,
Coss losses, and body diode losses. Reverse recovery losses are neglected, but can become significant at high
switching frequencies.
Conductive losses:
Pcond = IFET, rms2 × RDS on (1)

FET Losses Calculator www.ti.com
Switching losses:
Qgs − Qg th × Rg, total Qgd × Rg, total

trise = + V −V
Vmiller VGS th GS miller
VGS − −
2 2
Qgd × Rg, total Qgs − Qg th × Rg, total

tfall = Vmiller +
Vmiller VGS th
+
2 2
f
Pswitching = VDS × switch
2 × trise × IFET, min + tfall × IFET, max (2)
Coss losses:
f
PCoss = Coss × VDS2 × switch
2 (3)
Body Diode losses:
Pbody = VSD × f switch × tdead, on × IFET, min + tdead, off × IFET, max (4)
The total losses for the main FET can be calculated as indicated in Equation 5
Ptotal = Pcond + Pswitching + PCoss (5)
For synchronous rectifiers, the switching losses equal zero due to soft switching, but during the dead time the
body diode is conducting. So the total losses result as indicated in Equation 6:
Ptotal = Pcond + Pbody + PCoss (6)
Additionally, driver losses occur in the power management controller, which can be calculated as shown in
Equation 7:
Pdriver = Qg × VGS × f switch (7)
Power management controllers typically have a limited amount of gate drive current they can source and sink.
Therefore, it is important to adjust the total resistance in the gate drive path so the resulting gate drive current is
equal to or smaller than the limit in the data sheet.

www.ti.com Load Step Calculator
3 Load Step Calculator

The Load Step Calculator enables the user to estimate the minimum required output capacitance to meet certain
load transient requirement for power supplies that use current mode control or voltage mode control schemes.
Figure 3-1. Load Step Calculator Window
Current Mode Control (CMC):
1
Cout = ∆ Vout (8)
PM × π
2 × π × f co × − ESR × 2 − 2 × cos 180°
∆ Itran
Voltage Mode Control (VMC):
1
Cout = (9)
1 − ESR × 2 − 2 × cos PM × π
2 × π × f co × ∆ Itran 1 180°
∆ Vout − 2 × π × f co × L

Capacitor Current Sharing Calculator www.ti.com
4 Capacitor Current Sharing Calculator

When connecting different kinds of capacitors in parallel at the input or output of a power supply, the RMS
current going through each capacitor is different as it depends on the impedance of the capacitors across the
entire frequency range. For exact results for the RMS current per capacitor, impedances and currents must be
calculated for all harmonics of the switching frequency. The RMS current for each harmonic must be derived with
a Fast Fourier Transformation (FFT) of the total current signal based on the ratio between total impedance and
single-capacitor impedance at that harmonic frequency.
Figure 4-1 shows the Capacitor Current Sharing Calculator.
Note
In Power Stage Designer, the impedances and the RMS currents are only calculated at the switching
frequency. Thus, the resulting RMS currents are rough estimations.
Figure 4-1. Capacitor Current Sharing Calculator
The impedance for one capacitor at the switching frequency (n can be 1, 2, or 3 and refers to the capacitor
index) can be calculated as indicated in Equation 10:
Zcap, n = ESRCn + i × 2 × π × f switch × ESLCn − 2 × π × f 1 (10)

switch × Cn
Typical ESL values for capacitors are from 1 nH to 7 nH. By assuming 6 nH/cm as parasitic inductance for a
conductor, the inductance for a ceramic capacitor can be estimated by multiplying this value with the capacitor
length. PCB traces and vias can increase this value slightly (see [1]).

www.ti.com Capacitor Current Sharing Calculator
The total impedance of three parallel capacitors at the switching frequency results as seen in Equation 11:
1
Ztotal = 1 1 1 (11)
Zcap, 1 Zcap, 2 + Zcap, 3
+
The RMS current of one capacitor, while neglecting all other harmonics besides the switching frequency, can be
calculated as seen in Equation 12:
Ztotal
Irms, cap, n = Irms, total × (12)
Zcap, n

AC/DC Bulk Capacitor Calculator www.ti.com
5 AC/DC Bulk Capacitor Calculator

AC/DC power supplies typically require a bulk capacitor behind the input rectifier that provides a quasi-constant
input voltage for the converter stage (see Figure 5-1). Power Stage Designer can calculate the minimum
capacitance based on the desired minimum bulk voltage Vbulk,min, the maximum acceptable voltage ripple ∆V in
percent, the input power Pin and the minimum line frequency fline,min (see Equation 13).
Figure 5-1. Bulk Capacitor Calculator for AC/DC Power Supplies Window
Vbulk, min
VAC, min =
1 − ∆V × 2
tdischarge = 4 × f 1 + 2 × π × 1f × sin−1 1 − ∆ V
line, min line, min
tcharge = 4 × f 1 − 2 × π × 1f × sin−1 1 − ∆ V
line, min line, min
2 × Pin × tdischarge
Cbulk = 2
Vbulk, min2 × 1 −1∆ V − 1
2
Cbulk × Vbulk, min × 1 −1∆ V − 1 P 2
Ibulk, rms = + V in (13)
tcharge × 3 bulk, min

www.ti.com RCD-Snubber Calculator for Flyback Converters
6 RCD-Snubber Calculator for Flyback Converters

In Flyback converters the output voltage is reflected from the secondary to the primary side. Additionally,
parasitics caused by the layout and the Flyback transformer leakage inductance can cause a voltage spike
followed by ringing when the MOSFET is turning off. The voltage spike and the ringing can be limited by
implementing an RCD-snubber circuit in parallel to the primary winding. The energy of the high-frequency ringing
is dissipated in the RCD-network. The RCD-Snubber Calculator for Flyback converters in Power Stage Designer
helps the designer choose the starting values for snubber resistor and capacitor based on the user’s inputs,
which follow:
• Sum of output voltage and rectifier voltage
• Flyback transformer turns ratio
• Leakage inductance
• Maximum primary current
• Switching frequency
• Permitted voltage overshoot as a factor
• Snubber capacitor voltage ripple in percent

RCD-Snubber Calculator for Flyback Converters www.ti.com
Figure 6-1 shows the RCD-Snubber Calculator for Flyback Converters window.
Figure 6-1. RCD-Snubber Calculator for Flyback Converters Window
Vsnub is the reflected output voltage plus the permitted overshoot caused by transformer leakage inductance
and switching node parasitics. Thus Ksnub has a value greater than 1. TI recommends a value of 1.5 for most
applications, permitting 50% overshoot (see [1]). See Equation 14.
Np
Vsnub = Ksnub × N × Vout + Vf (14)
s

www.ti.com RC-Snubber Calculator
Starting Snubber resistance:
Vsnub2
Rsnub = Vsnub (15)
1 ×L 2
2 leak × Imax, pri × Np × f switch
Vsnub − N × Vout + Vf
s
Starting Snubber capacitance:
V
snub
Csnub = ∆ V (16)
snub × Vsnub × Rsnub × f switch
7 RC-Snubber Calculator
An RC-Snubber circuit is one option to reduce ringing in a switch mode power supply. Alternatives are the use
of MOSFET gate resistors or a resistor in series with the bootstrap capacitor to slow down rise and/or fall times.
With the RC-Snubber Calculator, Power Stage Designer helps the designer determine starting values for the
snubber resistor and capacitor.
Figure 7-1 shows the RC-Snubber Calculator window.
Figure 7-1. RC-Snubber Calculator Window
• Measure the oscillation frequency f0 of the circuit without a snubber network.

• Add a capacitor C1 in parallel with the rectifier or FET and measure the shifted oscillation frequency f1. Select
a C1 value that is several times larger than the stated typical capacitance of the rectifier at full reverse voltage
or the output capacitance of the FET.
• After entering these three values, the tool will propose starting values for the R-C Snubber network.

RC-Snubber Calculator www.ti.com
Frequency shift ratio:
f
m = f0 (17)
1
Parasitic capacitance:
C1
C0 = 2 (18)
m −1
Parasitic inductance:
m2 − 1
L= 2 (19)
2 × π × f 0 × C1
Initial Snubber capacitance:
Csnub = 3 × C0 (20)
Initial Snubber resistance:
L
Rsnub = C0 (21)

www.ti.com Output Voltage Resistor Divider
8 Output Voltage Resistor Divider

The Output Voltage Resistor Divider Tool calculates the closest resistor values of the chosen E-Series to match
the specified output voltage based on the entered reference voltage, reference voltage tolerance, and desired
resistance value. The resistance value can be entered for the high-side (HS) or the low-side (LS) resistor. It is
also possible to parallel two resistors to get more precise results. The following equations calculate the resulting
output voltage while respecting resistor tolerances and reference voltage tolerances. However, because effects
caused by the bias current are not considered for the calculations, these values are estimates.
Figure 8-1 shows the Output Voltage Resistor Divider Calculator window.
Figure 8-1. Output Voltage Resistor Divider Calculator Window
Effective output voltage with chosen resistance values (see Equation 22):
R +R
Vout, real = Vref × HSR LS
LS
V − Vout
∆ Vout = out, real
Vout (22)
Bias current:
V
Ibias = R out,+real (23)
HS RLS

Output Voltage Resistor Divider www.ti.com
Worst-case minimum output voltage:
R + RLS, max
Vout, min = Vref, min × HS, min
RLS, max
V − Vout
∆ Vout, min = out, min
Vout (24)
Worst-case maximum output voltage:
R + RLS, min
Vout, max = Vref, max × HS, max
RLS, min
V − Vout
∆ Vout, max = out, max
Vout (25)

www.ti.com Dynamic Analog Output Voltage Scaling
9 Dynamic Analog Output Voltage Scaling

If the output voltage of a power supply must be adjustable, add a third resistor to the feedback resistor divider
and apply an analog voltage to this resistor (for example, with the DAC of a microcontroller). The analog signal
can also be provided by smoothing a PWM signal with a low-pass filter. After entering the minimum output
voltage, maximum output voltage, reference voltage, maximum adjusting voltage signal, and the desired value
for the top feedback resistor, Power Stage Designer calculates the required bottom feedback resistance and the
adjusting voltage signal series resistance, as well as the minimum bias current going through the top feedback
resistor.
Figure 9-1 shows the Dynamic Output Voltage Scaling Calculator window.
Figure 9-1. Dynamic Output Voltage Scaling Calculator Window
V − Vref
IR1, min = out, min
R1
R1 × Vadj, max
R3 = V
out, max − Vref − R1 × IR1, min
R ×R ×V
1 3 ref
R2 = R × V (26)
3 out, max − R3 × Vref − R1 × Vref

Dynamic Digital Output Voltage Scaling www.ti.com
10 Dynamic Digital Output Voltage Scaling

Dynamic output voltage adjustment can also be achieved by applying GPIO signals to an array of resistors
and signal FET combinations in parallel with the low-side resistor of the feedback divider. For most cases, a
microcontroller output in open-drain configuration can be used instead of an external signal FET because it is
already part of the system. Power Stage Designer calculates the low-side feedback resistor, the voltage per step,
the bias current, and the series resistance for each bit based on the output voltage range, the reference voltage,
the number of bits, and the value of the high-side feedback resistor.
Figure 10-1 shows the Dynamic Output Voltage Scaling Calculator window.
Figure 10-1. Dynamic Output Voltage Scaling Calculator Window
V − Vref
IR1, min = out, min
R1
R ×V
R2 = V 1 − ref
out, min Vref
V − Vout, min
Vstep = out, max
Bits
2 −1
1
RBit n = (27)
Vout, min + 2Bit × Vstep − Vref 1
−R
R1 × Vref 2
The LM10011 is a device that has this feature integrated for 4/6-Bit VID.

www.ti.com Unit Converter
11 Unit Converter
The Unit Converter can help power supply designers convert typical parameters related to power supplies.
These parameters are magnetic flux, gain, length, weight, airstream, PCB copper thickness, and temperature.
Figure 11-1 shows the Unit Converter window.
Figure 11-1. Unit Converter Window

Loop Calculator www.ti.com
12 Loop Calculator
The Loop Calculator can help power supply designers with the compensation network for voltage mode
controlled (VMC) buck converters or current mode controlled (CMC) buck, boost, inverting buck-boost, forward,
and flyback converters operating in continuous conduction mode (CCM). The transfer functions have been
simplified, thus the results give a first-order approximation of how the Bode plot of the power supply will appear.
Figure 12-1 shows the Loop Calculator window.
Figure 12-1. Loop Calculator Window
The following steps apply when using the Loop Calculator.

1. Select the topology/control scheme and the type of compensation for the design with the radio buttons in the
bottom-left corner. Typically, only the VMC buck needs a Type III Compensation. For all CMC topologies, a
Type II Compensation is usually sufficient.
2. Fill in all input fields with white background. If the Loop Calculator is started from one of the supported
topologies, applicable values from the topologies window will directly transfer to the Loop Calculator window.
3. Under General Information (from the schematic) sum the capacitance of the same output capacitor types
and calculate their effective ESR. The DC-biasing effect for ceramic capacitors must be considered because
it can have a major impact on the accuracy of the gain and phase plot of the power stage.
4. Enter the Gain Information (from the schematic and the data sheet for the controller).
5. Fill in the values for RFBT and RFBB. With this information the Loop Calculator can suggest values for the
compensation network of the entered power supply design.

www.ti.com Loop Calculator
The compensation network suggestions are calculated as follows:
CAUTION
If unusual input conditions are applied, the suggestions of the tool do not necessarily lead to a stable
system.
• Compensation zeroes are placed on the pole of the transfer function of the power stage (L and Cout double
pole for VMC, Rout and Cout single pole for CMC).
• Compensation poles are placed on the lower of either half of the switching frequency or the ESR zero for
Buck derived topologies.
• Compensation poles are placed on the lower of either the right half plane zero (RHPZ) frequency or the ESR
zero frequency for Boost/Buck-Boost derived topologies.
• The maximum achievable crossover frequency is approximately two decades below the GBWP (gain
bandwidth product) of the error amplifier. The gain of the compensation network should never go above
the open loop gain of the error amplifier. Otherwise, the error amplifier will be clipping.
• For Boost/Buck-Boost derived topologies the desired crossover frequency is automatically set to 1/5 of the
RHPZ frequency.
12.1 Inputs
Table 12-1 lists general information.
Table 12-1. General Information
Vin Input voltage
Vout Output voltage
Iout Load current
L Inductance / Flyback primary inductance
DCRL Inductor DC resistance
Capacitance output capacitor 1
Cout,1 For ceramic capacitors use the capacitance at the DC bias
voltage.
ESRout,1 Equivalent series resistance output capacitor 1
Capacitance output capacitor 2
Cout,2 For ceramic capacitors use the capacitance at the DC bias
voltage.
ESRout,2 Equivalent series resistance output capacitor 2
fswitch Switching frequency
Np ⁄ Ns Transformer turns ratio
Opto BW Optocoupler bandwidth
Table 12-2 lists gain information.

Table 12-2. Gain Information
Vramp PWM ramp voltage
Gm Error amplifier transconductance
As Current-sense amplifier gain
Rs Current-sense resistance
AOL Error amplifier open-loop gain
GBWP Error amplifier gain bandwidth product
Rp ⁄ RD Optocoupler transfer ratio
CTR Current Transfer Ratio
Vslope Slope compensation voltage
SLM Slope compensation multiplier

Current-sense gain As and current-sense resistance Rs:

For converters with integrated current-sensing circuits, sometimes there are no specific values for As and Rs in
the data sheet. Instead, a value for Gm,ps (can also appear as “COMP to switch current transconductance”) is
typically displayed. Equation 28 shows the relationship between these values.
1
Gm, ps = A × (28)
s Rs
In this case, values for As and Rs must be chosen to have the stated Gm,ps as a result. (For example, use the
RDS(on) of the internal FET for Rs and calculate As from Equation 28.)
The input field for Vslope offers the user the option to use either Vslope or a slope compensation multiplier
(SLM), in case the value for Vslope cannot be calculated by the designer (for example, because of internal slope
compensation). Switching between these two variables can be done by right-clicking on the Vslope/SLM input
field.
Vslope:
• Calculate the value for Vslope with the equations from the data sheet. If the device has internal slope
compensation, a value for Vslope is typically given in the Electrical Characteristics section.
SLM:
• SLM is a variable to simulate the slope compensation under certain circumstances. How it affects calculations
can be found in the subsections for each topology.
• Ideal slope compensation will be calculated with a value of 1.
• Values greater than 1 show how the converter will drift to VMC with increasing values of SLM, as the
information of the original current signal will be lost at a certain point. A Type III compensation network would
then be necessary to compensate the converter.
• Values in the range from 0 to 1 simulate conditions when not enough slope compensation is present, and a
resonance will become visible at half the switching frequency caused by the quality factor of the double pole
of the inductance.
Table 12-3 lists component values.
Table 12-3. Component Values
RFBT Top feedback resistance
RFBB Bottom feedback resistance
RFF Compensation feed-forward resistance
RCOMP Compensation resistance
CFF Compensation feed-forward capacitance
CCOMP Compensation capacitance
CHF Compensation high-frequency capacitance
For Type II and Type II transconductance compensation networks, the Loop Calculator offers an option to use an
additional Feed-Forward Capacitor in parallel with RFBT. This option can be enabled by right-clicking on the CFF
input field and choosing Use.
At start-up the Loop Calculator displays only the resulting Bode plot for the Total Gain and Total Phase. The
graphs for the Gain of the Power Stage, Phase of the Power Stage, Gain of the Error Amplifier, Phase of
the Error Amplifier and the Error Amplifier Open Loop Gain can be switched on by selecting the respective
checkbox.

12.2 Transfer Functions

12.2.1 Output Impedance Transfer Function
For two parallel capacitors the transfer function can be written as shown in Equation 29:
Rout × s × C1 × ESR1 + 1 × s × C2 × ESR2 + 1

Zout = (29)
s × C1 × ESR1 + 1 × s × C2 × ESR2 + 1 + Rout × s × C2 × s × C1 × ESR1 + 1 + s × C1 × s × C2 × ESR2 + 1
12.2.2 Transfer Function VMC Buck Power Stage
vout K ×Z
= Zm+ Z out (30)
vc L out
DC-Gain:
V
Km = V in (31)
ramp
Filter-Inductor Impedance:
ZL = s × L + DCRL (32)
12.2.3 Transfer Function CMC Buck Power Stage
Vout Km × Zout

= (33)
Vc ZL + Zout + Km × Ri × H s
Duty cycle:
V
D = Vout (34)
in
DC-Gain:
1
Km = Vslope (35)
1
0.5 − D × Rs × As × +
fswitcℎ × L Vin
Sampling Gain Pole:
ωL = π × fswitcℎ (36)
Ri = As × Rs (37)
2
H s = 1 + Q ×s ω + s 2 (38)
L L ωL
With Vslope:
se = Vslope × f switch (39)

With SLM:
SLM × Vout × As × Rs
se = L
Vin − Vout × As × Rs
sn = L
1
QL = se (40)
π× 1+ × 1 − D − 0.5
sn
12.2.4 Transfer Function CMC Boost Power Stage
ZL
Km × 1 − D × 1 − 2
vout 1 − D × Rout
= (41)
vc Z ZL
2
1−D + Z L + Km × Ri × H s × R 1 + Z 1 + K × Km × 1 − D × 1 −
out out out 2
1 − D × Rout
Duty cycle:
V − Vin
D = out
V (42)
out
DC-Gain:
1
Km = Vslope (43)
1
0.5 − D × Rs × As × +
fswitcℎ × L Vin
1
K = 0.5 × Rs × As × f ×D× 1−D (44)
switcℎ × L
Sampling Gain Pole:
Ri = As × Rs (46)
2
H s = 1 + Q ×s ω + s 2 (47)
L L ωL
With Vslope:

With SLM:
SLM × Vout × As × Rs
se = L
V × A × Rs
sn = in Ls
1
QL = se (49)
π× 1+ × 1 − D − 0.5
sn
12.2.5 Transfer Function CMC Inverting Buck-Boost Power Stage
D × ZL
Km × 1 − D × 1 − 2
vout 1 − D × Rout
= (50)
vc Z D × ZL
2
1−D + Z L + Km × Ri × H s × R D + Z 1 + K × Km × 1 − D × 1 −
out out out 2
1 − D × Rout
Duty cycle:
−V
D = −V out (51)
out + Vin
Sampling Gain Pole:
ωL = π × f switch (52)
Ri = As × Rs (53)
2
H s = 1 + Q ×s ω + s 2 (54)
L L ωL
1
Km = Vslope (55)
1
0.5 − D × Rs × As × +
fswitcℎ × L Vin − Vout
1
K = 0.5 × Rs × As × f ×D× 1−D (56)
switcℎ × L
With Vslope:

With SLM:
SLM × −Vout × As × Rs
se = L
V × A × Rs
sn = in Ls
1
QL = se (58)
π× 1+ × 1 − D − 0.5
sn
12.2.6 Transfer Function CMC Forward Power Stage

For interleaved topologies like Push-Pull, Half-Bridge, or Full-Bridge, twice as much FET switching frequency
must be used for calculations because the output inductor "sees" twice the FET switching frequency.
N
Km × Zout × s
vout Np
= Ns (59)
vc
ZL + Zout + Km × Ri × N
p
Duty cycle:
Np
Vout × N
s
D= Vin (60)
DC-Gain:
1
Km = Vslope (61)
1
0.5 − D × Rs × As × +
fsw × L Vin
Sampling Gain Pole:
Ri = As × Rs (63)
As = 1 (64)
N′
N' is the turns ratio between auxiliary and primary winding.
2
H s = 1 + Q ×s ω + s 2 (65)
L L ωL
With Vslope:

With SLM:
Np
SLM × Vout × N × As × Rs
s
se =
Np 2
L× N
s
N
Vin × N s − Vout × As × Rs
p
sn = L
1
QL = s (67)
π× 1 + e × 1 − D − 0.5
sn
12.2.7 Transfer Function CMC Flyback Power Stage
vout
vc
(68)
D × ZL
Km × 1 − D × 1 −
2 Np 2
1−D × Rout ×
Ns
=
2 ZL D 1 D × ZL
1−D + + Km × Ri × H s × Rout × + + K × Km × 1 − D × 1 −
Np 2 Np 2 2 Np 2
Zout × N Zout × 1−D × Rout ×
s Ns Ns
Duty cycle:
Np
Vout ×
Ns
D= Np (69)
Vin + Vout × N
s
DC-Gain:
1
Km = Vslope (70)
1
0.5 − D × Rs × As × +
fsw × L Np
Vin + N × Vout
s
1
K = 0.5 × Rs × As × f ×D× 1−D (71)
switcℎ × L
Sampling Gain Pole:
Ri = As × Rs (73)
2
H s = 1 + Q ×s ω + s 2 (74)
L L ωL
With Vslope:

With SLM:
Np
SLM × Vout ×
Ns × As × Rs
se = L
V × A × Rs
sn = in Ls
1
QL = se (76)
π× 1+ × 1 − D − 0.5
sn
12.2.8 Transfer Function Closed Loop

Closed-loop error amplifier transfer function for non-isolated feedback:
vc 1
= − GEA s × (77)
vout 1 + s
1+ A + 1 + GFB s
OL ωBW
12.2.8.1 Transfer Function Type II Compensation Network

Figure 12-2 is a schematic of a Type II compensation network.
CHF
VOUT
CCOMP
RCOMP
VFB RFBT
-
VC
+ VREF
RFBB
Figure 12-2. Schematic of a Type II Compensation Network
Type II with feed forward:
ωZEA s s
AVM × s × 1 + ωZEA × 1 + ωZFF
GEA s = C (78)
1 + C HF × 1 + ωs
COMP HF
ωZEA s s
AVM ×
s × 1 + ωZEA × 1 + ωZFF
GFB s = RFBB CHF (79)
s
RFBB + RFBT × 1 + CCOMP × 1 + ωHF
Type II:
ωZEA s
AVM × s × 1 + ωZEA
GEA s = C (80)
1 + C HF × 1 + ωs
COMP HF
ωZEA s
AVM ×
s × 1 + ωZEA
s

Compensation zero:
1
ωZEA = R (82)
COMP × CCOMP
Compensation pole:
1
ωHF = R (83)
COMP × CHF
With additional feed-forward capacitor in parallel with RFBT:
ωZFF = R 1× C
FBT FF
1
ωPFF = 1 (84)
× CFF
1 1
RRFBB + RRFBT

12.2.8.2 Transfer Function Type II Transconductance Compensation Network

Figure 12-3 is a schematic of a Type II transconductance compensation network.
VOUT
RFBT
VFB
-
VC
+ VREF
RFBB
RCOMP
gm
CHF
CCOMP
Figure 12-3. Schematic of a Type II Transconductance Compensation Network
Type II Transconductance with feed-forward:
ωZEA s s
GEA s = C (85)
1 + C HF × 1+ ω s × 1 + ωs
COMP PFF HF
ωZEA s s
AVM ×
s × 1 + ωZEA × 1 + ωZFF
s s
RFBB + RFBT × 1 + CCOMP × 1 + ωPFF × 1 + ωHF
Type II Transconductance:
ωZEA s
GEA s = C (87)
1 + C HF × 1 + ωs
COMP HF
ωZEA s
AVM ×
s × 1 + ωZEA
s
DC-Gain:
R
FBB
AVM = R × Gm × RCOMP (89)
FBB + RFBT
Compensation zero:
1
ωZEA = R (90)
COMP × CCOMP
Compensation Pole:
1
ωHF = R (91)
COMP × CHF

With additional feed-forward capacitor in parallel with RFBT:
1
ωZFF = R
FBT × CCFF
1
ωPFF = 1 (92)
× CFF
1 1
RRFBB + RRFBT
12.2.8.3 Transfer Function Type III Compensation Network

Figure 12-4 is a schematic of a Type III compensation network.
CHF
VOUT
CCOMP
RCOMP
CFF
VFB RFBT
RFF
-
VC
+ VREF
RFBB
Figure 12-4. Schematic of a Type III Compensation Network
Type III:
ωZEA s s
GEA s = C (93)
1 + C HF × 1+ ω s × 1 + ωs
COMP PFF HF
ωZEA s s
AVM ×
s × 1 + ωZEA × 1 + ωZFF
s s
RFBB + RFBT × 1 + CCOMP × 1 + ωPFF × 1 + ωHF
DC-Gain:
R
AVM = RCOMP (95)
FBT
Compensation zero 1:
1
ωZEA = R (96)
COMP × CCOMP
Compensation zero 2:
ωZFF = R 1× C (97)
FBT FF

Compensation pole 1:
1
ωFP = R × (98)
FF CFF
Compensation pole 2:
1
ωHF = R (99)
COMP × CHF
12.2.9 Transfer Function Isolated Type II Compensation Network With a Zener Clamp
Figure 12-5 is a schematic of an isolated Type II compensation network with a Zener clamp.
VCC VOUT
RBIAS
RP
RD RFBT
CHF
VC
CCOMP
RCOMP
VFB
RFBB
Figure 12-5. Schematic of an Isolated Type II Compensation Network With a Zener Clamp
Closed loop error amplifier transfer function for isolated feedback.

Type II Isolated with Zener Clamp:
vc R
= − CTR s × RP × GEA s × 1
(100)
vout D 1 + s
1+
AOL ωBW + 1 + GFB s
ωZEA s
GEA s = C (101)
1 + C HF × 1 + ωs
COMP HF
ωZEA s
AVM ×
s × 1 + ωZEA
s
CTR
CTR s = (103)
1+ ω s
OPTO

DC-Gain:
R
AVM = CTR × R P (104)
D
Power Stage Designer uses a constant value of 1 for CTR.

Compensation zero:
1
ωZEA = R (105)
COMP × CCOMP
Compensation pole:
1
ωHF = R (106)
COMP × CHF
12.2.10 Transfer Function Isolated Type II Compensation Network Without a Zener Clamp
Figure 12-6 is a schematic of an isolated Type II compensation network without a Zener clamp.
VCC VOUT
RBIAS
RP
RD RFBT
CHF
VC
CCOMP
RCOMP
VFB
RFBB
Figure 12-6. Schematic of an Isolated Type II Compensation Network Without a Zener Clamp
vc R
= − CTR s × R P × 1 + GEA s × 1
(107)
vout D 1 + A1 + ω s + 1 + GFB s
OL BW
ωZEA s
GEA s = C (108)
1 + C HF × 1 + ωs
COMP HF
ωZEA s
AVM ×
s × 1 + ωZEA
s
CTR
CTR s = (110)
1+ ω s
OPTO

DC-Gain:
R
AVM = CTR × R P (111)
D
Compensation Zero:
1
ωZEA = R (112)
COMP × CCOMP
Compensation pole:
1
ωHF = R (113)
COMP × CHF
Note
Loop Calculator Tips
A Type I compensation network can be simulated by choosing a Type II compensation (Type II, Type
II isolated with a Zener clamp, Type II isolated with inner loop) and setting RCOMP equal to RFBT. The
crossover frequency depends on the value of CCOMP. Set CHF equal to CCOMP.

www.ti.com Filter Designer
13 Filter Designer
The Filter Designer enables the user to design a differential mode filter, such as the input filter for a power
supply. The tool shows the Bode plot of the filter transfer function and the damping circuit and helps with finding
a desirable damping circuit (see example in Figure 13-1). In addition, the filter impedance with and without the
damping circuit is displayed to determine if the filter is stable or not.
Figure 13-1. Filter Designer Window
13.1 Impedances
ZIN/OUT s = ESRIN/OUT + s × ESLIN/OUT + s × C 1 (114)

IN/OUT
ZD s = RD + ESRD + s × ESLD + s ×1C (115)

D
ZF s = ESRF + s × ESLF + s ×1C (116)

F
2
CL = L1 × 2 × π1× SRF (117)
F
DCR + s × L
ZL s = (118)
s × CL × DCR + s × L + 1
13.2 Transfer Functions

Noise source to input source, load:
ZF s
GF s = (119)
ZF s + ZL s

Filter Designer www.ti.com
Input source, load to noise source:
ZD s × ZIN/OUT s
ZD s + ZIN/OUT s
GD s = (120)
ZD s × ZIN/OUT s
+ ZL s
ZD s + ZIN/OUT s
13.3 Filter Output Impedance

Undamped:
ZL s × ZIN/OUT s
Zout, undamped s = (121)
ZL s + ZIN/OUT s
Damped:
ZD s × ZIN/OUT s
ZL s ×
ZD s + ZIN/OUT s
Zout, damped s = (122)
ZD s × ZIN/OUT s
ZL s +
ZD s + ZIN/OUT s
13.4 Damping Factor

fdamp is the filter frequency of the filter inductor and the parallel input/output capacitor and damping capacitor
network.
XCin/out = 2 × π × f 1 × C (123)
damp IN/OUT
XCd = 2 × π × f 1 (124)
damp × CD
Effective impedance at fdamp .
2
ESRIN/OUT2 + XCin/out2 × RD + ESRD + XCd2
Zeff = (125)
2 2
RD + ESRD + ESRIN/OUT + XCd + XCin/out
Effective phase angle at fdamp .
XCin/out X XCin/out + XCd

φeff = tan−1 ESR + tan−1 R +Cd − tan−1 ESR (126)
IN/OUT D ESRD IN/OUT + RD + ESRD
Effective capacitance:
1
Ceff = (127)
2 × π × fdamp × Zeff × sin φeff
Effective ESR:
ESReff = Zeff × cos φeff (128)
Damping factor:
LF
DCR + ESReff Ceff
δ = 0.5 × + V (129)
LF
− I in
Ceff in

www.ti.com Additional Information
14 Additional Information
The following list contains references to additional information for various topics in this user's guide.
1. Mammano, Robert A.; Kollmann, Robert; Fundamentals of Power Supply Design, Chapter 13: Power-Supply
Construction, Texas Instruments, ISBN: 978-0-9985994-0-3 (see Section 4)
2. Dinwoodie, L.; Exposing the Inner Behavior of a Quasi-Resonant Flyback Converter, Texas Instruments
Power Supply Design Seminar SEM2000, 2012/2013 (see Section 5)
3. Keogh, Bernard; Cohen, Isaac; Flyback transformer design considerations for efficiency and EMI, Texas
Instruments Power Supply Design Seminar SEM2200, 2016/2017 (see Section 6)
4. Dinwoodie, Lisa; Design Review: Isolated 50-Watt Flyback Converter Using the UCC3809 Primary Side
Controller and the UC3965 Precision Reference and Error Amplifier (see Section 6)
5. Dinwoodie, Lisa; Application Report: UCC38C44 12-V Isolated Bias Supply (see Section 6)
6. Betten, John; Power Tips: Calculate an R-C snubber in seven steps (see Section 7)
7. Sheehan, R.; Diana, L.; Switch-mode power converter compensation made easy, Texas Instruments Power
Supply Design Seminar SEM2200, 2016/2017 (see Section 12.2)
8. Ridley, R.; A More Accurate Current-Mode Control Model, Texas Instruments Power Supply Design Seminar
SEM1400, 2000 (see Section 12.2)
15 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2017) to Revision B (February 2023) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Replaced several figures to represent the new UI. Updated equations for Capacitor Current Sharing
Calculator and Loop Calculator. Added new tools, the Load Step Calculator and Filter Designer.....................1
Changes from Revision * (November 2017) to Revision A (February 2018) Page

• Changed fourth line of Equation 13.................................................................................................................. 10

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2023, Texas Instruments Incorporated

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www.ti.

com Table of Contents

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 1

2 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

Figure 1-2. Topology Window for SEPIC

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 3

Figure 1-3. Graph Window for FET Q1 of a SEPIC Operating in CCM

4 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

2 FET Losses Calculator

Figure 2-1. FET Losses Calculator Window

Pcond = IFET, rms2 × RDS on (1)

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 5

Qgs − Qg th × Rg, total Qgd × Rg, total

Qgd × Rg, total Qgs − Qg th × Rg, total

Body Diode losses:

Ptotal = Pcond + Pswitching + PCoss (5)

Ptotal = Pcond + Pbody + PCoss (6)

Pdriver = Qg × VGS × f switch (7)

6 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

3 Load Step Calculator

Figure 3-1. Load Step Calculator Window

Current Mode Control (CMC):

Voltage Mode Control (VMC):

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 7

4 Capacitor Current Sharing Calculator

Figure 4-1. Capacitor Current Sharing Calculator

Zcap, n = ESRCn + i × 2 × π × f switch × ESLCn − 2 × π × f 1 (10)

8 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 9

5 AC/DC Bulk Capacitor Calculator

10 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

6 RCD-Snubber Calculator for Flyback Converters

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 11

Figure 6-1. RCD-Snubber Calculator for Flyback Converters Window

12 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

Starting Snubber resistance:

Starting Snubber capacitance:

Figure 7-1. RC-Snubber Calculator Window

• Measure the oscillation frequency f0 of the circuit without a snubber network.

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 13

Frequency shift ratio:

Initial Snubber capacitance:

Initial Snubber resistance:

14 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

8 Output Voltage Resistor Divider

Figure 8-1. Output Voltage Resistor Divider Calculator Window

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 15

Worst-case minimum output voltage:

Worst-case maximum output voltage:

16 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

9 Dynamic Analog Output Voltage Scaling

Figure 9-1. Dynamic Output Voltage Scaling Calculator Window

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 17

10 Dynamic Digital Output Voltage Scaling

Figure 10-1. Dynamic Output Voltage Scaling Calculator Window

18 Power Stage Designer SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023

Figure 11-1. Unit Converter Window

SLVUBB4B – NOVEMBER 2017 – REVISED FEBRUARY 2023 Power Stage Designer 19

Figure 12-1. Loop Calculator Window