Maity - Patra - 2016 - Tradeoffs Aware Design Procedure For An Adaptively Biased Capacitorless Low
Maity - Patra - 2016 - Tradeoffs Aware Design Procedure For An Adaptively Biased Capacitorless Low
Maity - Patra - 2016 - Tradeoffs Aware Design Procedure For An Adaptively Biased Capacitorless Low
I. INTRODUCTION
N recent years, the development of a capacitor-free regulator
I architecture [1]–[3] has gained considerable importance for
system-on-chip (SoC) applications because of its higher level of
integration possibility which saves a lot of board space and pin
count [4], [5]. The stability over a wide range of load current
[6]–[9], the fast transient response [10]–[19] and small quiescent Fig. 2. Various tradeoffs hexagon in the AB-LDR topology.
current [20]–[22] are the essential features of the regulator re-
quired for SoC applications. The widely used adaptively biased,
low dropout regulator (AB-LDR) architecture for such appli- current of the first and second stages has two components: the
cations is shown in Fig. 1 [6], [7]. In order to get better load fixed bias If and the adaptive bias Iv which is generated by
regulation, it uses three gain amplifier stages compensated by a the M94 − M95 − M96 path. The current Iv increases with Io
pole-splitting Miller capacitor Cm 1 . The PMOS power transis- as Iv = δIo , where δ is the adaptive bias (AB) ratio and it is
tor, M98 has the maximum current driving capability required equal to (A/M ). The adaptive biasing [7], [25], [26] scheme
by the load Io,m ax . Due to its large size, it has a higher parasitic maintains a very low quiescent current at low load conditions
gate to drain capacitance which is modeled as Cm 2 . This forms and expands the unity gain frequency (ωU G F ) of the regulator
a nested Miller type frequency compensation scheme [6], [7], at high load condition to achieve a faster transient response.
[23], [24]. The resistor divider consisting of R1 and R2 , level There are several issues that exist in the nested Miller com-
shifts the voltage Vref to the desired output voltage Vo . The bias pensated AB-LDR. So, different tradeoffs need to be considered
while optimizing the key performance parameters of the regula-
Manuscript received November 26, 2014; revised January 5, 2015; accepted tor as shown in Fig. 2. Most of the related literature only optimize
January 24, 2015. Date of publication February 3, 2015; date of current ver- a few of them. Therefore, the said topology underperforms as
sion September 21, 2015. Recommended for publication by Associate Editor
M. A. E. Andersen. a regulator. For example, [6] mainly focuses on the Q-peaking
A. Maity is with the Advanced Technology Development Center, Indian In- issue which restricts the low load current value Io,m in . The re-
stitute of Technology, Kharagpur 721302, India (e-mail: ashis.iit@gmail.com). lation between Q-peaking and If is still unexplored and hence
A. Patra is with the Department of Electrical Engineering, Indian Institute of
Technology, Kharagpur 721302, India (e-mail: amit.patra@ieee.org). an additional Q-reduction capacitor is required to improve the
Digital Object Identifier 10.1109/TPEL.2015.2398868 same. Moreover, as the Q-reduction capacitor only offers some
0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
370 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
The schematic of the conventional AB-LDR topology is To understand the Q-peaking problem from the two nondom-
shown in Fig. 3. Here, we consider Vref = Vo . So, a unity mode inant poles better, the pole movements through-out the load
configuration of the regulator with a feedback factor of 1 is current range need to be analyzed carefully. While moving from
formed by eliminating R1 and R2 as used in Fig. 1. This does the high to moderate load condition, the dc operating point of
not create much difference while developing and designing the M98 moves from the above-threshold to the sub-threshold
√ re-
regulator topology. The first stage consists of a differential input gion. In√the above-threshold region, gm ,98 ∝ Io and hence
pair with active current mirror load, the second stage is a differ- ωp3 ∝ Io . Whereas in the sub-threshold region, gm ,98 ∝ Io
ential to single ended amplifier and the third one is the power and hence ωp3 ∝ Io . If the same level of channel inversion as
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 371
response, the tail current of the error amplifier is more than where Vth is the threshold voltage of the corresponding transis-
the required value. Therefore, there is a scope of improving the tor. The sizes of remaining transistors M89 − M90 , M95 − M96
current efficiency at the high load condition. In a conventional are not very critical, rather their ratios are more important.
design approach, a smaller value of δ is mainly chosen not to Hence, the size of those transistors should be chosen based
degrade the current efficiency at high load condition. However, on the maximum current flowing through it at Io,m ax .
this lowers down the current in the low-to-mid range of the load
current. Therefore, the dynamic response is not optimized in the B. Fixing the Values of Cm 1 and K
conventional approach.
Once the sizing of all the transistors is done, the value of
Cm 1 is to be fixed corresponding to Io,m in . In the sub-threshold
III. PROPOSED DESIGN PROCEDURE region, gm ,81 = I81 /nn VT and gm ,87 = KI81 /np VT . Here, nn ,
In this section, the biasing considerations of the regulator np are the sub-threshold region swing parameters of NMOS
are thoroughly analyzed. To avoid the Q-peaking effect, i.e., and PMOS transistors, respectively, whereas VT is the thermal
Q ≤ 0.5, we have to maintain the relation ωp3 ≥ 4ωp2 even at voltage. From the first inequality of (5), one can get as follows:
the low load condition. Assuming all the poles are real, the phase 2.2Cm 2 np
margin of the overall system is given by [7] Cm 1 = (8)
Knn
ω ω
P M |Q ≤0.5 = 90o − tan−1 − tan−1
U GF U GF
(4) While increasing the value of K, one has to decrease the value
ωp2 ωp3 of Cm 1 by the same factor to keep ωU G F at the same location as
Also, the condition for achieving a phase margin of 60o is per (8). This gives a practical limitation for increasing the value
given by [29] of K. Thus, Cm 1 should not be so small that it is comparable to
the parasitic value which degrades the robustness of the design.
ωp2 ωp3
ωU G F ≤ ≤ The value of K should be chosen in such a way that Cm 1 does
2.2 8.8 not take much area and also it is less susceptible to the parasitic
gm ,81 (It ) gm ,87 (It ) gm ,98 (Io ) effects.
≤ ≤ (5)
Cm 1 2.2Cm 2 8.8Co,o
C. Fixing the Values of If and A
A. Sizing of the Transistors As discussed before, the poles track each other at high to
The power transistor M98 should be sized at Io,m ax in the moderate load condition. This continues until Io reaches a level
dropout condition where the overdrive voltage Vov = (Vin − Io,cric where Iv and If are comparable to each other. Of course,
Vo ). Here, M98 operates at the edge of the linear and the satu- this happens at a very low load especially, if the value of If is
ration regions. So, the aspect ratio of M98 is given by quite small. For Io ≥ Io,cric , the nondominant poles ωp2 and ωp3
W are real and hence, there is no Q-peaking effect in the frequency
2Io,m ax response of the regulator. The value of Io,cric is calculated from
= (6)
L 98 μp Cox Vov 2 the second inequality of (5) which gives
where μp is the mobility of the holes and Cox is the gate oxide C A
m2
If ≤ − Io (9)
capacitance per unit area. For achieving less Vov , we need to 2KCo,o M
increase the value of (W/L)98 and hence more silicon area is
required. (9) gives the relation between the value If and the achievable
The sizing ratio of the transistor pair M94 , M98 is 1 : M limit of Io to avoid Q-peaking effect from the nondominant
which is kept very high (M > 1000) to minimize the current complex poles. In other words, to achieve a minimum value of
through this path. The perfect matching of M94 and M98 is Io,cric , If ,m ax should not exceed the value given by
extremely difficult to achieve, although a good layout technique C A
m2
helps to minimize the mismatch between them. If ,m ax = − Io,cric (10)
2KCo,o M
Once the size of M98 is chosen optimally, the sizes of the
remaining transistors are chosen to set these devices at the For Io < Io,cric , If dominates over the value of Iv and hence
same current density which ensures the same level of chan- It ≈ If . In this region, ωU G F , ωp2 are almost independent of Io ,
nel inversion. This leads to (W/L)87 = AK(W/L)98 /2M whereas ωp3 ∝ Io . Hence, ωp3 comes closer to ωp2 and makes
and (W/L)83,84 = A(W/L)98 /2M . To minimize the current ωp3 < 4ωp2 . This creates a complex pole pair in the system. The
through M88 , (W/L)87 = 4(W/L)88 is chosen. An even ratio angular corner frequency and the Q-factor are approximated as
ensures good matching between them. The dc current balancing follows:
is confirmed by choosing (W/L)90 = 4(W/L)89 . However, the If Io
input transistors, M81,82 are realized by the NMOS devices. The ω0 ≈ (11)
np nn VT 2 Cm 2 Co,o
aspect ratio of M81 (and M82 ) is given by
W Aμp (W/L)98 (Vsg ,98 − |Vth,98 |)2 If nn Co,o
= (7) Q≈ (12)
L 81,82 2M μn (Vg s,81 − Vth,81 )2 Io np Cm 2
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 373
√ √
It is interesting to note that, ωo ∝ Io and Q ∝ 1/ Io at Io < insignificant compared to the Io factor in the denominator. So,
Io,cric region. Therefore, the Q-factor gradually increases with η will mostly depend on the factor “A(1 + 0.625K)/M ” and
the fall of Io . is maximized by reducing this expression. To satisfy the second
The values of K and A have a direct correlation with If ,m ax inequality in (5), one should have AK/M ≤ Cm 2 /2Co,o . Here,
and Io,cric as given in (10). For obtaining a positive value of neither Cm 2 nor Co,o is a design variable, as they are deter-
If ,m ax , the condition, Cm 2 /(2KCo ) > A/M has to be satisfied. mined from the specification of Io,m ax and the load parasitic,
Now, once the value of K is increased and that of A is decreased respectively. For Cm 2 = 3.6 pF and Co,o = 100 pF, the max-
by the same factor, the value of If ,m ax is also decreased by the imum value of the factor AK/M = 0.018. For Io,m ax = 100
same factor. In other words, to achieve a desired value of Io,cric , mA, the maximum contribution from 0.625AK/M factor it-
one has to reduce the value of the fixed current component of self is around 1.125 mA. Considering the contribution of other
the error amplifier. However, putting an arbitrarily high value factors in (13), the value of η will be much less than 99%. There-
of If If ,m ax pushes ωU G F to a higher frequency at low load fore, to maximize the value of η, one has to choose a much lower
condition. Since, it reduces the separation with ωp2 , a higher value of the factor AK/M . The values of A, K, M are already
value of Cm 1 is required to compensate the regulator at the low fixed for achieving better dynamic response as described previ-
load. What is more, the regulation loop becomes overcompen- ously. For the duration, [t2 − t3 ] and [t4 − t5 ], the excess bias
sated with a high value of Cm 1 which restricts the expansion current should be reduced to maximize η at high load condition.
of ωU G F at the high load condition. This leads to a poor load This is done by modifying the adaptive bias loop as shown in
transient response at the high load range. Also, a higher value Fig. 6. The aspect ratio of M97 is the same as that of M94 and
of If ,m ax significantly reduces the current efficiency at the low they carry the same current. A minimum current selector circuit
load condition. While fixing the value of If , A should be chosen [30] consisting of M77 − M80 , clamps the magnitude of Iv to
optimally as it also affects the dynamic response. ILIM IT at higher load condition and improves the current effi-
ciency. The value of ILIM IT has to be decided based on the ex-
D. Maximizing the Current Efficiency pected rise/fall time of the load current step. The sizing ratios of
M77 − M80 are chosen as (W/L)80 = (W/L)79 = (W/L)95
The total quiescent current consumption of the regulator with and (W/L)78 = N (W/L)77 . The dc value of ILIM IT adds a
the different sizing ratios chosen in Fig. 3 is (I89 + If + Iv + component on the overall quiescent current consumption of the
I90 + I95 ) = [ If (1 + 0.625K) + Io {1/M + (1 + 0.625K) regulator. To minimize it, a high value of N is preferred. There-
A/M }]. So, the current efficiency, η of the regulator is given in fore, in the proposed topology, the magnitude of Iv is determined
(13) below. as follows:
I AI
η= o 1 A
(13) Iv = Min.
o
, AN I LIM IT (14)
If (1 + 0.625K) + Io 1 + M + M (1 + 0.625K) M
Here, η is a monotonically increasing function with Io . At low So, for Io ≥ (AN I LIM IT ), the regulator acts as a fixed bias
load condition, the value of η decreases as the If factor term scheme.
dominates in the denominator of (13). So, reducing the value To determine the magnitude of ILIM IT , one has to review the
of If increases η. At high load condition, the value of If is current source and current sink capability of the error amplifier
374 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
TABLE I
ASPECT RATIOS (W/L) IN μm OF ALL THE TRANSISTORS USED IN DIFFERENT
DESIGN VARIANTS
TABLE II
COMPARISON BETWEEN THEORETICAL AND SIMULATED VALUES
OF Io , c ric FOR DIFFERENT VALUES OF If , m a x Fig. 9 shows the comparison of ωU G F and the phase margin
for the four cases listed in Table I. To reduce the excess bias
If , m a x Theoretical value of Simulated value of current at high load condition, ILIM IT = 222 nA is chosen for
Io , c r i c Io , c r i c “With-ILIM IT ” case. With ILIM IT = 222 nA, the adaptive bias
becomes ineffective above Io =10.6 mA. So, ωU G F and ωp2
10 nA 830 nA 900 nA
100 nA 8.3 μA 8 μA become static above Io =10.6 mA, although ωp3 dynamically
1 μA 83 μA 80 μA varies with Io . As a result, the phase margin is increased by 9o
10 μA 830 μA 700 μA (from 69o to 78o ) compared with the case “Without-ILIM IT ” at
Io = 100 mA.
Now, comparing the case “Reduced-AB” with the case “With-
exact value of the load current is calculated numerically here ILIM IT ”, although the value of ωU G F is almost the same at
based on (10). In the “Without-ILIM IT ” case, the values of two extreme points of the load range, it falls in the midrange
Co,o = 100 pF, Cm 2 = 3.6 pF, K = 1, M = 4000 and A = 24. of the load current as shown in Fig. 9(a). On the other hand,
Therefore, Io,cric = 83If ,m ax . Table II compares the theoreti- for the case “Over-compensated,” If is biased at 1 μA rather
cal and simulated values of Io,cric for different numerical val- than the optimal value of 100 nA. Then the value of the factor
ues of If ,m ax for stable operation. There is a reasonably good (If + AIo /2M ) becomes 1060 nA. So, one has to use 6.6 times
agreement between them. From Table II, it is quite clear that, higher value of Cm 1 , i.e., 60 pF to keep ωU G F at the same
the value of If ,m ax fixes the allowable limit of Io,cric . Be- location at the low load condition. Similarly, the value of K
low Io = Io,cric , the phase and gain margins fall drastically is decreased by the same factor to keep the location of ωp2
and the regulator enters into an unstable region. To cover unaltered. With Cm 1 = 60pF, ωU G F is decreased by 6.6 times
Io,m in = 10 μA, a value of If = 100 nA is chosen as the optimal at Io,m ax as shown in Fig. 9(a). So, the LDR is overcompensated
value. at high load condition and it has more phase margin as shown in
376 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
Fig. 12. Measured load transient response for a load step from 100 mA–10
μA with a fall time of 50 ns for the case “Without-IL IM IT ” for different values
of If .
Fig. 10. Comparison of load transient response for the four cases for a load
step of 1–100 mA with rise/fall time 100 ns.
Fig. 9(b). What is more, having a smaller value of K, the slew Fig. 13. Measured load transient response for a load steps of 100 mA–10 μA
with a fall time of (a) 50 ns for “With-IL IM IT ” (Ch-1), “Without-IL IM IT ”
rate is expected to reduce at the gate of M98 . All four designs (Ch-2), (b) 100 ns for “With-IL IM IT ” (Ch-4), “Without-IL IM IT ” (Ch-5).
have almost the same ωU G F of 70 kHz and the same phase
margin of 66o at Io = 10 μA. Also, at Io = 100 mA, they have
approximately the same ωU G F of 12 MHz and the phase margin
values of If . The optimal value of If = 100 nA shows more
is quite close to 80o for all these cases.
stable settling behavior compared to the case If = 200 nA and
Fig. 10 shows the comparison of the load transient response
If = 400 nA.
for these four cases. For 1–100 mA load step, the cases “With-
On the other hand, Fig. 13(a) and (b) compares the tran-
ILIM IT ” and “Without-ILIM IT ” have almost the same settling
sient response between the cases “With-ILIM IT ” and “Without-
behavior even with a faster rise/fall time of 100 ns. However,
ILIM IT ” for the extreme load step of 100 mA–10 μA with differ-
the other two cases “Reduced-AB” (smaller δ) and “Over-
ent fall times of 50 and 100 ns, respectively. For a fall time of 50
compensated” (higher If ) provide large settling time for both
ns, the overshoots for the cases “With-ILIM IT ” and “Without-
the load transients. Also, the amount of undershoot and over-
ILIM IT ” are +340 and +170 mV, respectively, whereas for a
shoot are also more for the latter two cases. Due to the optimal
fall time of 100 ns, their values are almost equal to +130 mV.
choices of δ and If in the cases “With/Without-ILIM IT ,” the
These results confirm that the consumption of high bias current
settling behavior is much better than the other two cases.
at maximum load current is not very useful to improve the dy-
namic response for a slower load step. Hence, a judicious value
V. EXPERIMENTAL RESULTS
of ILIM IT should be chosen to reduce the excess bias current.
To validate the proposed design procedure, the cases “With- For the other edge of load transient, i.e., 10 μA–100 mA, the
ILIM IT ” and “Without-ILIM IT ” have been fabricated in silicon effect of ILIM IT is minimal for the same rise time. For example,
in 0.18 μm CMOS technology. The microphotograph of the the amount of undershoot is −360 mV with 50-ns rise time of the
proposed regulator is shown in Fig. 11. It occupies an active load current for both the cases as shown in Fig. 14(a). However,
area of 0.07 mm2 excluding the PAD area. the case “Without-ILIM IT ,” provides a little faster settling time
Fig. 12 compares the load transient response for the extreme (50 ns versus 80 ns) compared to the case “With-ILIM IT .” For a
load step of 100 mA–10 μA with a fall time of 50 ns for different rise time of 100 ns, both the cases provide the same undershoot
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 377
Fig. 14. Measured load transient response for a load steps of 10 μA–100 mA
with a rise time of (a) 50 ns for “With-IL IM IT ” (Ch-1), “Without-IL IM IT ”
(Ch-2), (b) 100 ns for “With-IL IM IT ” (Ch-4), “Without-IL IM IT ”(Ch-5).
Fig. 18. Measured value of V o variation across (a) load current, (b) input
voltage. Fig. 19. Comparison of the (a) measured quiescent current, (b) measured
current efficiency across the load current for the cases “With-IL IM IT ” and
“Without-IL IM IT .”
TABLE III
PERFORMANCE COMPARISON WITH PREVIOUSLY REPORTED REGULATORS
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IEEE Appl. Power Electron. Conf. Exp., Mar. 2013, pp. 1366–1369. India, in 2002, and the M.S. degree from the Indian
[17] S. Pan and P. Jain, “Analysis of a high performance voltage regulator with Institute of Technology, Kharagpur, India, in 2009.
non-linear multi-mode control: Bandwidth and large transient response,” He is currently working toward the Ph.D. degree at
in Proc. IEEE Appl. Power Electron. Conf. Exp., Feb. 2010, pp. 499–506. Advanced Technology Development Center, Indian
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[19] W. Guo and P. Jain, “A predictive non-linear voltage mode control method sign Team. Then, during 2006–2008, he was working
to improve the transient performance of voltage regulator,” in Proc. IEEE as a Research Consultant in Advanced VLSI Design
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[20] C.-Y. Hsieh, C.-Y. Yang, and K.-H. Chen, “A low-dropout regulator with was with National Semiconductor, Tokyo, Japan, as a Senior Design Engineer.
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capacitorless LDO in 90-nm CMOS technology,” IEEE J. Solid-State
Circuits, vol. 45, no. 9, pp. 1896–1905, Sep. 2010.
[22] N. Kularatna, J. Fernando, K. Kankanamge, and X. Zhang, “A low fre-
quency supercapacitor circulation technique to improve the efficiency of Amit Patra (M’87) received the B.Tech., M.Tech.
linear regulators based on LDO ICs,” in Proc. IEEE Appl. Power Electron. and Ph.D. degrees from the Indian Institute of Tech-
Conf. Exp., Mar. 2011, pp. 1161–1165. nology, Kharagpur, India, in 1984, 1986 and 1990,
[23] W.-J. Huang and S.-I. Liu, “Capacitor-free low dropout regulators using respectively.
nested miller compensation with active resistor and 1-bit programmable During 1992–1993 and in 2000, he visited the
capacitor array,” IET Circuits, Devices Syst., vol. 2, no. 3, pp. 306–316, Ruhr-University, Bochum, Germany, as a Postdoc-
Jun. 2008. toral Fellow of the Alexander von Humboldt Foun-
[24] Y.-H. Lin, K.-L. Zheng, and K.-H. Chen, “Smooth pole tracking technique dation. He joined the Department of Electrical Engi-
by power MOSFET array in low-dropout regulators,” IEEE Trans. Power neering, Indian Institute of Technology, Kharagpur,
Electron., vol. 23, no. 5, pp. 2421–2427, Sep. 2008. in 1987 as a Faculty Member, and is currently a Pro-
[25] Y.-H. Lam and W.-H. Ki, “A 0.9 V 0.35 μm adaptively biased CMOS LDO fessor. He was the Professor-in-Charge, Advanced
regulator with fast transient response,” in Proc. Int. Solid-State Circuits VLSI Design Lab, IIT Kharagpur, during 2004–2007. Between 2007 and 2013,
Conf. Dig. Tech. Papers, Feb. 2008, pp. 442–626. he served as the Dean (Alumni Affairs and International Relations), IIT Kharag-
[26] V. Balan, “A low-voltage regulator circuit with self-bias to improve ac- pur. His current research interests include power management circuits, mixed-
curacy,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 365–368, Feb. signal VLSI design and embedded control systems. He has guided 17 doctoral
2003. students and published more than 200 research papers in various journals and
[27] C. Zhan and W.-H. Ki, “An output-capacitor-free adaptively biased low- conferences. He is the Coauthor of two research monographs entitled General
dropout regulator with subthreshold undershoot-reduction for SoC,” IEEE Hybrid Orthogonal Functions and Their Applications in Systems and Control
Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 1119–1131, May (New York, NY, USA: Springer-Verlag, 1996) and Nano-Scale CMOS Ana-
2012. log Circuits: Models and CAD Tools for High-Level Design (Boca Raton, FL,
[28] G. Palumbo and S. Pennisi, “Design methodology and advances in nested- USA: CRC Press, 2014). He has carried out more than 40 sponsored projects
miller compensation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., mostly in the areas of VLSI and power management circuits and control sys-
vol. 49, no. 7, pp. 893–903, Jul. 2002. tems. He has been consulted by National Semiconductor Corporation, Infineon
[29] K. N. Leung and P. Mok, “Analysis of multistage amplifier-frequency Technologies, Freescale Semiconductor and Maxim Corporation in the power
compensation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. management area. As the Professor-in-Charge of Advanced VLSI Design Lab-
48, no. 9, pp. 1041–1056, Sep. 2001. oratory, he also took the lead role in the formation of the AVLSI Consortium at
[30] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable IIT Kharagpur to increase collaboration between the industry and the academic
rail-to-rail constant-gm ,” in Proc. IEEE Int. Symp. Circuits Syst., Jun. community in the area of VLSI.
1997, pp. 1988–1991. Dr. Patra received the Young Engineer Award of the Indian National Academy
[31] C.-J. Park, M. Onabajo, and J. Silva-Martinez, “External capacitor-less of Engineering in 1996 and the Young Teachers Career Award from the All India
low drop-out regulator with 25 dB superior power supply rejection in Council for Technical Education in 1995. He has been a Young Associate of the
the 0.4-4 MHz range,” IEEE J. Solid-State Circuits, vol. 49, no. 2, Indian Academy of Sciences during 1992–1997. He is a Member of Institution
pp. 486–501, Feb. 2014. of Engineers (India) and a Life Member of the Systems Society of India.