1 MHz to 10 GHz, 45 dB

Log Detector/Controller
Data Sheet AD8319
FEATURES FUNCTIONAL BLOCK DIAGRAM
VPOS TADJ
Wide bandwidth: 1 MHz to 10 GHz
High accuracy: ±1.0 dB over temperature
GAIN SLOPE
45 dB dynamic range up to 8 GHz BIAS I V VSET

Stability over temperature: ±0.5 dB

Low noise measurement/controller output VOUT I V VOUT
Pulse response time (fall/rise): 6 ns/10 ns DET DET DET DET

Small footprint: 2 mm × 3 mm LFCSP INHI

CLPF

Supply operation: 3.0 V to 5.5 V @ 22 mA

INLO
Fabricated using high speed SiGe process

05705-001
COMM

APPLICATIONS Figure 1.

RF transmitter PA setpoint controls and level monitoring

Power monitoring in radiolink transmitters
RSSI measurement in base stations, WLANs, WiMAX,
and radars

GENERAL DESCRIPTION
The AD8319 is a demodulating logarithmic amplifier, capable The feedback loop through an RF amplifier is closed via VOUT,
of accurately converting an RF input signal to a corresponding the output of which regulates the output of the amplifier to a
decibel-scaled output. It employs the progressive compression magnitude corresponding to VSET. The AD8319 provides 0 V to
technique over a cascaded amplifier chain, each stage of which (VPOS − 0.1 V) output capability at the VOUT pin, suitable for
is equipped with a detector cell. The device can be used in either controller applications. As a measurement device, VOUT is
measurement or controller modes. The AD8319 maintains externally connected to VSET to produce an output voltage,
accurate log conformance for signals of 1 MHz to 8 GHz and VOUT, that is a decreasing linear-in-dB function of the RF input
provides useful operation to 10 GHz. The input dynamic range signal amplitude.
is typically 45 dB (re: 50 Ω) with error less than ±3 dB. The The logarithmic slope is −22 mV/dB, determined by the VSET
AD8319 has 6 ns/10 ns (fall time/rise time) response time that interface. The intercept is 15 dBm (re: 50 Ω, CW input) using
enables RF burst detection to a pulse rate of beyond 50 MHz. the INHI input. These parameters are very stable against supply
The device provides unprecedented logarithmic intercept stability and temperature variations.
vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V
is required to power the device. Current consumption is typically The AD8319 is fabricated on a SiGe bipolar IC process and is
22 mA, and it decreases to 200 µA when the device is disabled. available in a 2 mm × 3 mm, 8-lead LFCSP for an operating
temperature range of −40°C to +85°C.
The AD8319 can be configured to provide a control voltage to
a power amplifier or a measurement output from the VOUT
pin. Because the output can be used for controller applications,
special attention was paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to the VSET pin.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD8319 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Input Signal Coupling ................................................................ 11
Applications ....................................................................................... 1 Output Interface ......................................................................... 11
Functional Block Diagram .............................................................. 1 Setpoint Interface ....................................................................... 11
General Description ......................................................................... 1 Temperature Compensation of Output Voltage ..................... 12
Revision History ............................................................................... 2 Measurement Mode ................................................................... 12
Specifications..................................................................................... 3 Setting the Output Slope in Measurement Mode .................. 13
Absolute Maximum Ratings ............................................................ 5 Controller Mode ......................................................................... 13
ESD Caution .................................................................................. 5 Output Filtering .......................................................................... 15
Pin Configuration and Function Descriptions ............................. 6 Operation Beyond 8 GHz.......................................................... 16
Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 17
Theory of Operation ...................................................................... 10 Outline Dimensions ....................................................................... 19
Using the AD8319 .......................................................................... 11 Ordering Guide .......................................................................... 19
Basic Connections ...................................................................... 11

REVISION HISTORY
9/2017—Rev. C to Rev. D
Changed CP-8-1 to CP-8-23 ........................................ Throughout
Changes to Figure 2 .......................................................................... 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19

3/2013—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 18

4/2008—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Changes to Theory of Operation Section .................................... 10
Changes to Figure 22 and Setpoint Interface Section ................ 11

3/2007—Rev. 0 to Rev. A
Changes to Figure 9 .......................................................................... 8
Changes to Figure 22 and Setpoint Interface Section ................ 11
Changes to Measurement Mode Section ..................................... 12
Changes to Layout .......................................................................... 16
Changes to Layout .......................................................................... 17
Updated Outline Dimensions ....................................................... 18

10/2005—Revision 0: Initial Version

Rev. D | Page 2 of 19
Data Sheet AD8319

SPECIFICATIONS
VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted.

Table 1.
Parameter Conditions Min Typ Max Unit
SIGNAL INPUT INTERFACE INHI (Pin 1)
Specified Frequency Range 0.001 10 GHz
DC Common-Mode Voltage VPOS − 0.6 V
MEASUREMENT MODE VOUT (Pin 5) shorted to VSET (Pin 4),
sinusoidal input signal
f = 900 MHz RTADJ = 18 kΩ
Input Impedance 1500||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −3 dBm
Minimum Input Level ±1 dB error −43 dBm
Slope 1 −25 −22 −19.5 mV/dB
Intercept1 12 15 21 dBm
Output Voltage: High Power In PIN = −10 dBm 0.57 V
Output Voltage: Low Power In PIN = −40 dBm 1.25 V
f = 1.9 GHz RTADJ = 8 kΩ
Input Impedance 950||0.38 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −4 dBm
Minimum Input Level ±1 dB error −44 dBm
Slope1 −25 −22 −19.5 mV/dB
Intercept1 10 13 20 dBm
Output Voltage: High Power In PIN = −10 dBm 0.53 V
Output Voltage: Low Power In PIN = −35 dBm 1.19 V
f = 2.2 GHz RTADJ = 8 kΩ
Input Impedance 810||0.39 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −5 dBm
Minimum Input Level ±1 dB error −45 dBm
Slope1 −22 mV/dB
Intercept1 13 dBm
Output Voltage: High Power In PIN = −10 dBm 0.5 V
Output Voltage: Low Power In PIN = −35 dBm 1.18 V
f = 3.6 GHz RTADJ = 8 kΩ
Input Impedance 300||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 36 dB
Maximum Input Level ±1 dB error −6 dBm
Minimum Input Level ±1 dB error −46 dBm
Slope1 −22 mV/dB
Intercept1 10 dBm
Output Voltage: High Power In PIN = −10 dBm 0.46 V
Output Voltage: Low Power In PIN = −40 dBm 1.14 V

Rev. D | Page 3 of 19
AD8319 Data Sheet
Parameter Conditions Min Typ Max Unit
f = 5.8 GHz RTADJ = 500 Ω
Input Impedance 110||0.05 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −3 dBm
Minimum Input Level ±1 dB error −43 dBm
Slope1 −22 mV/dB
Intercept1 15 dBm
Output Voltage: High Power In PIN = −10 dBm 0.57 V
Output Voltage: Low Power In PIN = −40 dBm 1.25 V
f = 8.0 GHz RTADJ = open
Input Impedance 28||0.79 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 31 dB
Maximum Input Level ±1 dB error −1 dBm
Minimum Input Level ±1 dB error −41 dBm
Slope 2 −22 mV/dB
Intercept2 20 dBm
Output Voltage: High Power In PIN = −10 dBm 0.67 V
Output Voltage: Low Power In PIN = −40 dBm 1.34 V
OUTPUT INTERFACE VOUT (Pin 5)
Voltage Swing VSET = 0 V; RFIN = open VPOS − 0.1 V
VSET = 1.5 V; RFIN = open 10 mV
Output Current Drive VSET = 0 V; RFIN = open 10 mA
Small Signal Bandwidth RFIN = −10 dBm; from CLPF to VOUT 140 MHz
Output Noise RFIN = 2.2 GHz, −10 dBm, fNOISE = 100 kHz, 90 nV/√Hz
CLPF = open
Fall Time Input level = no signal to −10 dBm, 90% to 10%; 18 ns
CLPF = 8 pF
Input level = no signal to −10 dBm, 90% to 10%; 6 ns
CLPF = open; ROUT = 150 Ω
Rise Time Input level = −10 dBm to no signal, 10% to 90%; 20 ns
CLPF = 8 pF
Input level = −10 dBm to no signal, 10% to 90%; 10 ns
CLPF = open; ROUT = 150 Ω
Video Bandwidth (or Envelope Bandwidth) 50 MHz
VSET INTERFACE VSET (Pin 4)
Nominal Input Range RFIN = 0 dBm; measurement mode 0.35 V
RFIN = −40 dBm; measurement mode 1.23 V
Logarithmic Scale Factor −45 dB/V
Input Resistance RFIN = −20 dBm; controller mode; VSET = 1 V 40 kΩ
TADJ INTERFACE TADJ (Pin 6)
Input Resistance TADJ = 0.9 V, sourcing 50 µA 40 kΩ
Disable Threshold Voltage TADJ = open VPOS − 0.4 V
POWER INTERFACE VPOS (Pin 7)
Supply Voltage 3.0 5.5 V
Quiescent Current 18 22 30 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 60 µA/°C
Disable Current TADJ = VPOS 200 µA
1
Slope and intercept are determined by calculating the best fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency.
2
Slope and intercept are determined by calculating the best fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz.

Rev. D | Page 4 of 19
Data Sheet AD8319

ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Supply Voltage: VPOS 5.7 V
or any other conditions above those indicated in the operational
VSET Voltage 0 to VPOS
section of this specification is not implied. Operation beyond
Input Power (Single-Ended, re: 50 Ω) 12 dBm
the maximum operating conditions for extended periods may
Internal Power Dissipation 0.73 W
affect product reliability.
θJA 55°C/W
Maximum Junction Temperature 125°C
ESD CAUTION
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C

Rev. D | Page 5 of 19
AD8319 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

INHI 1 8 INLO

COMM 2 7 VPOS
AD8319
TOP VIEW
CLPF 3 (Not to Scale) 6 TADJ

VSET 4 5 VOUT

NOTES

05705-002
1. THE PAD IS INTERNALLY CONNECTED TO
COMM; SOLDER TO A LOW IMPEDANCE
GROUND PLANE.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1 INHI RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input.
2 COMM Device Common. Connect this pin to a low impedance ground plane.
3 CLPF Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth.
In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator.
4 VSET Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode.
5 VOUT Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB
representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or
VVA with a positive gain sense (increasing voltage increases gain).
6 TADJ Temperature Compensation Adjustment. Frequency dependent temperature compensation is set by connecting
a ground referenced resistor to this pin.
7 VPOS Positive Supply Voltage, 3.0 V to 5.5 V.
8 INLO RF Common for INHI. AC-coupled RF common.
EPAD The pad is internally connected to COMM; solder to a low impedance ground plane.

Rev. D | Page 6 of 19
Data Sheet AD8319

TYPICAL PERFORMANCE CHARACTERISTICS

VPOS = 3 V; T = 25°C, −40°C, +85°C; CLPF = 1000 pF; unless otherwise noted. Black: 25°C; Blue: −40°C; Red: +85°C. Error is calculated by
using the best fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted.
2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)
ERROR (dB)

VOUT (V)
VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0

05705-006
05705-003
–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
PIN (dBm) PIN (dBm)

Figure 3. VOUT and Log Conformance Error vs. Figure 6. VOUT and Log Conformance Error vs.
Input Amplitude at 900 MHz, RTADJ = 18 kΩ Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ

2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)

ERROR (dB)
VOUT (V)

VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0
05705-004

05705-007
–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
PIN (dBm) PIN (dBm)

Figure 4. VOUT and Log Conformance Error vs. Figure 7. VOUT and Log Conformance Error vs.
Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ Input Amplitude at 5.8 GHz, RTADJ = 500 Ω
2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)

ERROR (dB)
VOUT (V)

VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0
05705-005

05705-008

–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
PIN (dBm) PIN (dBm)

Figure 5. VOUT and Log Conformance Error vs. Figure 8. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm

Rev. D | Page 7 of 19
AD8319 Data Sheet
2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)
ERROR (dB)

VOUT (V)
VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0

05705-012
–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10

05705-009
PIN (dBm) PIN (dBm)

Figure 9. VOUT and Log Conformance Error vs. Input Amplitude at 900 MHz, Figure 12. VOUT and Log Conformance Error vs. Input Amplitude at 3.6 GHz,
Multiple Devices, RTADJ = 18 kΩ Multiple Devices, RTADJ = 8 kΩ

2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)
ERROR (dB)

VOUT (V)
VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0

05705-013
05705-010

–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
PIN (dBm) PIN (dBm)

Figure 10. VOUT and Log Conformance Error vs. Input Amplitude at 1.9 GHz, Figure 13. VOUT and Log Conformance Error vs. Input Amplitude at 5.8 GHz,
Multiple Devices, RTADJ = 8 kΩ Multiple Devices, RTADJ = 500 Ω

2.00 2.0 2.00 2.0

1.75 1.5 1.75 1.5

1.50 1.0 1.50 1.0

1.25 0.5 1.25 0.5

ERROR (dB)
ERROR (dB)

VOUT (V)
VOUT (V)

1.00 0 1.00 0

0.75 –0.5 0.75 –0.5

0.50 –1.0 0.50 –1.0

0.25 –1.5 0.25 –1.5

0 –2.0 0 –2.0
05705-014
05705-011

–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10

PIN (dBm) PIN (dBm)

Figure 11. VOUT and Log Conformance Error vs. Input Amplitude at 2.2 GHz, Figure 14. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
Multiple Devices, RTADJ = 8 kΩ Multiple Devices, RTADJ = Open, Error Calculated from
PIN = −34 dBm to PIN = −16 dBm

Rev. D | Page 8 of 19
Data Sheet AD8319
j1

j0.5 j2

10k

NOISE SPECTRAL DENSITY (nV/ Hz)

j0.2

–60dBm
1k
0
0.2 0.5 1 2
RF OFF

100MHz –20dBm
–10dBm
–j0.2 –40dBm
900MHz 100

1900MHz
0dBm
2200MHz

05705-018
8000MHz –j0.5 –j2
3600MHz
10
START FREQUENCY = 0.05GHz 1k 10k 100k 1M 10M
–j1

05705-015
STOP FREQUENCY = 10GHz FREQUENCY (Hz)
10000MHz 5800MHz

Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI Figure 18. Noise Spectral Density of Output vs. Frequency; CLPF = Open
(Impedance De-Embedded to Input Pins), Z0 = 50 Ω

∆ : 1.53V 10k
@ : 1.53V

NOISE SPECTRAL DENSITY (nV/ Hz)

1k

100
1
05705-016

05705-019
10
Ch1 500mV M2.00µs A CH1 420V 1k 10k 100k 1M 10M
T 29.60%
FREQUENCY (Hz)
Figure 16. Power On/Off Response Time; VP = 3.0 V; Figure 19. Noise Spectral Density of Output Buffer vs. Frequency (from CLPF
Input AC-Coupling Capacitors = 10 pF; CLPF = Open to VOUT); CLPF = 0.1 μF

2.00 2.0
CH1 RISE 3.3V
9.949ns 1.75 1.5
3.0V
CH1 FALL
6.032ns 1.50 3.6V 1.0

1.25 0.5
ERROR (dB)
VOUT (V)

1.00 0

0.75 –0.5

0.50 –1.0

0.25 –1.5
05705-017

1 0 –2.0
05705-020

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10
Ch1 200mV M20.0ns A CH1 1.04V
T 72.40% PIN (dBm)

Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm; Figure 20. VOUT Stability and Error vs. Supply Voltage at 1.9 GHz
CLPF = Open; RLOAD = 150 Ω When VPOS Varies by 10%

Rev. D | Page 9 of 19
AD8319 Data Sheet

THEORY OF OPERATION
The AD8319 is a five-stage demodulating logarithmic amplifier, The logarithmic function is approximated in a piecewise fashion
specifically designed for use in RF measurement and power control by five cascaded gain stages. (For a detailed explanation of the
applications at frequencies up to 10 GHz. A block diagram is logarithm approximation, refer to the AD8307 data sheet.) The
shown in Figure 21. Sharing much of its design with the AD8318 cells have a nominal voltage gain of 9 dB each and a 3 dB
logarithmic detector/controller, the AD8319 maintains tight bandwidth of 10.5 GHz. Using precision biasing, the gain is
intercept variability vs. temperature over a 40 dB range. Additional stabilized over temperature and supply variations. The overall
enhancements over the AD8318, such as reduced RF burst dc gain is high due to the cascaded nature of the gain stages.
response time of 6 ns to 10 ns, 22 mA supply current, and An offset compensation loop is included to correct for offsets
board space requirements of only 2 mm × 3 mm add to the low within the cascaded cells. At the output of each of the gain
cost and high performance benefits found in the AD8319. stages, a square-law detector cell is used to rectify the signal.
VPSO TADJ The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
GAIN SLOPE Along with the five gain stages and detector cells, an additional
BIAS V I VSET
detector is included at the input of the AD8319, providing a
40 dB dynamic range in total. After the detector currents are
I V VOUT
summed and filtered, the following function is formed at the
DET DET DET DET
CLPF summing node:
INHI
ID × log10(VIN/VINTERCEPT) (1)
INLO
where:
05705-021

COMM ID is the internally set detector current.

Figure 21. Block Diagram VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
A fully differential design, using a proprietary, high speed
the output voltage would be 0 V, if it were capable of going to 0 V).
SiGe process, extends high frequency performance. Input INHI
receives the signal with a low frequency impedance of nominally
500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB
log conformance error is typically 0 dBm (re: 50 Ω). The noise
spectral density referred to the input is 1.15 nV/√Hz, which is
equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth
or a noise power of −66 dBm (re: 50 Ω). This noise spectral
density sets the lower limit of the dynamic range. However, the
low end accuracy of the AD8319 is enhanced by specially shaping
the demodulating transfer characteristic to partially compensate
for errors due to internal noise. The common pin, COMM,
provides a quality low impedance connection to the PCB
ground. The package paddle, which is internally connected
to the COMM pin, should also be grounded to the PCB to
reduce thermal impedance from the die to the PCB.

Rev. D | Page 10 of 19
Data Sheet AD8319

USING THE AD8319

BASIC CONNECTIONS combines with the relatively high input impedance to give an
The AD8319 is specified for operation up to 10 GHz, as a result, adequate broadband 50 Ω match.
low impedance supply pins with adequate isolation between The coupling time constant, 50 × CC/2, forms a high-pass corner
functions are essential. A power supply voltage of between 3.0 V with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 =
and 5.5 V should be applied to VPOS. Power supply decoupling C2 = CC. Using the typical value of 47 nF, this high-pass corner
capacitors of 100 pF and 0.1 µF should be connected close to is ~68 kHz. In high frequency applications, fHP should be as
this power supply pin. large as possible to minimize the coupling of unwanted low
VS (3.0V TO 5.5V) frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
C5
for similar reasons. This should generally be placed at the generator
R2
0.1µF 0Ω side of the coupling capacitors, thereby lowering the required
capacitance value for a given high-pass corner frequency.
C4 SEE
100pF NOTE 1
VOUT OUTPUT INTERFACE
C2
47nF 8 7 6 5 The VOUT pin is driven by a PNP output stage. An internal 10 Ω
R1
INLO VPOS TADJ VOUT
R4 resistor is placed in series with the output and the VOUT pin.
AD8319 0Ω
52.3Ω The rise time of the output is limited mainly by the slew on
INHI COMM CLPF VSET
C1 1 2 3 4 CLPF. The fall time is an RC-limited slew given by the load
SIGNAL
47nF
SEE capacitance and the pull-down resistance at VOUT. There is
INPUT NOTE 2
an internal pull-down resistor of 1.6 kΩ. A resistive load at
NOTES
VOUT is placed in parallel with the internal pull-down resistor
05705-022

1. SEE THE TEMPERATURE COMPENSATION OF THE OUTPUT VOLTAGE

SECTION.
2. SEE THE OUTPUT FILTERING SECTION. to provide additional discharge current.
Figure 22. Basic Connections VPOS

CLPF
The paddle of the LFCSP is internally connected to COMM. 10Ω
For optimum thermal and electrical performance, the paddle +
VOUT

should be soldered to a low impedance ground plane. 0.8V

– 1200Ω

INPUT SIGNAL COUPLING

05705-024
400Ω
COMM
The RF input (INHI) is single-ended and must be ac-coupled.
Figure 24. Output Interface
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style To reduce the fall time, VOUT should be loaded with a resistive
capacitors for input frequencies of 1 MHz to 10 GHz. The load of <1.6 kΩ. For example, with an external load of 150 Ω,
coupling capacitors should be mounted close to the INHI and the AD8319 fall time is <7 ns.
INLO pins. The coupling capacitor values can be increased to
SETPOINT INTERFACE
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the The VSET input drives the high impedance input (40 kΩ) of an
internal 10 pF high-pass capacitor. The dc voltage on INHI and internal op amp. The VSET voltage appears across the internal
INLO is approximately one diode voltage drop below VPOS. 1.5 kΩ resistor to generate ISET. When a portion of VOUT is
applied to VSET, the feedback loop forces
VPOS CURRENT
−ID × log10(VIN/VINTERCEPT) = ISET (2)
5pF 5pF
If VSET = VOUT/2x, ISET = VOUT/(2x × 1.5 kΩ).
FIRST
18.7kΩ 18.7kΩ GAIN
STAGE
The result is
INHI
VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)
2kΩ A = 9dB
ISET
INLO 20kΩ VSET
VSET
05705-023

Gm OFFSET
STAGE COMP

Figure 23. Input Interface 20kΩ

1.5kΩ
Although the input can be reactively matched, in general, this is not
05705-025

necessary. An external 52.3 Ω shunt resistor (connected on the COMM COMM

signal side of the input coupling capacitors, as shown in Figure 22) Figure 25. VSET Interface

Rev. D | Page 11 of 19
AD8319 Data Sheet
The slope is given by −ID × 2x × 1.5 kΩ = −22 mV/dB × x. For 2.00 2.0
VOUT 25°C
example, if a resistor divider to ground is used to generate a VSET 1.75 ERROR 25°C 1.5
voltage of VOUT/2, x = 2. The slope is set to −880 mV/decade or
−44 mV/dB. 1.50 1.0

TEMPERATURE COMPENSATION OF OUTPUT 1.25 0.5

ERROR (dB)
VOUT (V)
VOLTAGE 1.00 0

The primary component of the variation in VOUT vs. temperature, 0.75 –0.5
as the input signal amplitude is held constant is the drift of the
intercept. This drift is also a weak function of the input signal 0.50
RANGE FOR
–1.0

frequency; therefore, provision is made for optimization of 0.25

CALCULATION OF

05705-027
–1.5
SLOPE AND INTERCEPT
internal temperature compensation at a given frequency by
providing the TADJ pin. 0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
INTERCEPT
AD8319 PIN (dBm)
VINTERNAL
ICOMP Figure 27. Typical Output Voltage vs. Input Signal

TADJ The output voltage vs. input signal voltage of the AD8319 is
linear-in-dB over a multidecade range. The equation for this
RTADJ
function is
VOUT = X × VSLOPE/DEC × log10(VIN/VINTERCEPT) =
05705-026

1.5kΩ
X × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT) (3)
COMM COMM
where:
Figure 26. TADJ Interface
X is the feedback factor in VSET = VOUT/X.
RTADJ is connected between this pin and ground. The value of VSLOPE/DEC is nominally −440 mV/decade or −22 mV/dB.
this resistor partially determines the magnitude of an analog VINTERCEPT is the x-axis intercept of the linear-in-dB portion of
correction coefficient, which is used to reduce intercept drift. the VOUT vs. PIN curve (see Figure 27).
The relationship between output temperature drift and VINTERCEPT is 15 dBm (2 dBV) for a sinusoidal input signal.
frequency is not linear and cannot be easily modeled. As a An offset voltage, VOFFSET, of 0.35 V is internally added to the
result, experimentation is required to choose the correct detector signal, so that the minimum value for VOUT is
TADJ resistor. Table 4 shows the recommended values for X × VOFFSET, so for X = 1, minimum VOUT is 0.35 V.
some commonly used frequencies.
The slope is very stable vs. process and temperature variation.
Table 4. Recommended RTADJ Resistor Values When base-10 logarithms are used, VSLOPE/DEC represents the
Frequency Recommended RTADJ volts/decade. A decade corresponds to 20 dB; VSLOPE/DEC/20 =
50 MHz 18 kΩ VSLOPE/dB represents the slope in volts/dB.
100 MHz 18 kΩ As noted in the Equation 1 and Equation 2, the VOUT voltage has
900 MHz 18 kΩ a negative slope. This is also the correct slope polarity to control
1.8 GHz 8 kΩ the gain of many power amplifiers in a negative feedback configu-
1.9 GHz 8 kΩ ration. Because both the slope and intercept vary slightly with
2.2 GHz 8 kΩ frequency, it is recommended to refer to the Specifications
3.6 GHz 8 kΩ section for application-specific values for the slope and intercept.
5.3 GHZ 500 Ω
Although demodulating log amps respond to input signal
5.8 GHz 500 Ω
voltage, not input signal power, it is customary to discuss the
8 GHz Open
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z0, must be
MEASUREMENT MODE known to convert voltages to their corresponding power levels.
When the VOUT voltage or a portion of the VOUT voltage is fed Equation 4 to Equation 6 are used to perform this conversion.
back to the VSET pin, the device operates in measurement
P(dBm) = 10 × log10(Vrms2/(Z0 × 1 mW)) (4)
mode. As seen in Figure 27, the AD8319 has an offset voltage,
a negative slope, and a VOUT measurement intercept at the high P(dBV) = 20 × log10(Vrms/1 Vrms) (5)
end of its input signal range. P(dBm) = P(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms ) 2
(6)

Rev. D | Page 12 of 19
Data Sheet AD8319
For example, PINTERCEPT for a sinusoidal input signal expressed in To operate in controller mode, the link between VSET and
terms of dBm (decibels referred to 1 mW), in a 50 Ω system is VOUT is broken. A setpoint voltage is applied to the VSET
PINTERCEPT(dBm) = input; VOUT is connected to the gain control terminal of the
PINTERCEPT(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2) = VGA and the RF input of the detector is connected to the
2 dBV − 10 × log10(50×10-3) = 15 dBm (7) output of the VGA (usually using a directional coupler and
some additional attenuation). Based on the defined relationship
For a square wave input signal in a 200 Ω system between VOUT and the RF input signal when the device is in
PINTERCEPT = −1 dBV − 10 × log10[(200 Ω × 1 mW/1Vrms2)] = measurement mode, the AD8319 adjusts the voltage on VOUT
6 dBm (VOUT is now an error amplifier output) until the level at the
Further information on the intercept variation dependence upon RF input corresponds to the applied VSET. When the AD8319
waveform can be found in the AD8313 and AD8307 data sheets. operates in controller mode, there is no defined relationship
between the VSET and VOUT voltages; VOUT settles to a value that
SETTING THE OUTPUT SLOPE IN MEASUREMENT results in the correct input signal level appearing at INHI/INLO.
MODE
For this output power control loop to be stable, a ground-
To operate in measurement mode, VOUT must be connected to referenced capacitor must be connected to the CLPF pin. This
VSET. Connecting VOUT directly to VSET yields the nominal capacitor, CFLT, integrates the error signal (in the form of a
logarithmic slope of −22 mV/dB. The output swing corresponding current) to set the loop bandwidth and ensure loop stability.
to the specified input range is then 0.35 V to 1.5 V. The slope Further details on control loop dynamics can be found in the
and output swing can be increased by placing a resistor divider AD8315 data sheet.
between VOUT and VSET (that is, one resistor from VOUT to
VSET and one resistor from VSET to ground). The input imped-
ance of VSET is 40 kΩ. Slope setting resistors should be kept below VGA/VVA RFIN

20 kΩ to prevent this input impedance from affecting the DIRECTIONAL

COUPLER
resulting slope. If two equal resistors are used (for example, GAIN
CONTROL
10 kΩ/10 kΩ), the slope doubles to −44 mV/dB. ATTENUATOR
VOLTAGE

47nF VOUT
AD8319
INHI
VOUT –44mV/dB
52.3Ω AD8319
10kΩ
VSET DAC
VSET INLO
10kΩ 47nF CLPF
05705-028

05705-029
CFLT

Figure 28. Increasing the Slope

Figure 29. Controller Mode
CONTROLLER MODE
Decreasing VSET, which corresponds to demanding a higher
The AD8319 provides a controller mode feature at the VOUT signal from the VGA, increases VOUT. The gain control voltage
pin. Using VSET for the setpoint voltage, it is possible for the of the VGA must have a positive sense. A positive control voltage
AD8319 to control subsystems, such as power amplifiers (PAs), to the VGA increases the gain of the device.
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs) that have output power that increases monotonically
with respect to their gain control signal.

Rev. D | Page 13 of 19
AD8319 Data Sheet
+5V
+5V

RF INPUT 120nH 120nH RF OUTPUT

SIGNAL SIGNAL
VPOS COMM
100pF 100pF
INHI OPHI
ADL5330 100pF
INLO OPLO
100pF DIRECTIONAL
GAIN COUPLER

4.12kΩ ATTENUATOR
10kΩ +5V

SETPOINT
VOLTAGE VOUT VPOS 47nF
DAC VSET INHI
AD8319 52.3Ω
LOG AMP
CLPF INLO
1nF TADJ COMM 47nF

18kΩ

05705-030
Figure 30. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330

The basic connections for operating the AD8319 in an automatic The AGC loop is capable of controlling signals of ~40 dB. This
gain control (AGC) loop with the ADL5330 are shown in range limitation is due to the dynamic range of the AD8319.
Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a Using a wider dynamic range detector, such as the AD8317,
large gain control range of 60 dB with ±0.5 dB gain stability. AD8318, or AD8362, allows for the full 60 dB range of the
This configuration is similar to Figure 29. ADL5330 to be used. The performance over temperature is
The gain of the ADL5330 is controlled by the output pin of the most accurate over the highest power range, where it is generally
AD8319. This voltage, VOUT, has a range of 0 V to near VPOS. To most critical. Across the top 40 dB range of output power, the
avoid overdrive recovery issues, the AD8319 output voltage can linear conformance error is well within ±0.5 dB over temperature.
30 4
be scaled down using a resistive divider to interface with the 0 V
to 1.4 V gain control range of the ADL5330. 20 3

A coupler/attenuation of 21 dB is used to match the desired 10 2

OUTPUT POWER (dBm)

maximum output power from the VGA to the top end of the
linear operating range of the AD8319 (approximately −5 dBm 0 1

ERROR (dB)
at 900 MHz). –10 0

Figure 31 shows the transfer function of the output power vs.

–20 –1
the VSET voltage over temperature for a 900 MHz sine wave with
an input power of −1.5 dBm. Note that the power control of the –30 –2

AD8319 has a negative sense. Decreasing VSET, which corresponds

–40 –3
to demanding a higher signal from the ADL5330, increases gain.
–50 –4
05705-031

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
SETPOINT VOLTAGE (V)

Figure 31. ADL5330 Output Power vs. AD8319 Setpoint Voltage, PIN = −1.5 dBm

Rev. D | Page 14 of 19
Data Sheet AD8319
For the AGC loop to remain in equilibrium, the AD8319 must Calibration in controller mode is similar to the method used
track the envelope of the output signal of the ADL5330 and in measurement mode. A simple two-point calibration can be
provide the necessary voltage levels to the gain control input done by applying two known VSET voltages or DAC codes and
of the ADL5330. Figure 32 shows an oscilloscope screenshot of measuring the output power from the VGA. Slope and intercept
the AGC loop depicted in Figure 30. A 100 MHz sine wave with can then be calculated by:
50% AM modulation is applied to the ADL5330. The output signal Slope = (VSET1 − VSET2)/(POUT1 − POUT2) (8)
from the VGA is a constant envelope sine wave with amplitude
corresponding to a setpoint voltage at the AD8319 of 1.3 V. Intercept = POUT1 − VSET1/Slope (9)
The gain control response of the AD8319 to the changing input VSETx = Slope × (POUTx − Intercept) (10)
envelope is also shown. More information on the use of the ADL5330 in AGC applications
AM MODULATED INPUT can be found in the ADL5330 data sheet.
OUTPUT FILTERING
1
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.
The nominal output video bandwidth of 50 MHz can be reduced
AD8319 OUTPUT
by connecting a ground-referenced capacitor (CFLT) to the CLPF
pin, as shown in Figure 34. This is generally done to reduce output
3 ripple (at twice the input frequency for a symmetric input
waveform such as sinusoidal signals).
05705-032

2 ADL5330 OUTPUT
CH1 200mV Ch2 200mV M2.00ms A Ch2 1.03V AD8319
Ch3 100mVΩ T 0.00000 s ILOG
Figure 32. Oscilloscope Screenshot Showing an AM Modulated Input Signal +4
VOUT
and the Response from the AD8319
1.5kΩ 3.5pF
Figure 33 shows the response of the AGC RF output to a pulse CLPF

05705-037
CFLT
on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop
responds with an RF burst. In this configuration, the input signal to
the ADL5330 is a 1 GHz sine wave at a power level of −15 dBm.
T Figure 34. Lowering the Postdemodulation Bandwidth
AD8319 VSET PULSE
CFLT is selected by
1
C FLT 
1
2π  1.5 kΩ  Video Bandwidth   3.5 pF (11)

The video bandwidth should typically be set to a frequency

equal to approximately one-tenth the minimum input frequency.
This ensures that the output ripple of the demodulated log
ADL5330 OUTPUT
3
output, which is at twice the input frequency, is well filtered.
In many log amp applications, it may be necessary to lower the
05705-033

corner frequency of the postdemodulation filtering to achieve

low output ripple while maintaining a rapid response time to
Ch1 2.00V M10.µs A Ch1 2.60V
Ch3 50mVΩ T 179.800µs changes in signal level. An example of a four-pole active filter
Figure 33. Oscilloscope Screenshot Showing the is shown in the AD8307 data sheet.
Response Time of the AGC Loop

Response time and the amount of signal integration are

controlled by CFLT. This functionality is analogous to the
feedback capacitor around an integrating amplifier. While it
is possible to use large capacitors for CFLT, in most applications,
values under 1 nF provide sufficient filtering.

Rev. D | Page 15 of 19
AD8319 Data Sheet
OPERATION BEYOND 8 GHz Implementing an impedance match for frequencies beyond
The AD8319 is specified for operation up to 8 GHz, but it provides 8 GHz can improve the sensitivity of the AD8319 and
useful measurement accuracy over a reduced dynamic range of measurement range.
up to 10 GHz. Figure 35 shows the performance of the AD8319 Operation beyond 10 GHz is possible, but part-to-part
over temperature at 10 GHz when the device is configured as variation, most notably in the intercept, becomes significant.
shown in Figure 22. Dynamic range is reduced at this frequency,
but the AD8319 does provide 30 dB of measurement range within
±3 dB of linearity error.
2.0 5

1.8 4

1.6 3

1.4 2

ERROR (dB)
1.2 1
VOUT (V)

1.0 0

0.8 –1

0.6 –2

0.4 –3

0.2 –4

0 –5
05705-038

–40 –35 –30 –25 –20 –15 –10 –5 0 5

PIN (dBm)

Figure 35. VOUT and Log Conformance Error vs. Input Amplitude at 10 GHz,
Multiple Devices, RTADJ = Open, CLPF = 1000 pF

Rev. D | Page 16 of 19
Data Sheet AD8319

EVALUATION BOARD
VPOS TADJ
GND
C4
R5
0.1µF 200Ω
VOUT_ALT
C5
R4
R7 OPEN
100pF
C1 OPEN
R6
VOUT
47nF 1kΩ CL RL
8 7 6 5 OPEN OPEN
INLO VPOS TADJ VOUT
R1 R2
52.3Ω AD8319 0Ω
INHI COMM CLPF VSET
1 2 3 4
RFIN C2
C3
8.2pF VSET
47nF R3
OPEN

05705-034
Figure 36. Evaluation Board Schematic (Rev. A)

Table 5. Evaluation Board (Rev. A) Configuration Options

Component Function Default Conditions
VPOS, GND Supply and Ground Connections. Not applicable
R1, C1, C2 Input Interface. R1 = 52.3 Ω (Size 0402)
The 52.3 Ω resistor in Position R1 combines with the internal input impedance of the AD8319 to C1 = 47 nF (Size 0402)
give a broadband input impedance of approximately 50 Ω. Capacitor C1 and Capacitor C2 are dc C2 = 47 nF (Size 0402)
blocking capacitors. A reactive impedance match can be implemented by replacing R1 with an
inductor and C1 and C2 with appropriately valued capacitors.
R5, R7 Temperature Compensation Interface. R5 = 200 Ω (Size 0402)
The internal temperature compensation network is optimized for input signals up to 3.6 GHz when R7 = open (Size 0402)
R7 is 10 kΩ. This circuit can be adjusted to optimize performance for other input frequencies
by changing the value of the resistor in Position R7. See Table 4 for specific RTADJ resistor values.
R2, R3, R4, Output Interface—Measurement Mode. R2 = 0 Ω (Size 0402)
R6, RL, CL In measurement mode, a portion of the output voltage is fed back to the VSET pin via R2. The R3 = open (Size 0402)
magnitude of the slope of the VOUT output voltage response can be increased by reducing the R4 = open (Size 0402)
portion of VOUT that is fed back to VSET. R6 can be used as a back-terminating resistor or as part R6 = 1 kΩ (Size 0402)
of a single-pole, low-pass filter. RL = CL = open (Size 0402)
R2, R3 Output Interface—Controller Mode. R2 = open (Size 0402)
In this mode, R2 must be open. In controller mode, the AD8319 can control the gain of an R3 = open (Size 0402)
external component. A setpoint voltage is applied to the VSET pin, the value of which corresponds
to the desired RF input signal level applied to the AD8319 RF input. A sample of the RF output
signal from this variable-gain component is selected, typically via a directional coupler, and
applied to AD8319 RF input. The voltage at the VOUT pin is applied to the gain control of the
variable gain element. A control voltage is applied to the VSET pin. The magnitude of the
control voltage can optionally be attenuated via the voltage divider comprising R2 and R3, or a
capacitor can be installed in Position R3 to form a low-pass filter along with R2.
C4, C5 Power Supply Decoupling. C4 = 0.1 µF (Size 0603)
The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to C5 = 100 pF (Size 0402)
the AD8319 and a 0.1 µF capacitor placed physically close to the power supply input pin.
C3 Filter Capacitor. C3 = 8.2 pF (Size 0402)
The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a
capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall
time of the AD8319 for pulsed input signals. See the Output Filtering section for more details.

Rev. D | Page 17 of 19
AD8319 Data Sheet

05705-036
05705-035

Figure 37. Component Side Layout Figure 38. Component Side Silkscreen

Rev. D | Page 18 of 19
Data Sheet AD8319

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)

3.25 1.89
3.00 1.74
0.55
2.75 1.59
0.40
0.30 0.20 MIN
2.25 5 8

2.00 EXPOSED PAD

0.60
1.75
0.45 4
1
0.30
TOP VIEW BOTTOM VIEW
PIN 1 INDEX PIN 1
INDIC ATOR AREA OPTIONS
AREA 0.50 BSC (SEE DETAIL A)

0.80 FOR PROPER CONNECTION OF

0.75 0.05 MAX THE EXPOSED PAD, REFER TO
0.70 THE PIN CONFIGURATION AND
0.02 NOM FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
0.30
SEATING 0.23 0.203 REF

02-13-2017-A
PLANE
0.18
PKG-004467

Figure 39. 8-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 2 mm Body and 0.75 mm Package Height
(CP-8-23)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Branding
AD8319ACPZ-R7 –40°C to +85°C 8-Lead LFCSP CP-8-23 Q2
AD8319ACPZ-R2 –40°C to +85°C 8-Lead LFCSP CP-8-23 Q2
AD8319ACPZ-WP –40°C to +85°C 8-Lead LFCSP, Waffle Pack CP-8-23 Q2
AD8319-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05705-0-9/17(D)

Rev. D | Page 19 of 19